xref: /openbmc/linux/drivers/ata/sata_qstor.c (revision b6dcefde)
1 /*
2  *  sata_qstor.c - Pacific Digital Corporation QStor SATA
3  *
4  *  Maintained by:  Mark Lord <mlord@pobox.com>
5  *
6  *  Copyright 2005 Pacific Digital Corporation.
7  *  (OSL/GPL code release authorized by Jalil Fadavi).
8  *
9  *
10  *  This program is free software; you can redistribute it and/or modify
11  *  it under the terms of the GNU General Public License as published by
12  *  the Free Software Foundation; either version 2, or (at your option)
13  *  any later version.
14  *
15  *  This program is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *  GNU General Public License for more details.
19  *
20  *  You should have received a copy of the GNU General Public License
21  *  along with this program; see the file COPYING.  If not, write to
22  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23  *
24  *
25  *  libata documentation is available via 'make {ps|pdf}docs',
26  *  as Documentation/DocBook/libata.*
27  *
28  */
29 
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/device.h>
38 #include <scsi/scsi_host.h>
39 #include <linux/libata.h>
40 
41 #define DRV_NAME	"sata_qstor"
42 #define DRV_VERSION	"0.09"
43 
44 enum {
45 	QS_MMIO_BAR		= 4,
46 
47 	QS_PORTS		= 4,
48 	QS_MAX_PRD		= LIBATA_MAX_PRD,
49 	QS_CPB_ORDER		= 6,
50 	QS_CPB_BYTES		= (1 << QS_CPB_ORDER),
51 	QS_PRD_BYTES		= QS_MAX_PRD * 16,
52 	QS_PKT_BYTES		= QS_CPB_BYTES + QS_PRD_BYTES,
53 
54 	/* global register offsets */
55 	QS_HCF_CNFG3		= 0x0003, /* host configuration offset */
56 	QS_HID_HPHY		= 0x0004, /* host physical interface info */
57 	QS_HCT_CTRL		= 0x00e4, /* global interrupt mask offset */
58 	QS_HST_SFF		= 0x0100, /* host status fifo offset */
59 	QS_HVS_SERD3		= 0x0393, /* PHY enable offset */
60 
61 	/* global control bits */
62 	QS_HPHY_64BIT		= (1 << 1), /* 64-bit bus detected */
63 	QS_CNFG3_GSRST		= 0x01,     /* global chip reset */
64 	QS_SERD3_PHY_ENA	= 0xf0,     /* PHY detection ENAble*/
65 
66 	/* per-channel register offsets */
67 	QS_CCF_CPBA		= 0x0710, /* chan CPB base address */
68 	QS_CCF_CSEP		= 0x0718, /* chan CPB separation factor */
69 	QS_CFC_HUFT		= 0x0800, /* host upstream fifo threshold */
70 	QS_CFC_HDFT		= 0x0804, /* host downstream fifo threshold */
71 	QS_CFC_DUFT		= 0x0808, /* dev upstream fifo threshold */
72 	QS_CFC_DDFT		= 0x080c, /* dev downstream fifo threshold */
73 	QS_CCT_CTR0		= 0x0900, /* chan control-0 offset */
74 	QS_CCT_CTR1		= 0x0901, /* chan control-1 offset */
75 	QS_CCT_CFF		= 0x0a00, /* chan command fifo offset */
76 
77 	/* channel control bits */
78 	QS_CTR0_REG		= (1 << 1),   /* register mode (vs. pkt mode) */
79 	QS_CTR0_CLER		= (1 << 2),   /* clear channel errors */
80 	QS_CTR1_RDEV		= (1 << 1),   /* sata phy/comms reset */
81 	QS_CTR1_RCHN		= (1 << 4),   /* reset channel logic */
82 	QS_CCF_RUN_PKT		= 0x107,      /* RUN a new dma PKT */
83 
84 	/* pkt sub-field headers */
85 	QS_HCB_HDR		= 0x01,   /* Host Control Block header */
86 	QS_DCB_HDR		= 0x02,   /* Device Control Block header */
87 
88 	/* pkt HCB flag bits */
89 	QS_HF_DIRO		= (1 << 0),   /* data DIRection Out */
90 	QS_HF_DAT		= (1 << 3),   /* DATa pkt */
91 	QS_HF_IEN		= (1 << 4),   /* Interrupt ENable */
92 	QS_HF_VLD		= (1 << 5),   /* VaLiD pkt */
93 
94 	/* pkt DCB flag bits */
95 	QS_DF_PORD		= (1 << 2),   /* Pio OR Dma */
96 	QS_DF_ELBA		= (1 << 3),   /* Extended LBA (lba48) */
97 
98 	/* PCI device IDs */
99 	board_2068_idx		= 0,	/* QStor 4-port SATA/RAID */
100 };
101 
102 enum {
103 	QS_DMA_BOUNDARY		= ~0UL
104 };
105 
106 typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
107 
108 struct qs_port_priv {
109 	u8			*pkt;
110 	dma_addr_t		pkt_dma;
111 	qs_state_t		state;
112 };
113 
114 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
115 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
117 static int qs_port_start(struct ata_port *ap);
118 static void qs_host_stop(struct ata_host *host);
119 static void qs_qc_prep(struct ata_queued_cmd *qc);
120 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
121 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
122 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
123 static u8 qs_bmdma_status(struct ata_port *ap);
124 static void qs_freeze(struct ata_port *ap);
125 static void qs_thaw(struct ata_port *ap);
126 static int qs_prereset(struct ata_link *link, unsigned long deadline);
127 static void qs_error_handler(struct ata_port *ap);
128 
129 static struct scsi_host_template qs_ata_sht = {
130 	ATA_BASE_SHT(DRV_NAME),
131 	.sg_tablesize		= QS_MAX_PRD,
132 	.dma_boundary		= QS_DMA_BOUNDARY,
133 };
134 
135 static struct ata_port_operations qs_ata_ops = {
136 	.inherits		= &ata_sff_port_ops,
137 
138 	.check_atapi_dma	= qs_check_atapi_dma,
139 	.bmdma_stop		= qs_bmdma_stop,
140 	.bmdma_status		= qs_bmdma_status,
141 	.qc_prep		= qs_qc_prep,
142 	.qc_issue		= qs_qc_issue,
143 
144 	.freeze			= qs_freeze,
145 	.thaw			= qs_thaw,
146 	.prereset		= qs_prereset,
147 	.softreset		= ATA_OP_NULL,
148 	.error_handler		= qs_error_handler,
149 	.post_internal_cmd	= ATA_OP_NULL,
150 	.lost_interrupt		= ATA_OP_NULL,
151 
152 	.scr_read		= qs_scr_read,
153 	.scr_write		= qs_scr_write,
154 
155 	.port_start		= qs_port_start,
156 	.host_stop		= qs_host_stop,
157 };
158 
159 static const struct ata_port_info qs_port_info[] = {
160 	/* board_2068_idx */
161 	{
162 		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
163 				  ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
164 		.pio_mask	= ATA_PIO4_ONLY,
165 		.udma_mask	= ATA_UDMA6,
166 		.port_ops	= &qs_ata_ops,
167 	},
168 };
169 
170 static const struct pci_device_id qs_ata_pci_tbl[] = {
171 	{ PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
172 
173 	{ }	/* terminate list */
174 };
175 
176 static struct pci_driver qs_ata_pci_driver = {
177 	.name			= DRV_NAME,
178 	.id_table		= qs_ata_pci_tbl,
179 	.probe			= qs_ata_init_one,
180 	.remove			= ata_pci_remove_one,
181 };
182 
183 static void __iomem *qs_mmio_base(struct ata_host *host)
184 {
185 	return host->iomap[QS_MMIO_BAR];
186 }
187 
188 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
189 {
190 	return 1;	/* ATAPI DMA not supported */
191 }
192 
193 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
194 {
195 	/* nothing */
196 }
197 
198 static u8 qs_bmdma_status(struct ata_port *ap)
199 {
200 	return 0;
201 }
202 
203 static inline void qs_enter_reg_mode(struct ata_port *ap)
204 {
205 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
206 	struct qs_port_priv *pp = ap->private_data;
207 
208 	pp->state = qs_state_mmio;
209 	writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
210 	readb(chan + QS_CCT_CTR0);        /* flush */
211 }
212 
213 static inline void qs_reset_channel_logic(struct ata_port *ap)
214 {
215 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
216 
217 	writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
218 	readb(chan + QS_CCT_CTR0);        /* flush */
219 	qs_enter_reg_mode(ap);
220 }
221 
222 static void qs_freeze(struct ata_port *ap)
223 {
224 	u8 __iomem *mmio_base = qs_mmio_base(ap->host);
225 
226 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
227 	qs_enter_reg_mode(ap);
228 }
229 
230 static void qs_thaw(struct ata_port *ap)
231 {
232 	u8 __iomem *mmio_base = qs_mmio_base(ap->host);
233 
234 	qs_enter_reg_mode(ap);
235 	writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
236 }
237 
238 static int qs_prereset(struct ata_link *link, unsigned long deadline)
239 {
240 	struct ata_port *ap = link->ap;
241 
242 	qs_reset_channel_logic(ap);
243 	return ata_sff_prereset(link, deadline);
244 }
245 
246 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
247 {
248 	if (sc_reg > SCR_CONTROL)
249 		return -EINVAL;
250 	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
251 	return 0;
252 }
253 
254 static void qs_error_handler(struct ata_port *ap)
255 {
256 	qs_enter_reg_mode(ap);
257 	ata_std_error_handler(ap);
258 }
259 
260 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
261 {
262 	if (sc_reg > SCR_CONTROL)
263 		return -EINVAL;
264 	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
265 	return 0;
266 }
267 
268 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
269 {
270 	struct scatterlist *sg;
271 	struct ata_port *ap = qc->ap;
272 	struct qs_port_priv *pp = ap->private_data;
273 	u8 *prd = pp->pkt + QS_CPB_BYTES;
274 	unsigned int si;
275 
276 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
277 		u64 addr;
278 		u32 len;
279 
280 		addr = sg_dma_address(sg);
281 		*(__le64 *)prd = cpu_to_le64(addr);
282 		prd += sizeof(u64);
283 
284 		len = sg_dma_len(sg);
285 		*(__le32 *)prd = cpu_to_le32(len);
286 		prd += sizeof(u64);
287 
288 		VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
289 					(unsigned long long)addr, len);
290 	}
291 
292 	return si;
293 }
294 
295 static void qs_qc_prep(struct ata_queued_cmd *qc)
296 {
297 	struct qs_port_priv *pp = qc->ap->private_data;
298 	u8 dflags = QS_DF_PORD, *buf = pp->pkt;
299 	u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
300 	u64 addr;
301 	unsigned int nelem;
302 
303 	VPRINTK("ENTER\n");
304 
305 	qs_enter_reg_mode(qc->ap);
306 	if (qc->tf.protocol != ATA_PROT_DMA) {
307 		ata_sff_qc_prep(qc);
308 		return;
309 	}
310 
311 	nelem = qs_fill_sg(qc);
312 
313 	if ((qc->tf.flags & ATA_TFLAG_WRITE))
314 		hflags |= QS_HF_DIRO;
315 	if ((qc->tf.flags & ATA_TFLAG_LBA48))
316 		dflags |= QS_DF_ELBA;
317 
318 	/* host control block (HCB) */
319 	buf[ 0] = QS_HCB_HDR;
320 	buf[ 1] = hflags;
321 	*(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
322 	*(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
323 	addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
324 	*(__le64 *)(&buf[16]) = cpu_to_le64(addr);
325 
326 	/* device control block (DCB) */
327 	buf[24] = QS_DCB_HDR;
328 	buf[28] = dflags;
329 
330 	/* frame information structure (FIS) */
331 	ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
332 }
333 
334 static inline void qs_packet_start(struct ata_queued_cmd *qc)
335 {
336 	struct ata_port *ap = qc->ap;
337 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
338 
339 	VPRINTK("ENTER, ap %p\n", ap);
340 
341 	writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
342 	wmb();                             /* flush PRDs and pkt to memory */
343 	writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
344 	readl(chan + QS_CCT_CFF);          /* flush */
345 }
346 
347 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
348 {
349 	struct qs_port_priv *pp = qc->ap->private_data;
350 
351 	switch (qc->tf.protocol) {
352 	case ATA_PROT_DMA:
353 		pp->state = qs_state_pkt;
354 		qs_packet_start(qc);
355 		return 0;
356 
357 	case ATAPI_PROT_DMA:
358 		BUG();
359 		break;
360 
361 	default:
362 		break;
363 	}
364 
365 	pp->state = qs_state_mmio;
366 	return ata_sff_qc_issue(qc);
367 }
368 
369 static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
370 {
371 	qc->err_mask |= ac_err_mask(status);
372 
373 	if (!qc->err_mask) {
374 		ata_qc_complete(qc);
375 	} else {
376 		struct ata_port    *ap  = qc->ap;
377 		struct ata_eh_info *ehi = &ap->link.eh_info;
378 
379 		ata_ehi_clear_desc(ehi);
380 		ata_ehi_push_desc(ehi, "status 0x%02X", status);
381 
382 		if (qc->err_mask == AC_ERR_DEV)
383 			ata_port_abort(ap);
384 		else
385 			ata_port_freeze(ap);
386 	}
387 }
388 
389 static inline unsigned int qs_intr_pkt(struct ata_host *host)
390 {
391 	unsigned int handled = 0;
392 	u8 sFFE;
393 	u8 __iomem *mmio_base = qs_mmio_base(host);
394 
395 	do {
396 		u32 sff0 = readl(mmio_base + QS_HST_SFF);
397 		u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
398 		u8 sEVLD = (sff1 >> 30) & 0x01;	/* valid flag */
399 		sFFE  = sff1 >> 31;		/* empty flag */
400 
401 		if (sEVLD) {
402 			u8 sDST = sff0 >> 16;	/* dev status */
403 			u8 sHST = sff1 & 0x3f;	/* host status */
404 			unsigned int port_no = (sff1 >> 8) & 0x03;
405 			struct ata_port *ap = host->ports[port_no];
406 
407 			DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
408 					sff1, sff0, port_no, sHST, sDST);
409 			handled = 1;
410 			if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
411 				struct ata_queued_cmd *qc;
412 				struct qs_port_priv *pp = ap->private_data;
413 				if (!pp || pp->state != qs_state_pkt)
414 					continue;
415 				qc = ata_qc_from_tag(ap, ap->link.active_tag);
416 				if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
417 					switch (sHST) {
418 					case 0: /* successful CPB */
419 					case 3: /* device error */
420 						qs_enter_reg_mode(qc->ap);
421 						qs_do_or_die(qc, sDST);
422 						break;
423 					default:
424 						break;
425 					}
426 				}
427 			}
428 		}
429 	} while (!sFFE);
430 	return handled;
431 }
432 
433 static inline unsigned int qs_intr_mmio(struct ata_host *host)
434 {
435 	unsigned int handled = 0, port_no;
436 
437 	for (port_no = 0; port_no < host->n_ports; ++port_no) {
438 		struct ata_port *ap;
439 		ap = host->ports[port_no];
440 		if (ap &&
441 		    !(ap->flags & ATA_FLAG_DISABLED)) {
442 			struct ata_queued_cmd *qc;
443 			struct qs_port_priv *pp;
444 			qc = ata_qc_from_tag(ap, ap->link.active_tag);
445 			if (!qc || !(qc->flags & ATA_QCFLAG_ACTIVE)) {
446 				/*
447 				 * The qstor hardware generates spurious
448 				 * interrupts from time to time when switching
449 				 * in and out of packet mode.
450 				 * There's no obvious way to know if we're
451 				 * here now due to that, so just ack the irq
452 				 * and pretend we knew it was ours.. (ugh).
453 				 * This does not affect packet mode.
454 				 */
455 				ata_sff_check_status(ap);
456 				handled = 1;
457 				continue;
458 			}
459 			pp = ap->private_data;
460 			if (!pp || pp->state != qs_state_mmio)
461 				continue;
462 			if (!(qc->tf.flags & ATA_TFLAG_POLLING))
463 				handled |= ata_sff_host_intr(ap, qc);
464 		}
465 	}
466 	return handled;
467 }
468 
469 static irqreturn_t qs_intr(int irq, void *dev_instance)
470 {
471 	struct ata_host *host = dev_instance;
472 	unsigned int handled = 0;
473 	unsigned long flags;
474 
475 	VPRINTK("ENTER\n");
476 
477 	spin_lock_irqsave(&host->lock, flags);
478 	handled  = qs_intr_pkt(host) | qs_intr_mmio(host);
479 	spin_unlock_irqrestore(&host->lock, flags);
480 
481 	VPRINTK("EXIT\n");
482 
483 	return IRQ_RETVAL(handled);
484 }
485 
486 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
487 {
488 	port->cmd_addr		=
489 	port->data_addr		= base + 0x400;
490 	port->error_addr	=
491 	port->feature_addr	= base + 0x408; /* hob_feature = 0x409 */
492 	port->nsect_addr	= base + 0x410; /* hob_nsect   = 0x411 */
493 	port->lbal_addr		= base + 0x418; /* hob_lbal    = 0x419 */
494 	port->lbam_addr		= base + 0x420; /* hob_lbam    = 0x421 */
495 	port->lbah_addr		= base + 0x428; /* hob_lbah    = 0x429 */
496 	port->device_addr	= base + 0x430;
497 	port->status_addr	=
498 	port->command_addr	= base + 0x438;
499 	port->altstatus_addr	=
500 	port->ctl_addr		= base + 0x440;
501 	port->scr_addr		= base + 0xc00;
502 }
503 
504 static int qs_port_start(struct ata_port *ap)
505 {
506 	struct device *dev = ap->host->dev;
507 	struct qs_port_priv *pp;
508 	void __iomem *mmio_base = qs_mmio_base(ap->host);
509 	void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
510 	u64 addr;
511 	int rc;
512 
513 	rc = ata_port_start(ap);
514 	if (rc)
515 		return rc;
516 	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
517 	if (!pp)
518 		return -ENOMEM;
519 	pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
520 				      GFP_KERNEL);
521 	if (!pp->pkt)
522 		return -ENOMEM;
523 	memset(pp->pkt, 0, QS_PKT_BYTES);
524 	ap->private_data = pp;
525 
526 	qs_enter_reg_mode(ap);
527 	addr = (u64)pp->pkt_dma;
528 	writel((u32) addr,        chan + QS_CCF_CPBA);
529 	writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
530 	return 0;
531 }
532 
533 static void qs_host_stop(struct ata_host *host)
534 {
535 	void __iomem *mmio_base = qs_mmio_base(host);
536 
537 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
538 	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
539 }
540 
541 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
542 {
543 	void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
544 	unsigned int port_no;
545 
546 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
547 	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
548 
549 	/* reset each channel in turn */
550 	for (port_no = 0; port_no < host->n_ports; ++port_no) {
551 		u8 __iomem *chan = mmio_base + (port_no * 0x4000);
552 		writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
553 		writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
554 		readb(chan + QS_CCT_CTR0);        /* flush */
555 	}
556 	writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
557 
558 	for (port_no = 0; port_no < host->n_ports; ++port_no) {
559 		u8 __iomem *chan = mmio_base + (port_no * 0x4000);
560 		/* set FIFO depths to same settings as Windows driver */
561 		writew(32, chan + QS_CFC_HUFT);
562 		writew(32, chan + QS_CFC_HDFT);
563 		writew(10, chan + QS_CFC_DUFT);
564 		writew( 8, chan + QS_CFC_DDFT);
565 		/* set CPB size in bytes, as a power of two */
566 		writeb(QS_CPB_ORDER,    chan + QS_CCF_CSEP);
567 	}
568 	writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
569 }
570 
571 /*
572  * The QStor understands 64-bit buses, and uses 64-bit fields
573  * for DMA pointers regardless of bus width.  We just have to
574  * make sure our DMA masks are set appropriately for whatever
575  * bridge lies between us and the QStor, and then the DMA mapping
576  * code will ensure we only ever "see" appropriate buffer addresses.
577  * If we're 32-bit limited somewhere, then our 64-bit fields will
578  * just end up with zeros in the upper 32-bits, without any special
579  * logic required outside of this routine (below).
580  */
581 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
582 {
583 	u32 bus_info = readl(mmio_base + QS_HID_HPHY);
584 	int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
585 
586 	if (have_64bit_bus &&
587 	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
588 		rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
589 		if (rc) {
590 			rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
591 			if (rc) {
592 				dev_printk(KERN_ERR, &pdev->dev,
593 					   "64-bit DMA enable failed\n");
594 				return rc;
595 			}
596 		}
597 	} else {
598 		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
599 		if (rc) {
600 			dev_printk(KERN_ERR, &pdev->dev,
601 				"32-bit DMA enable failed\n");
602 			return rc;
603 		}
604 		rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
605 		if (rc) {
606 			dev_printk(KERN_ERR, &pdev->dev,
607 				"32-bit consistent DMA enable failed\n");
608 			return rc;
609 		}
610 	}
611 	return 0;
612 }
613 
614 static int qs_ata_init_one(struct pci_dev *pdev,
615 				const struct pci_device_id *ent)
616 {
617 	static int printed_version;
618 	unsigned int board_idx = (unsigned int) ent->driver_data;
619 	const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
620 	struct ata_host *host;
621 	int rc, port_no;
622 
623 	if (!printed_version++)
624 		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
625 
626 	/* alloc host */
627 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
628 	if (!host)
629 		return -ENOMEM;
630 
631 	/* acquire resources and fill host */
632 	rc = pcim_enable_device(pdev);
633 	if (rc)
634 		return rc;
635 
636 	if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
637 		return -ENODEV;
638 
639 	rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
640 	if (rc)
641 		return rc;
642 	host->iomap = pcim_iomap_table(pdev);
643 
644 	rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
645 	if (rc)
646 		return rc;
647 
648 	for (port_no = 0; port_no < host->n_ports; ++port_no) {
649 		struct ata_port *ap = host->ports[port_no];
650 		unsigned int offset = port_no * 0x4000;
651 		void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
652 
653 		qs_ata_setup_port(&ap->ioaddr, chan);
654 
655 		ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
656 		ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
657 	}
658 
659 	/* initialize adapter */
660 	qs_host_init(host, board_idx);
661 
662 	pci_set_master(pdev);
663 	return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
664 				 &qs_ata_sht);
665 }
666 
667 static int __init qs_ata_init(void)
668 {
669 	return pci_register_driver(&qs_ata_pci_driver);
670 }
671 
672 static void __exit qs_ata_exit(void)
673 {
674 	pci_unregister_driver(&qs_ata_pci_driver);
675 }
676 
677 MODULE_AUTHOR("Mark Lord");
678 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
679 MODULE_LICENSE("GPL");
680 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
681 MODULE_VERSION(DRV_VERSION);
682 
683 module_init(qs_ata_init);
684 module_exit(qs_ata_exit);
685