1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * sata_promise.c - Promise SATA 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Mikael Pettersson 7 * Please ALWAYS copy linux-ide@vger.kernel.org 8 * on emails. 9 * 10 * Copyright 2003-2004 Red Hat, Inc. 11 * 12 * libata documentation is available via 'make {ps|pdf}docs', 13 * as Documentation/driver-api/libata.rst 14 * 15 * Hardware information only available under NDA. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/gfp.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/device.h> 26 #include <scsi/scsi.h> 27 #include <scsi/scsi_host.h> 28 #include <scsi/scsi_cmnd.h> 29 #include <linux/libata.h> 30 #include "sata_promise.h" 31 32 #define DRV_NAME "sata_promise" 33 #define DRV_VERSION "2.12" 34 35 enum { 36 PDC_MAX_PORTS = 4, 37 PDC_MMIO_BAR = 3, 38 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ 39 40 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */ 41 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 42 PDC_FLASH_CTL = 0x44, /* Flash control register */ 43 PDC_PCI_CTL = 0x48, /* PCI control/status reg */ 44 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 45 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 46 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 47 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 48 49 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */ 50 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 51 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 52 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 53 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ 54 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ 55 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ 56 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 57 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 58 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 59 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 60 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 61 62 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */ 63 PDC_SATA_ERROR = 0x04, 64 PDC_PHYMODE4 = 0x14, 65 PDC_LINK_LAYER_ERRORS = 0x6C, 66 PDC_FPDMA_CTLSTAT = 0xD8, 67 PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */ 68 PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */ 69 70 /* PDC_FPDMA_CTLSTAT bit definitions */ 71 PDC_FPDMA_CTLSTAT_RESET = 1 << 3, 72 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10, 73 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11, 74 75 /* PDC_GLOBAL_CTL bit definitions */ 76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ 78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ 79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ 80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ 81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ 82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ 83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ 84 PDC_DRIVE_ERR = (1 << 21), /* drive error */ 85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ 86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ 87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, 88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | 89 PDC2_ATA_DMA_CNT_ERR, 90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | 91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | 92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | 93 PDC1_ERR_MASK | PDC2_ERR_MASK, 94 95 board_2037x = 0, /* FastTrak S150 TX2plus */ 96 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ 97 board_20319 = 2, /* FastTrak S150 TX4 */ 98 board_20619 = 3, /* FastTrak TX4000 */ 99 board_2057x = 4, /* SATAII150 Tx2plus */ 100 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ 101 board_40518 = 6, /* SATAII150 Tx4 */ 102 103 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 104 105 /* Sequence counter control registers bit definitions */ 106 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ 107 108 /* Feature register values */ 109 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ 110 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ 111 112 /* Device/Head register values */ 113 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ 114 115 /* PDC_CTLSTAT bit definitions */ 116 PDC_DMA_ENABLE = (1 << 7), 117 PDC_IRQ_DISABLE = (1 << 10), 118 PDC_RESET = (1 << 11), /* HDMA reset */ 119 120 PDC_COMMON_FLAGS = ATA_FLAG_PIO_POLLING, 121 122 /* ap->flags bits */ 123 PDC_FLAG_GEN_II = (1 << 24), 124 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ 125 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ 126 }; 127 128 struct pdc_port_priv { 129 u8 *pkt; 130 dma_addr_t pkt_dma; 131 }; 132 133 struct pdc_host_priv { 134 spinlock_t hard_reset_lock; 135 }; 136 137 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 138 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 139 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 140 static int pdc_common_port_start(struct ata_port *ap); 141 static int pdc_sata_port_start(struct ata_port *ap); 142 static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc); 143 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 144 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 145 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 146 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); 147 static void pdc_irq_clear(struct ata_port *ap); 148 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc); 149 static void pdc_freeze(struct ata_port *ap); 150 static void pdc_sata_freeze(struct ata_port *ap); 151 static void pdc_thaw(struct ata_port *ap); 152 static void pdc_sata_thaw(struct ata_port *ap); 153 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, 154 unsigned long deadline); 155 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, 156 unsigned long deadline); 157 static void pdc_error_handler(struct ata_port *ap); 158 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 159 static int pdc_pata_cable_detect(struct ata_port *ap); 160 static int pdc_sata_cable_detect(struct ata_port *ap); 161 162 static struct scsi_host_template pdc_ata_sht = { 163 ATA_BASE_SHT(DRV_NAME), 164 .sg_tablesize = PDC_MAX_PRD, 165 .dma_boundary = ATA_DMA_BOUNDARY, 166 }; 167 168 static const struct ata_port_operations pdc_common_ops = { 169 .inherits = &ata_sff_port_ops, 170 171 .sff_tf_load = pdc_tf_load_mmio, 172 .sff_exec_command = pdc_exec_command_mmio, 173 .check_atapi_dma = pdc_check_atapi_dma, 174 .qc_prep = pdc_qc_prep, 175 .qc_issue = pdc_qc_issue, 176 177 .sff_irq_clear = pdc_irq_clear, 178 .lost_interrupt = ATA_OP_NULL, 179 180 .post_internal_cmd = pdc_post_internal_cmd, 181 .error_handler = pdc_error_handler, 182 }; 183 184 static struct ata_port_operations pdc_sata_ops = { 185 .inherits = &pdc_common_ops, 186 .cable_detect = pdc_sata_cable_detect, 187 .freeze = pdc_sata_freeze, 188 .thaw = pdc_sata_thaw, 189 .scr_read = pdc_sata_scr_read, 190 .scr_write = pdc_sata_scr_write, 191 .port_start = pdc_sata_port_start, 192 .hardreset = pdc_sata_hardreset, 193 }; 194 195 /* First-generation chips need a more restrictive ->check_atapi_dma op, 196 and ->freeze/thaw that ignore the hotplug controls. */ 197 static struct ata_port_operations pdc_old_sata_ops = { 198 .inherits = &pdc_sata_ops, 199 .freeze = pdc_freeze, 200 .thaw = pdc_thaw, 201 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 202 }; 203 204 static struct ata_port_operations pdc_pata_ops = { 205 .inherits = &pdc_common_ops, 206 .cable_detect = pdc_pata_cable_detect, 207 .freeze = pdc_freeze, 208 .thaw = pdc_thaw, 209 .port_start = pdc_common_port_start, 210 .softreset = pdc_pata_softreset, 211 }; 212 213 static const struct ata_port_info pdc_port_info[] = { 214 [board_2037x] = 215 { 216 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 217 PDC_FLAG_SATA_PATA, 218 .pio_mask = ATA_PIO4, 219 .mwdma_mask = ATA_MWDMA2, 220 .udma_mask = ATA_UDMA6, 221 .port_ops = &pdc_old_sata_ops, 222 }, 223 224 [board_2037x_pata] = 225 { 226 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 227 .pio_mask = ATA_PIO4, 228 .mwdma_mask = ATA_MWDMA2, 229 .udma_mask = ATA_UDMA6, 230 .port_ops = &pdc_pata_ops, 231 }, 232 233 [board_20319] = 234 { 235 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 236 PDC_FLAG_4_PORTS, 237 .pio_mask = ATA_PIO4, 238 .mwdma_mask = ATA_MWDMA2, 239 .udma_mask = ATA_UDMA6, 240 .port_ops = &pdc_old_sata_ops, 241 }, 242 243 [board_20619] = 244 { 245 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 246 PDC_FLAG_4_PORTS, 247 .pio_mask = ATA_PIO4, 248 .mwdma_mask = ATA_MWDMA2, 249 .udma_mask = ATA_UDMA6, 250 .port_ops = &pdc_pata_ops, 251 }, 252 253 [board_2057x] = 254 { 255 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 256 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, 257 .pio_mask = ATA_PIO4, 258 .mwdma_mask = ATA_MWDMA2, 259 .udma_mask = ATA_UDMA6, 260 .port_ops = &pdc_sata_ops, 261 }, 262 263 [board_2057x_pata] = 264 { 265 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 266 PDC_FLAG_GEN_II, 267 .pio_mask = ATA_PIO4, 268 .mwdma_mask = ATA_MWDMA2, 269 .udma_mask = ATA_UDMA6, 270 .port_ops = &pdc_pata_ops, 271 }, 272 273 [board_40518] = 274 { 275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 276 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, 277 .pio_mask = ATA_PIO4, 278 .mwdma_mask = ATA_MWDMA2, 279 .udma_mask = ATA_UDMA6, 280 .port_ops = &pdc_sata_ops, 281 }, 282 }; 283 284 static const struct pci_device_id pdc_ata_pci_tbl[] = { 285 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 286 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 287 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 288 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 289 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, 290 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, 291 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 292 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, 293 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, 294 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 295 296 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 297 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 298 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, 299 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, 300 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, 301 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 302 303 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 304 305 { } /* terminate list */ 306 }; 307 308 static struct pci_driver pdc_ata_pci_driver = { 309 .name = DRV_NAME, 310 .id_table = pdc_ata_pci_tbl, 311 .probe = pdc_ata_init_one, 312 .remove = ata_pci_remove_one, 313 }; 314 315 static int pdc_common_port_start(struct ata_port *ap) 316 { 317 struct device *dev = ap->host->dev; 318 struct pdc_port_priv *pp; 319 int rc; 320 321 /* we use the same prd table as bmdma, allocate it */ 322 rc = ata_bmdma_port_start(ap); 323 if (rc) 324 return rc; 325 326 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 327 if (!pp) 328 return -ENOMEM; 329 330 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 331 if (!pp->pkt) 332 return -ENOMEM; 333 334 ap->private_data = pp; 335 336 return 0; 337 } 338 339 static int pdc_sata_port_start(struct ata_port *ap) 340 { 341 int rc; 342 343 rc = pdc_common_port_start(ap); 344 if (rc) 345 return rc; 346 347 /* fix up PHYMODE4 align timing */ 348 if (ap->flags & PDC_FLAG_GEN_II) { 349 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 350 unsigned int tmp; 351 352 tmp = readl(sata_mmio + PDC_PHYMODE4); 353 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 354 writel(tmp, sata_mmio + PDC_PHYMODE4); 355 } 356 357 return 0; 358 } 359 360 static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap) 361 { 362 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 363 u32 tmp; 364 365 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT); 366 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG; 367 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG; 368 369 /* It's not allowed to write to the entire FPDMA_CTLSTAT register 370 when NCQ is running. So do a byte-sized write to bits 10 and 11. */ 371 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1); 372 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */ 373 } 374 375 static void pdc_fpdma_reset(struct ata_port *ap) 376 { 377 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 378 u8 tmp; 379 380 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT); 381 tmp &= 0x7F; 382 tmp |= PDC_FPDMA_CTLSTAT_RESET; 383 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT); 384 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */ 385 udelay(100); 386 tmp &= ~PDC_FPDMA_CTLSTAT_RESET; 387 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT); 388 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */ 389 390 pdc_fpdma_clear_interrupt_flag(ap); 391 } 392 393 static void pdc_not_at_command_packet_phase(struct ata_port *ap) 394 { 395 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 396 unsigned int i; 397 u32 tmp; 398 399 /* check not at ASIC packet command phase */ 400 for (i = 0; i < 100; ++i) { 401 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1); 402 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2); 403 if ((tmp & 0xF) != 1) 404 break; 405 udelay(100); 406 } 407 } 408 409 static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap) 410 { 411 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 412 413 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR); 414 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS); 415 } 416 417 static void pdc_reset_port(struct ata_port *ap) 418 { 419 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 420 unsigned int i; 421 u32 tmp; 422 423 if (ap->flags & PDC_FLAG_GEN_II) 424 pdc_not_at_command_packet_phase(ap); 425 426 tmp = readl(ata_ctlstat_mmio); 427 tmp |= PDC_RESET; 428 writel(tmp, ata_ctlstat_mmio); 429 430 for (i = 11; i > 0; i--) { 431 tmp = readl(ata_ctlstat_mmio); 432 if (tmp & PDC_RESET) 433 break; 434 435 udelay(100); 436 437 tmp |= PDC_RESET; 438 writel(tmp, ata_ctlstat_mmio); 439 } 440 441 tmp &= ~PDC_RESET; 442 writel(tmp, ata_ctlstat_mmio); 443 readl(ata_ctlstat_mmio); /* flush */ 444 445 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) { 446 pdc_fpdma_reset(ap); 447 pdc_clear_internal_debug_record_error_register(ap); 448 } 449 } 450 451 static int pdc_pata_cable_detect(struct ata_port *ap) 452 { 453 u8 tmp; 454 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 455 456 tmp = readb(ata_mmio + PDC_CTLSTAT + 3); 457 if (tmp & 0x01) 458 return ATA_CBL_PATA40; 459 return ATA_CBL_PATA80; 460 } 461 462 static int pdc_sata_cable_detect(struct ata_port *ap) 463 { 464 return ATA_CBL_SATA; 465 } 466 467 static int pdc_sata_scr_read(struct ata_link *link, 468 unsigned int sc_reg, u32 *val) 469 { 470 if (sc_reg > SCR_CONTROL) 471 return -EINVAL; 472 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); 473 return 0; 474 } 475 476 static int pdc_sata_scr_write(struct ata_link *link, 477 unsigned int sc_reg, u32 val) 478 { 479 if (sc_reg > SCR_CONTROL) 480 return -EINVAL; 481 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); 482 return 0; 483 } 484 485 static void pdc_atapi_pkt(struct ata_queued_cmd *qc) 486 { 487 struct ata_port *ap = qc->ap; 488 dma_addr_t sg_table = ap->bmdma_prd_dma; 489 unsigned int cdb_len = qc->dev->cdb_len; 490 u8 *cdb = qc->cdb; 491 struct pdc_port_priv *pp = ap->private_data; 492 u8 *buf = pp->pkt; 493 __le32 *buf32 = (__le32 *) buf; 494 unsigned int dev_sel, feature; 495 496 /* set control bits (byte 0), zero delay seq id (byte 3), 497 * and seq id (byte 2) 498 */ 499 switch (qc->tf.protocol) { 500 case ATAPI_PROT_DMA: 501 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 502 buf32[0] = cpu_to_le32(PDC_PKT_READ); 503 else 504 buf32[0] = 0; 505 break; 506 case ATAPI_PROT_NODATA: 507 buf32[0] = cpu_to_le32(PDC_PKT_NODATA); 508 break; 509 default: 510 BUG(); 511 break; 512 } 513 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 514 buf32[2] = 0; /* no next-packet */ 515 516 /* select drive */ 517 if (sata_scr_valid(&ap->link)) 518 dev_sel = PDC_DEVICE_SATA; 519 else 520 dev_sel = qc->tf.device; 521 522 buf[12] = (1 << 5) | ATA_REG_DEVICE; 523 buf[13] = dev_sel; 524 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; 525 buf[15] = dev_sel; /* once more, waiting for BSY to clear */ 526 527 buf[16] = (1 << 5) | ATA_REG_NSECT; 528 buf[17] = qc->tf.nsect; 529 buf[18] = (1 << 5) | ATA_REG_LBAL; 530 buf[19] = qc->tf.lbal; 531 532 /* set feature and byte counter registers */ 533 if (qc->tf.protocol != ATAPI_PROT_DMA) 534 feature = PDC_FEATURE_ATAPI_PIO; 535 else 536 feature = PDC_FEATURE_ATAPI_DMA; 537 538 buf[20] = (1 << 5) | ATA_REG_FEATURE; 539 buf[21] = feature; 540 buf[22] = (1 << 5) | ATA_REG_BYTEL; 541 buf[23] = qc->tf.lbam; 542 buf[24] = (1 << 5) | ATA_REG_BYTEH; 543 buf[25] = qc->tf.lbah; 544 545 /* send ATAPI packet command 0xA0 */ 546 buf[26] = (1 << 5) | ATA_REG_CMD; 547 buf[27] = qc->tf.command; 548 549 /* select drive and check DRQ */ 550 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; 551 buf[29] = dev_sel; 552 553 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 554 BUG_ON(cdb_len & ~0x1E); 555 556 /* append the CDB as the final part */ 557 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 558 memcpy(buf+31, cdb, cdb_len); 559 } 560 561 /** 562 * pdc_fill_sg - Fill PCI IDE PRD table 563 * @qc: Metadata associated with taskfile to be transferred 564 * 565 * Fill PCI IDE PRD (scatter-gather) table with segments 566 * associated with the current disk command. 567 * Make sure hardware does not choke on it. 568 * 569 * LOCKING: 570 * spin_lock_irqsave(host lock) 571 * 572 */ 573 static void pdc_fill_sg(struct ata_queued_cmd *qc) 574 { 575 struct ata_port *ap = qc->ap; 576 struct ata_bmdma_prd *prd = ap->bmdma_prd; 577 struct scatterlist *sg; 578 const u32 SG_COUNT_ASIC_BUG = 41*4; 579 unsigned int si, idx; 580 u32 len; 581 582 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 583 return; 584 585 idx = 0; 586 for_each_sg(qc->sg, sg, qc->n_elem, si) { 587 u32 addr, offset; 588 u32 sg_len; 589 590 /* determine if physical DMA addr spans 64K boundary. 591 * Note h/w doesn't support 64-bit, so we unconditionally 592 * truncate dma_addr_t to u32. 593 */ 594 addr = (u32) sg_dma_address(sg); 595 sg_len = sg_dma_len(sg); 596 597 while (sg_len) { 598 offset = addr & 0xffff; 599 len = sg_len; 600 if ((offset + sg_len) > 0x10000) 601 len = 0x10000 - offset; 602 603 prd[idx].addr = cpu_to_le32(addr); 604 prd[idx].flags_len = cpu_to_le32(len & 0xffff); 605 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 606 607 idx++; 608 sg_len -= len; 609 addr += len; 610 } 611 } 612 613 len = le32_to_cpu(prd[idx - 1].flags_len); 614 615 if (len > SG_COUNT_ASIC_BUG) { 616 u32 addr; 617 618 VPRINTK("Splitting last PRD.\n"); 619 620 addr = le32_to_cpu(prd[idx - 1].addr); 621 prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG); 622 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG); 623 624 addr = addr + len - SG_COUNT_ASIC_BUG; 625 len = SG_COUNT_ASIC_BUG; 626 prd[idx].addr = cpu_to_le32(addr); 627 prd[idx].flags_len = cpu_to_le32(len); 628 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 629 630 idx++; 631 } 632 633 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 634 } 635 636 static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc) 637 { 638 struct pdc_port_priv *pp = qc->ap->private_data; 639 unsigned int i; 640 641 VPRINTK("ENTER\n"); 642 643 switch (qc->tf.protocol) { 644 case ATA_PROT_DMA: 645 pdc_fill_sg(qc); 646 /*FALLTHROUGH*/ 647 case ATA_PROT_NODATA: 648 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma, 649 qc->dev->devno, pp->pkt); 650 if (qc->tf.flags & ATA_TFLAG_LBA48) 651 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 652 else 653 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 654 pdc_pkt_footer(&qc->tf, pp->pkt, i); 655 break; 656 case ATAPI_PROT_PIO: 657 pdc_fill_sg(qc); 658 break; 659 case ATAPI_PROT_DMA: 660 pdc_fill_sg(qc); 661 /*FALLTHROUGH*/ 662 case ATAPI_PROT_NODATA: 663 pdc_atapi_pkt(qc); 664 break; 665 default: 666 break; 667 } 668 669 return AC_ERR_OK; 670 } 671 672 static int pdc_is_sataii_tx4(unsigned long flags) 673 { 674 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; 675 return (flags & mask) == mask; 676 } 677 678 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, 679 int is_sataii_tx4) 680 { 681 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; 682 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; 683 } 684 685 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap) 686 { 687 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2; 688 } 689 690 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap) 691 { 692 const struct ata_host *host = ap->host; 693 unsigned int nr_ports = pdc_sata_nr_ports(ap); 694 unsigned int i; 695 696 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i) 697 ; 698 BUG_ON(i >= nr_ports); 699 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags)); 700 } 701 702 static void pdc_freeze(struct ata_port *ap) 703 { 704 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 705 u32 tmp; 706 707 tmp = readl(ata_mmio + PDC_CTLSTAT); 708 tmp |= PDC_IRQ_DISABLE; 709 tmp &= ~PDC_DMA_ENABLE; 710 writel(tmp, ata_mmio + PDC_CTLSTAT); 711 readl(ata_mmio + PDC_CTLSTAT); /* flush */ 712 } 713 714 static void pdc_sata_freeze(struct ata_port *ap) 715 { 716 struct ata_host *host = ap->host; 717 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 718 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR; 719 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 720 u32 hotplug_status; 721 722 /* Disable hotplug events on this port. 723 * 724 * Locking: 725 * 1) hotplug register accesses must be serialised via host->lock 726 * 2) ap->lock == &ap->host->lock 727 * 3) ->freeze() and ->thaw() are called with ap->lock held 728 */ 729 hotplug_status = readl(host_mmio + hotplug_offset); 730 hotplug_status |= 0x11 << (ata_no + 16); 731 writel(hotplug_status, host_mmio + hotplug_offset); 732 readl(host_mmio + hotplug_offset); /* flush */ 733 734 pdc_freeze(ap); 735 } 736 737 static void pdc_thaw(struct ata_port *ap) 738 { 739 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 740 u32 tmp; 741 742 /* clear IRQ */ 743 readl(ata_mmio + PDC_COMMAND); 744 745 /* turn IRQ back on */ 746 tmp = readl(ata_mmio + PDC_CTLSTAT); 747 tmp &= ~PDC_IRQ_DISABLE; 748 writel(tmp, ata_mmio + PDC_CTLSTAT); 749 readl(ata_mmio + PDC_CTLSTAT); /* flush */ 750 } 751 752 static void pdc_sata_thaw(struct ata_port *ap) 753 { 754 struct ata_host *host = ap->host; 755 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 756 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR; 757 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 758 u32 hotplug_status; 759 760 pdc_thaw(ap); 761 762 /* Enable hotplug events on this port. 763 * Locking: see pdc_sata_freeze(). 764 */ 765 hotplug_status = readl(host_mmio + hotplug_offset); 766 hotplug_status |= 0x11 << ata_no; 767 hotplug_status &= ~(0x11 << (ata_no + 16)); 768 writel(hotplug_status, host_mmio + hotplug_offset); 769 readl(host_mmio + hotplug_offset); /* flush */ 770 } 771 772 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, 773 unsigned long deadline) 774 { 775 pdc_reset_port(link->ap); 776 return ata_sff_softreset(link, class, deadline); 777 } 778 779 static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap) 780 { 781 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 782 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; 783 784 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */ 785 return (ata_mmio - host_mmio - 0x200) / 0x80; 786 } 787 788 static void pdc_hard_reset_port(struct ata_port *ap) 789 { 790 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; 791 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1; 792 unsigned int ata_no = pdc_ata_port_to_ata_no(ap); 793 struct pdc_host_priv *hpriv = ap->host->private_data; 794 u8 tmp; 795 796 spin_lock(&hpriv->hard_reset_lock); 797 798 tmp = readb(pcictl_b1_mmio); 799 tmp &= ~(0x10 << ata_no); 800 writeb(tmp, pcictl_b1_mmio); 801 readb(pcictl_b1_mmio); /* flush */ 802 udelay(100); 803 tmp |= (0x10 << ata_no); 804 writeb(tmp, pcictl_b1_mmio); 805 readb(pcictl_b1_mmio); /* flush */ 806 807 spin_unlock(&hpriv->hard_reset_lock); 808 } 809 810 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, 811 unsigned long deadline) 812 { 813 if (link->ap->flags & PDC_FLAG_GEN_II) 814 pdc_not_at_command_packet_phase(link->ap); 815 /* hotplug IRQs should have been masked by pdc_sata_freeze() */ 816 pdc_hard_reset_port(link->ap); 817 pdc_reset_port(link->ap); 818 819 /* sata_promise can't reliably acquire the first D2H Reg FIS 820 * after hardreset. Do non-waiting hardreset and request 821 * follow-up SRST. 822 */ 823 return sata_std_hardreset(link, class, deadline); 824 } 825 826 static void pdc_error_handler(struct ata_port *ap) 827 { 828 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 829 pdc_reset_port(ap); 830 831 ata_sff_error_handler(ap); 832 } 833 834 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 835 { 836 struct ata_port *ap = qc->ap; 837 838 /* make DMA engine forget about the failed command */ 839 if (qc->flags & ATA_QCFLAG_FAILED) 840 pdc_reset_port(ap); 841 } 842 843 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, 844 u32 port_status, u32 err_mask) 845 { 846 struct ata_eh_info *ehi = &ap->link.eh_info; 847 unsigned int ac_err_mask = 0; 848 849 ata_ehi_clear_desc(ehi); 850 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); 851 port_status &= err_mask; 852 853 if (port_status & PDC_DRIVE_ERR) 854 ac_err_mask |= AC_ERR_DEV; 855 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) 856 ac_err_mask |= AC_ERR_OTHER; 857 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) 858 ac_err_mask |= AC_ERR_ATA_BUS; 859 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR 860 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) 861 ac_err_mask |= AC_ERR_HOST_BUS; 862 863 if (sata_scr_valid(&ap->link)) { 864 u32 serror; 865 866 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror); 867 ehi->serror |= serror; 868 } 869 870 qc->err_mask |= ac_err_mask; 871 872 pdc_reset_port(ap); 873 874 ata_port_abort(ap); 875 } 876 877 static unsigned int pdc_host_intr(struct ata_port *ap, 878 struct ata_queued_cmd *qc) 879 { 880 unsigned int handled = 0; 881 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 882 u32 port_status, err_mask; 883 884 err_mask = PDC_ERR_MASK; 885 if (ap->flags & PDC_FLAG_GEN_II) 886 err_mask &= ~PDC1_ERR_MASK; 887 else 888 err_mask &= ~PDC2_ERR_MASK; 889 port_status = readl(ata_mmio + PDC_GLOBAL_CTL); 890 if (unlikely(port_status & err_mask)) { 891 pdc_error_intr(ap, qc, port_status, err_mask); 892 return 1; 893 } 894 895 switch (qc->tf.protocol) { 896 case ATA_PROT_DMA: 897 case ATA_PROT_NODATA: 898 case ATAPI_PROT_DMA: 899 case ATAPI_PROT_NODATA: 900 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 901 ata_qc_complete(qc); 902 handled = 1; 903 break; 904 default: 905 ap->stats.idle_irq++; 906 break; 907 } 908 909 return handled; 910 } 911 912 static void pdc_irq_clear(struct ata_port *ap) 913 { 914 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 915 916 readl(ata_mmio + PDC_COMMAND); 917 } 918 919 static irqreturn_t pdc_interrupt(int irq, void *dev_instance) 920 { 921 struct ata_host *host = dev_instance; 922 struct ata_port *ap; 923 u32 mask = 0; 924 unsigned int i, tmp; 925 unsigned int handled = 0; 926 void __iomem *host_mmio; 927 unsigned int hotplug_offset, ata_no; 928 u32 hotplug_status; 929 int is_sataii_tx4; 930 931 VPRINTK("ENTER\n"); 932 933 if (!host || !host->iomap[PDC_MMIO_BAR]) { 934 VPRINTK("QUICK EXIT\n"); 935 return IRQ_NONE; 936 } 937 938 host_mmio = host->iomap[PDC_MMIO_BAR]; 939 940 spin_lock(&host->lock); 941 942 /* read and clear hotplug flags for all ports */ 943 if (host->ports[0]->flags & PDC_FLAG_GEN_II) { 944 hotplug_offset = PDC2_SATA_PLUG_CSR; 945 hotplug_status = readl(host_mmio + hotplug_offset); 946 if (hotplug_status & 0xff) 947 writel(hotplug_status | 0xff, host_mmio + hotplug_offset); 948 hotplug_status &= 0xff; /* clear uninteresting bits */ 949 } else 950 hotplug_status = 0; 951 952 /* reading should also clear interrupts */ 953 mask = readl(host_mmio + PDC_INT_SEQMASK); 954 955 if (mask == 0xffffffff && hotplug_status == 0) { 956 VPRINTK("QUICK EXIT 2\n"); 957 goto done_irq; 958 } 959 960 mask &= 0xffff; /* only 16 SEQIDs possible */ 961 if (mask == 0 && hotplug_status == 0) { 962 VPRINTK("QUICK EXIT 3\n"); 963 goto done_irq; 964 } 965 966 writel(mask, host_mmio + PDC_INT_SEQMASK); 967 968 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); 969 970 for (i = 0; i < host->n_ports; i++) { 971 VPRINTK("port %u\n", i); 972 ap = host->ports[i]; 973 974 /* check for a plug or unplug event */ 975 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 976 tmp = hotplug_status & (0x11 << ata_no); 977 if (tmp) { 978 struct ata_eh_info *ehi = &ap->link.eh_info; 979 ata_ehi_clear_desc(ehi); 980 ata_ehi_hotplugged(ehi); 981 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); 982 ata_port_freeze(ap); 983 ++handled; 984 continue; 985 } 986 987 /* check for a packet interrupt */ 988 tmp = mask & (1 << (i + 1)); 989 if (tmp) { 990 struct ata_queued_cmd *qc; 991 992 qc = ata_qc_from_tag(ap, ap->link.active_tag); 993 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 994 handled += pdc_host_intr(ap, qc); 995 } 996 } 997 998 VPRINTK("EXIT\n"); 999 1000 done_irq: 1001 spin_unlock(&host->lock); 1002 return IRQ_RETVAL(handled); 1003 } 1004 1005 static void pdc_packet_start(struct ata_queued_cmd *qc) 1006 { 1007 struct ata_port *ap = qc->ap; 1008 struct pdc_port_priv *pp = ap->private_data; 1009 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; 1010 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 1011 unsigned int port_no = ap->port_no; 1012 u8 seq = (u8) (port_no + 1); 1013 1014 VPRINTK("ENTER, ap %p\n", ap); 1015 1016 writel(0x00000001, host_mmio + (seq * 4)); 1017 readl(host_mmio + (seq * 4)); /* flush */ 1018 1019 pp->pkt[2] = seq; 1020 wmb(); /* flush PRD, pkt writes */ 1021 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT); 1022 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */ 1023 } 1024 1025 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) 1026 { 1027 switch (qc->tf.protocol) { 1028 case ATAPI_PROT_NODATA: 1029 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 1030 break; 1031 /*FALLTHROUGH*/ 1032 case ATA_PROT_NODATA: 1033 if (qc->tf.flags & ATA_TFLAG_POLLING) 1034 break; 1035 /*FALLTHROUGH*/ 1036 case ATAPI_PROT_DMA: 1037 case ATA_PROT_DMA: 1038 pdc_packet_start(qc); 1039 return 0; 1040 default: 1041 break; 1042 } 1043 return ata_sff_qc_issue(qc); 1044 } 1045 1046 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 1047 { 1048 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 1049 ata_sff_tf_load(ap, tf); 1050 } 1051 1052 static void pdc_exec_command_mmio(struct ata_port *ap, 1053 const struct ata_taskfile *tf) 1054 { 1055 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 1056 ata_sff_exec_command(ap, tf); 1057 } 1058 1059 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) 1060 { 1061 u8 *scsicmd = qc->scsicmd->cmnd; 1062 int pio = 1; /* atapi dma off by default */ 1063 1064 /* Whitelist commands that may use DMA. */ 1065 switch (scsicmd[0]) { 1066 case WRITE_12: 1067 case WRITE_10: 1068 case WRITE_6: 1069 case READ_12: 1070 case READ_10: 1071 case READ_6: 1072 case 0xad: /* READ_DVD_STRUCTURE */ 1073 case 0xbe: /* READ_CD */ 1074 pio = 0; 1075 } 1076 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ 1077 if (scsicmd[0] == WRITE_10) { 1078 unsigned int lba = 1079 (scsicmd[2] << 24) | 1080 (scsicmd[3] << 16) | 1081 (scsicmd[4] << 8) | 1082 scsicmd[5]; 1083 if (lba >= 0xFFFF4FA2) 1084 pio = 1; 1085 } 1086 return pio; 1087 } 1088 1089 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) 1090 { 1091 /* First generation chips cannot use ATAPI DMA on SATA ports */ 1092 return 1; 1093 } 1094 1095 static void pdc_ata_setup_port(struct ata_port *ap, 1096 void __iomem *base, void __iomem *scr_addr) 1097 { 1098 ap->ioaddr.cmd_addr = base; 1099 ap->ioaddr.data_addr = base; 1100 ap->ioaddr.feature_addr = 1101 ap->ioaddr.error_addr = base + 0x4; 1102 ap->ioaddr.nsect_addr = base + 0x8; 1103 ap->ioaddr.lbal_addr = base + 0xc; 1104 ap->ioaddr.lbam_addr = base + 0x10; 1105 ap->ioaddr.lbah_addr = base + 0x14; 1106 ap->ioaddr.device_addr = base + 0x18; 1107 ap->ioaddr.command_addr = 1108 ap->ioaddr.status_addr = base + 0x1c; 1109 ap->ioaddr.altstatus_addr = 1110 ap->ioaddr.ctl_addr = base + 0x38; 1111 ap->ioaddr.scr_addr = scr_addr; 1112 } 1113 1114 static void pdc_host_init(struct ata_host *host) 1115 { 1116 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 1117 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 1118 int hotplug_offset; 1119 u32 tmp; 1120 1121 if (is_gen2) 1122 hotplug_offset = PDC2_SATA_PLUG_CSR; 1123 else 1124 hotplug_offset = PDC_SATA_PLUG_CSR; 1125 1126 /* 1127 * Except for the hotplug stuff, this is voodoo from the 1128 * Promise driver. Label this entire section 1129 * "TODO: figure out why we do this" 1130 */ 1131 1132 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 1133 tmp = readl(host_mmio + PDC_FLASH_CTL); 1134 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 1135 if (!is_gen2) 1136 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 1137 writel(tmp, host_mmio + PDC_FLASH_CTL); 1138 1139 /* clear plug/unplug flags for all ports */ 1140 tmp = readl(host_mmio + hotplug_offset); 1141 writel(tmp | 0xff, host_mmio + hotplug_offset); 1142 1143 tmp = readl(host_mmio + hotplug_offset); 1144 if (is_gen2) /* unmask plug/unplug ints */ 1145 writel(tmp & ~0xff0000, host_mmio + hotplug_offset); 1146 else /* mask plug/unplug ints */ 1147 writel(tmp | 0xff0000, host_mmio + hotplug_offset); 1148 1149 /* don't initialise TBG or SLEW on 2nd generation chips */ 1150 if (is_gen2) 1151 return; 1152 1153 /* reduce TBG clock to 133 Mhz. */ 1154 tmp = readl(host_mmio + PDC_TBG_MODE); 1155 tmp &= ~0x30000; /* clear bit 17, 16*/ 1156 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 1157 writel(tmp, host_mmio + PDC_TBG_MODE); 1158 1159 readl(host_mmio + PDC_TBG_MODE); /* flush */ 1160 msleep(10); 1161 1162 /* adjust slew rate control register. */ 1163 tmp = readl(host_mmio + PDC_SLEW_CTL); 1164 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 1165 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 1166 writel(tmp, host_mmio + PDC_SLEW_CTL); 1167 } 1168 1169 static int pdc_ata_init_one(struct pci_dev *pdev, 1170 const struct pci_device_id *ent) 1171 { 1172 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 1173 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 1174 struct ata_host *host; 1175 struct pdc_host_priv *hpriv; 1176 void __iomem *host_mmio; 1177 int n_ports, i, rc; 1178 int is_sataii_tx4; 1179 1180 ata_print_version_once(&pdev->dev, DRV_VERSION); 1181 1182 /* enable and acquire resources */ 1183 rc = pcim_enable_device(pdev); 1184 if (rc) 1185 return rc; 1186 1187 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 1188 if (rc == -EBUSY) 1189 pcim_pin_device(pdev); 1190 if (rc) 1191 return rc; 1192 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 1193 1194 /* determine port configuration and setup host */ 1195 n_ports = 2; 1196 if (pi->flags & PDC_FLAG_4_PORTS) 1197 n_ports = 4; 1198 for (i = 0; i < n_ports; i++) 1199 ppi[i] = pi; 1200 1201 if (pi->flags & PDC_FLAG_SATA_PATA) { 1202 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1); 1203 if (!(tmp & 0x80)) 1204 ppi[n_ports++] = pi + 1; 1205 } 1206 1207 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1208 if (!host) { 1209 dev_err(&pdev->dev, "failed to allocate host\n"); 1210 return -ENOMEM; 1211 } 1212 hpriv = devm_kzalloc(&pdev->dev, sizeof *hpriv, GFP_KERNEL); 1213 if (!hpriv) 1214 return -ENOMEM; 1215 spin_lock_init(&hpriv->hard_reset_lock); 1216 host->private_data = hpriv; 1217 host->iomap = pcim_iomap_table(pdev); 1218 1219 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); 1220 for (i = 0; i < host->n_ports; i++) { 1221 struct ata_port *ap = host->ports[i]; 1222 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 1223 unsigned int ata_offset = 0x200 + ata_no * 0x80; 1224 unsigned int scr_offset = 0x400 + ata_no * 0x100; 1225 1226 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset); 1227 1228 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 1229 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata"); 1230 } 1231 1232 /* initialize adapter */ 1233 pdc_host_init(host); 1234 1235 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); 1236 if (rc) 1237 return rc; 1238 1239 /* start host, request IRQ and attach */ 1240 pci_set_master(pdev); 1241 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, 1242 &pdc_ata_sht); 1243 } 1244 1245 module_pci_driver(pdc_ata_pci_driver); 1246 1247 MODULE_AUTHOR("Jeff Garzik"); 1248 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); 1249 MODULE_LICENSE("GPL"); 1250 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); 1251 MODULE_VERSION(DRV_VERSION); 1252