1 /* 2 * sata_promise.c - Promise SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Mikael Pettersson <mikpe@it.uu.se> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2003-2004 Red Hat, Inc. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * 27 * libata documentation is available via 'make {ps|pdf}docs', 28 * as Documentation/DocBook/libata.* 29 * 30 * Hardware information only available under NDA. 31 * 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/init.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/device.h> 42 #include <scsi/scsi.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include "sata_promise.h" 47 48 #define DRV_NAME "sata_promise" 49 #define DRV_VERSION "2.12" 50 51 enum { 52 PDC_MAX_PORTS = 4, 53 PDC_MMIO_BAR = 3, 54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ 55 56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */ 57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 58 PDC_FLASH_CTL = 0x44, /* Flash control register */ 59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 60 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 61 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 62 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 63 64 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */ 65 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 66 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 67 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 68 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ 69 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ 70 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ 71 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 72 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 73 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 74 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 75 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 76 77 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */ 78 PDC_PHYMODE4 = 0x14, 79 80 /* PDC_GLOBAL_CTL bit definitions */ 81 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 82 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ 83 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ 84 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ 85 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ 86 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ 87 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ 88 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ 89 PDC_DRIVE_ERR = (1 << 21), /* drive error */ 90 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ 91 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ 92 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, 93 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | 94 PDC2_ATA_DMA_CNT_ERR, 95 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | 96 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | 97 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | 98 PDC1_ERR_MASK | PDC2_ERR_MASK, 99 100 board_2037x = 0, /* FastTrak S150 TX2plus */ 101 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ 102 board_20319 = 2, /* FastTrak S150 TX4 */ 103 board_20619 = 3, /* FastTrak TX4000 */ 104 board_2057x = 4, /* SATAII150 Tx2plus */ 105 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ 106 board_40518 = 6, /* SATAII150 Tx4 */ 107 108 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 109 110 /* Sequence counter control registers bit definitions */ 111 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ 112 113 /* Feature register values */ 114 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ 115 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ 116 117 /* Device/Head register values */ 118 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ 119 120 /* PDC_CTLSTAT bit definitions */ 121 PDC_DMA_ENABLE = (1 << 7), 122 PDC_IRQ_DISABLE = (1 << 10), 123 PDC_RESET = (1 << 11), /* HDMA reset */ 124 125 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | 126 ATA_FLAG_MMIO | 127 ATA_FLAG_PIO_POLLING, 128 129 /* ap->flags bits */ 130 PDC_FLAG_GEN_II = (1 << 24), 131 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ 132 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ 133 }; 134 135 struct pdc_port_priv { 136 u8 *pkt; 137 dma_addr_t pkt_dma; 138 }; 139 140 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 141 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 142 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 143 static int pdc_common_port_start(struct ata_port *ap); 144 static int pdc_sata_port_start(struct ata_port *ap); 145 static void pdc_qc_prep(struct ata_queued_cmd *qc); 146 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 147 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 148 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 149 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); 150 static void pdc_irq_clear(struct ata_port *ap); 151 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc); 152 static void pdc_freeze(struct ata_port *ap); 153 static void pdc_sata_freeze(struct ata_port *ap); 154 static void pdc_thaw(struct ata_port *ap); 155 static void pdc_sata_thaw(struct ata_port *ap); 156 static void pdc_error_handler(struct ata_port *ap); 157 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 158 static int pdc_pata_cable_detect(struct ata_port *ap); 159 static int pdc_sata_cable_detect(struct ata_port *ap); 160 161 static struct scsi_host_template pdc_ata_sht = { 162 ATA_BASE_SHT(DRV_NAME), 163 .sg_tablesize = PDC_MAX_PRD, 164 .dma_boundary = ATA_DMA_BOUNDARY, 165 }; 166 167 static const struct ata_port_operations pdc_common_ops = { 168 .inherits = &ata_sff_port_ops, 169 170 .sff_tf_load = pdc_tf_load_mmio, 171 .sff_exec_command = pdc_exec_command_mmio, 172 .check_atapi_dma = pdc_check_atapi_dma, 173 .qc_prep = pdc_qc_prep, 174 .qc_issue = pdc_qc_issue, 175 .sff_irq_clear = pdc_irq_clear, 176 177 .post_internal_cmd = pdc_post_internal_cmd, 178 .error_handler = pdc_error_handler, 179 }; 180 181 static struct ata_port_operations pdc_sata_ops = { 182 .inherits = &pdc_common_ops, 183 .cable_detect = pdc_sata_cable_detect, 184 .freeze = pdc_sata_freeze, 185 .thaw = pdc_sata_thaw, 186 .scr_read = pdc_sata_scr_read, 187 .scr_write = pdc_sata_scr_write, 188 .port_start = pdc_sata_port_start, 189 }; 190 191 /* First-generation chips need a more restrictive ->check_atapi_dma op */ 192 static struct ata_port_operations pdc_old_sata_ops = { 193 .inherits = &pdc_sata_ops, 194 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 195 }; 196 197 static struct ata_port_operations pdc_pata_ops = { 198 .inherits = &pdc_common_ops, 199 .cable_detect = pdc_pata_cable_detect, 200 .freeze = pdc_freeze, 201 .thaw = pdc_thaw, 202 .port_start = pdc_common_port_start, 203 }; 204 205 static const struct ata_port_info pdc_port_info[] = { 206 [board_2037x] = 207 { 208 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 209 PDC_FLAG_SATA_PATA, 210 .pio_mask = 0x1f, /* pio0-4 */ 211 .mwdma_mask = 0x07, /* mwdma0-2 */ 212 .udma_mask = ATA_UDMA6, 213 .port_ops = &pdc_old_sata_ops, 214 }, 215 216 [board_2037x_pata] = 217 { 218 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 219 .pio_mask = 0x1f, /* pio0-4 */ 220 .mwdma_mask = 0x07, /* mwdma0-2 */ 221 .udma_mask = ATA_UDMA6, 222 .port_ops = &pdc_pata_ops, 223 }, 224 225 [board_20319] = 226 { 227 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 228 PDC_FLAG_4_PORTS, 229 .pio_mask = 0x1f, /* pio0-4 */ 230 .mwdma_mask = 0x07, /* mwdma0-2 */ 231 .udma_mask = ATA_UDMA6, 232 .port_ops = &pdc_old_sata_ops, 233 }, 234 235 [board_20619] = 236 { 237 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 238 PDC_FLAG_4_PORTS, 239 .pio_mask = 0x1f, /* pio0-4 */ 240 .mwdma_mask = 0x07, /* mwdma0-2 */ 241 .udma_mask = ATA_UDMA6, 242 .port_ops = &pdc_pata_ops, 243 }, 244 245 [board_2057x] = 246 { 247 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 248 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, 249 .pio_mask = 0x1f, /* pio0-4 */ 250 .mwdma_mask = 0x07, /* mwdma0-2 */ 251 .udma_mask = ATA_UDMA6, 252 .port_ops = &pdc_sata_ops, 253 }, 254 255 [board_2057x_pata] = 256 { 257 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 258 PDC_FLAG_GEN_II, 259 .pio_mask = 0x1f, /* pio0-4 */ 260 .mwdma_mask = 0x07, /* mwdma0-2 */ 261 .udma_mask = ATA_UDMA6, 262 .port_ops = &pdc_pata_ops, 263 }, 264 265 [board_40518] = 266 { 267 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 268 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, 269 .pio_mask = 0x1f, /* pio0-4 */ 270 .mwdma_mask = 0x07, /* mwdma0-2 */ 271 .udma_mask = ATA_UDMA6, 272 .port_ops = &pdc_sata_ops, 273 }, 274 }; 275 276 static const struct pci_device_id pdc_ata_pci_tbl[] = { 277 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 278 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 279 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 280 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 281 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, 282 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, 283 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 284 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, 285 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, 286 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 287 288 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 289 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 290 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, 291 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, 292 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, 293 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 294 295 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 296 297 { } /* terminate list */ 298 }; 299 300 static struct pci_driver pdc_ata_pci_driver = { 301 .name = DRV_NAME, 302 .id_table = pdc_ata_pci_tbl, 303 .probe = pdc_ata_init_one, 304 .remove = ata_pci_remove_one, 305 }; 306 307 static int pdc_common_port_start(struct ata_port *ap) 308 { 309 struct device *dev = ap->host->dev; 310 struct pdc_port_priv *pp; 311 int rc; 312 313 rc = ata_port_start(ap); 314 if (rc) 315 return rc; 316 317 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 318 if (!pp) 319 return -ENOMEM; 320 321 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 322 if (!pp->pkt) 323 return -ENOMEM; 324 325 ap->private_data = pp; 326 327 return 0; 328 } 329 330 static int pdc_sata_port_start(struct ata_port *ap) 331 { 332 int rc; 333 334 rc = pdc_common_port_start(ap); 335 if (rc) 336 return rc; 337 338 /* fix up PHYMODE4 align timing */ 339 if (ap->flags & PDC_FLAG_GEN_II) { 340 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 341 unsigned int tmp; 342 343 tmp = readl(sata_mmio + PDC_PHYMODE4); 344 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 345 writel(tmp, sata_mmio + PDC_PHYMODE4); 346 } 347 348 return 0; 349 } 350 351 static void pdc_reset_port(struct ata_port *ap) 352 { 353 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 354 unsigned int i; 355 u32 tmp; 356 357 for (i = 11; i > 0; i--) { 358 tmp = readl(ata_ctlstat_mmio); 359 if (tmp & PDC_RESET) 360 break; 361 362 udelay(100); 363 364 tmp |= PDC_RESET; 365 writel(tmp, ata_ctlstat_mmio); 366 } 367 368 tmp &= ~PDC_RESET; 369 writel(tmp, ata_ctlstat_mmio); 370 readl(ata_ctlstat_mmio); /* flush */ 371 } 372 373 static int pdc_pata_cable_detect(struct ata_port *ap) 374 { 375 u8 tmp; 376 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 377 378 tmp = readb(ata_mmio + PDC_CTLSTAT + 3); 379 if (tmp & 0x01) 380 return ATA_CBL_PATA40; 381 return ATA_CBL_PATA80; 382 } 383 384 static int pdc_sata_cable_detect(struct ata_port *ap) 385 { 386 return ATA_CBL_SATA; 387 } 388 389 static int pdc_sata_scr_read(struct ata_link *link, 390 unsigned int sc_reg, u32 *val) 391 { 392 if (sc_reg > SCR_CONTROL) 393 return -EINVAL; 394 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); 395 return 0; 396 } 397 398 static int pdc_sata_scr_write(struct ata_link *link, 399 unsigned int sc_reg, u32 val) 400 { 401 if (sc_reg > SCR_CONTROL) 402 return -EINVAL; 403 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); 404 return 0; 405 } 406 407 static void pdc_atapi_pkt(struct ata_queued_cmd *qc) 408 { 409 struct ata_port *ap = qc->ap; 410 dma_addr_t sg_table = ap->prd_dma; 411 unsigned int cdb_len = qc->dev->cdb_len; 412 u8 *cdb = qc->cdb; 413 struct pdc_port_priv *pp = ap->private_data; 414 u8 *buf = pp->pkt; 415 __le32 *buf32 = (__le32 *) buf; 416 unsigned int dev_sel, feature; 417 418 /* set control bits (byte 0), zero delay seq id (byte 3), 419 * and seq id (byte 2) 420 */ 421 switch (qc->tf.protocol) { 422 case ATAPI_PROT_DMA: 423 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 424 buf32[0] = cpu_to_le32(PDC_PKT_READ); 425 else 426 buf32[0] = 0; 427 break; 428 case ATAPI_PROT_NODATA: 429 buf32[0] = cpu_to_le32(PDC_PKT_NODATA); 430 break; 431 default: 432 BUG(); 433 break; 434 } 435 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 436 buf32[2] = 0; /* no next-packet */ 437 438 /* select drive */ 439 if (sata_scr_valid(&ap->link)) 440 dev_sel = PDC_DEVICE_SATA; 441 else 442 dev_sel = qc->tf.device; 443 444 buf[12] = (1 << 5) | ATA_REG_DEVICE; 445 buf[13] = dev_sel; 446 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; 447 buf[15] = dev_sel; /* once more, waiting for BSY to clear */ 448 449 buf[16] = (1 << 5) | ATA_REG_NSECT; 450 buf[17] = qc->tf.nsect; 451 buf[18] = (1 << 5) | ATA_REG_LBAL; 452 buf[19] = qc->tf.lbal; 453 454 /* set feature and byte counter registers */ 455 if (qc->tf.protocol != ATAPI_PROT_DMA) 456 feature = PDC_FEATURE_ATAPI_PIO; 457 else 458 feature = PDC_FEATURE_ATAPI_DMA; 459 460 buf[20] = (1 << 5) | ATA_REG_FEATURE; 461 buf[21] = feature; 462 buf[22] = (1 << 5) | ATA_REG_BYTEL; 463 buf[23] = qc->tf.lbam; 464 buf[24] = (1 << 5) | ATA_REG_BYTEH; 465 buf[25] = qc->tf.lbah; 466 467 /* send ATAPI packet command 0xA0 */ 468 buf[26] = (1 << 5) | ATA_REG_CMD; 469 buf[27] = qc->tf.command; 470 471 /* select drive and check DRQ */ 472 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; 473 buf[29] = dev_sel; 474 475 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 476 BUG_ON(cdb_len & ~0x1E); 477 478 /* append the CDB as the final part */ 479 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 480 memcpy(buf+31, cdb, cdb_len); 481 } 482 483 /** 484 * pdc_fill_sg - Fill PCI IDE PRD table 485 * @qc: Metadata associated with taskfile to be transferred 486 * 487 * Fill PCI IDE PRD (scatter-gather) table with segments 488 * associated with the current disk command. 489 * Make sure hardware does not choke on it. 490 * 491 * LOCKING: 492 * spin_lock_irqsave(host lock) 493 * 494 */ 495 static void pdc_fill_sg(struct ata_queued_cmd *qc) 496 { 497 struct ata_port *ap = qc->ap; 498 struct scatterlist *sg; 499 const u32 SG_COUNT_ASIC_BUG = 41*4; 500 unsigned int si, idx; 501 u32 len; 502 503 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 504 return; 505 506 idx = 0; 507 for_each_sg(qc->sg, sg, qc->n_elem, si) { 508 u32 addr, offset; 509 u32 sg_len; 510 511 /* determine if physical DMA addr spans 64K boundary. 512 * Note h/w doesn't support 64-bit, so we unconditionally 513 * truncate dma_addr_t to u32. 514 */ 515 addr = (u32) sg_dma_address(sg); 516 sg_len = sg_dma_len(sg); 517 518 while (sg_len) { 519 offset = addr & 0xffff; 520 len = sg_len; 521 if ((offset + sg_len) > 0x10000) 522 len = 0x10000 - offset; 523 524 ap->prd[idx].addr = cpu_to_le32(addr); 525 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff); 526 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 527 528 idx++; 529 sg_len -= len; 530 addr += len; 531 } 532 } 533 534 len = le32_to_cpu(ap->prd[idx - 1].flags_len); 535 536 if (len > SG_COUNT_ASIC_BUG) { 537 u32 addr; 538 539 VPRINTK("Splitting last PRD.\n"); 540 541 addr = le32_to_cpu(ap->prd[idx - 1].addr); 542 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG); 543 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG); 544 545 addr = addr + len - SG_COUNT_ASIC_BUG; 546 len = SG_COUNT_ASIC_BUG; 547 ap->prd[idx].addr = cpu_to_le32(addr); 548 ap->prd[idx].flags_len = cpu_to_le32(len); 549 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 550 551 idx++; 552 } 553 554 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 555 } 556 557 static void pdc_qc_prep(struct ata_queued_cmd *qc) 558 { 559 struct pdc_port_priv *pp = qc->ap->private_data; 560 unsigned int i; 561 562 VPRINTK("ENTER\n"); 563 564 switch (qc->tf.protocol) { 565 case ATA_PROT_DMA: 566 pdc_fill_sg(qc); 567 /*FALLTHROUGH*/ 568 case ATA_PROT_NODATA: 569 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, 570 qc->dev->devno, pp->pkt); 571 if (qc->tf.flags & ATA_TFLAG_LBA48) 572 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 573 else 574 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 575 pdc_pkt_footer(&qc->tf, pp->pkt, i); 576 break; 577 case ATAPI_PROT_PIO: 578 pdc_fill_sg(qc); 579 break; 580 case ATAPI_PROT_DMA: 581 pdc_fill_sg(qc); 582 /*FALLTHROUGH*/ 583 case ATAPI_PROT_NODATA: 584 pdc_atapi_pkt(qc); 585 break; 586 default: 587 break; 588 } 589 } 590 591 static int pdc_is_sataii_tx4(unsigned long flags) 592 { 593 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; 594 return (flags & mask) == mask; 595 } 596 597 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, 598 int is_sataii_tx4) 599 { 600 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; 601 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; 602 } 603 604 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap) 605 { 606 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2; 607 } 608 609 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap) 610 { 611 const struct ata_host *host = ap->host; 612 unsigned int nr_ports = pdc_sata_nr_ports(ap); 613 unsigned int i; 614 615 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i) 616 ; 617 BUG_ON(i >= nr_ports); 618 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags)); 619 } 620 621 static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap) 622 { 623 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR; 624 } 625 626 static void pdc_freeze(struct ata_port *ap) 627 { 628 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 629 u32 tmp; 630 631 tmp = readl(ata_mmio + PDC_CTLSTAT); 632 tmp |= PDC_IRQ_DISABLE; 633 tmp &= ~PDC_DMA_ENABLE; 634 writel(tmp, ata_mmio + PDC_CTLSTAT); 635 readl(ata_mmio + PDC_CTLSTAT); /* flush */ 636 } 637 638 static void pdc_sata_freeze(struct ata_port *ap) 639 { 640 struct ata_host *host = ap->host; 641 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 642 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap); 643 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 644 u32 hotplug_status; 645 646 /* Disable hotplug events on this port. 647 * 648 * Locking: 649 * 1) hotplug register accesses must be serialised via host->lock 650 * 2) ap->lock == &ap->host->lock 651 * 3) ->freeze() and ->thaw() are called with ap->lock held 652 */ 653 hotplug_status = readl(host_mmio + hotplug_offset); 654 hotplug_status |= 0x11 << (ata_no + 16); 655 writel(hotplug_status, host_mmio + hotplug_offset); 656 readl(host_mmio + hotplug_offset); /* flush */ 657 658 pdc_freeze(ap); 659 } 660 661 static void pdc_thaw(struct ata_port *ap) 662 { 663 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 664 u32 tmp; 665 666 /* clear IRQ */ 667 readl(ata_mmio + PDC_COMMAND); 668 669 /* turn IRQ back on */ 670 tmp = readl(ata_mmio + PDC_CTLSTAT); 671 tmp &= ~PDC_IRQ_DISABLE; 672 writel(tmp, ata_mmio + PDC_CTLSTAT); 673 readl(ata_mmio + PDC_CTLSTAT); /* flush */ 674 } 675 676 static void pdc_sata_thaw(struct ata_port *ap) 677 { 678 struct ata_host *host = ap->host; 679 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 680 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap); 681 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 682 u32 hotplug_status; 683 684 pdc_thaw(ap); 685 686 /* Enable hotplug events on this port. 687 * Locking: see pdc_sata_freeze(). 688 */ 689 hotplug_status = readl(host_mmio + hotplug_offset); 690 hotplug_status |= 0x11 << ata_no; 691 hotplug_status &= ~(0x11 << (ata_no + 16)); 692 writel(hotplug_status, host_mmio + hotplug_offset); 693 readl(host_mmio + hotplug_offset); /* flush */ 694 } 695 696 static void pdc_error_handler(struct ata_port *ap) 697 { 698 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 699 pdc_reset_port(ap); 700 701 ata_std_error_handler(ap); 702 } 703 704 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 705 { 706 struct ata_port *ap = qc->ap; 707 708 /* make DMA engine forget about the failed command */ 709 if (qc->flags & ATA_QCFLAG_FAILED) 710 pdc_reset_port(ap); 711 } 712 713 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, 714 u32 port_status, u32 err_mask) 715 { 716 struct ata_eh_info *ehi = &ap->link.eh_info; 717 unsigned int ac_err_mask = 0; 718 719 ata_ehi_clear_desc(ehi); 720 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); 721 port_status &= err_mask; 722 723 if (port_status & PDC_DRIVE_ERR) 724 ac_err_mask |= AC_ERR_DEV; 725 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) 726 ac_err_mask |= AC_ERR_HSM; 727 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) 728 ac_err_mask |= AC_ERR_ATA_BUS; 729 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR 730 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) 731 ac_err_mask |= AC_ERR_HOST_BUS; 732 733 if (sata_scr_valid(&ap->link)) { 734 u32 serror; 735 736 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror); 737 ehi->serror |= serror; 738 } 739 740 qc->err_mask |= ac_err_mask; 741 742 pdc_reset_port(ap); 743 744 ata_port_abort(ap); 745 } 746 747 static unsigned int pdc_host_intr(struct ata_port *ap, 748 struct ata_queued_cmd *qc) 749 { 750 unsigned int handled = 0; 751 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 752 u32 port_status, err_mask; 753 754 err_mask = PDC_ERR_MASK; 755 if (ap->flags & PDC_FLAG_GEN_II) 756 err_mask &= ~PDC1_ERR_MASK; 757 else 758 err_mask &= ~PDC2_ERR_MASK; 759 port_status = readl(ata_mmio + PDC_GLOBAL_CTL); 760 if (unlikely(port_status & err_mask)) { 761 pdc_error_intr(ap, qc, port_status, err_mask); 762 return 1; 763 } 764 765 switch (qc->tf.protocol) { 766 case ATA_PROT_DMA: 767 case ATA_PROT_NODATA: 768 case ATAPI_PROT_DMA: 769 case ATAPI_PROT_NODATA: 770 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 771 ata_qc_complete(qc); 772 handled = 1; 773 break; 774 default: 775 ap->stats.idle_irq++; 776 break; 777 } 778 779 return handled; 780 } 781 782 static void pdc_irq_clear(struct ata_port *ap) 783 { 784 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 785 786 readl(ata_mmio + PDC_COMMAND); 787 } 788 789 static irqreturn_t pdc_interrupt(int irq, void *dev_instance) 790 { 791 struct ata_host *host = dev_instance; 792 struct ata_port *ap; 793 u32 mask = 0; 794 unsigned int i, tmp; 795 unsigned int handled = 0; 796 void __iomem *host_mmio; 797 unsigned int hotplug_offset, ata_no; 798 u32 hotplug_status; 799 int is_sataii_tx4; 800 801 VPRINTK("ENTER\n"); 802 803 if (!host || !host->iomap[PDC_MMIO_BAR]) { 804 VPRINTK("QUICK EXIT\n"); 805 return IRQ_NONE; 806 } 807 808 host_mmio = host->iomap[PDC_MMIO_BAR]; 809 810 spin_lock(&host->lock); 811 812 /* read and clear hotplug flags for all ports */ 813 if (host->ports[0]->flags & PDC_FLAG_GEN_II) 814 hotplug_offset = PDC2_SATA_PLUG_CSR; 815 else 816 hotplug_offset = PDC_SATA_PLUG_CSR; 817 hotplug_status = readl(host_mmio + hotplug_offset); 818 if (hotplug_status & 0xff) 819 writel(hotplug_status | 0xff, host_mmio + hotplug_offset); 820 hotplug_status &= 0xff; /* clear uninteresting bits */ 821 822 /* reading should also clear interrupts */ 823 mask = readl(host_mmio + PDC_INT_SEQMASK); 824 825 if (mask == 0xffffffff && hotplug_status == 0) { 826 VPRINTK("QUICK EXIT 2\n"); 827 goto done_irq; 828 } 829 830 mask &= 0xffff; /* only 16 SEQIDs possible */ 831 if (mask == 0 && hotplug_status == 0) { 832 VPRINTK("QUICK EXIT 3\n"); 833 goto done_irq; 834 } 835 836 writel(mask, host_mmio + PDC_INT_SEQMASK); 837 838 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); 839 840 for (i = 0; i < host->n_ports; i++) { 841 VPRINTK("port %u\n", i); 842 ap = host->ports[i]; 843 844 /* check for a plug or unplug event */ 845 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 846 tmp = hotplug_status & (0x11 << ata_no); 847 if (tmp && ap && 848 !(ap->flags & ATA_FLAG_DISABLED)) { 849 struct ata_eh_info *ehi = &ap->link.eh_info; 850 ata_ehi_clear_desc(ehi); 851 ata_ehi_hotplugged(ehi); 852 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); 853 ata_port_freeze(ap); 854 ++handled; 855 continue; 856 } 857 858 /* check for a packet interrupt */ 859 tmp = mask & (1 << (i + 1)); 860 if (tmp && ap && 861 !(ap->flags & ATA_FLAG_DISABLED)) { 862 struct ata_queued_cmd *qc; 863 864 qc = ata_qc_from_tag(ap, ap->link.active_tag); 865 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 866 handled += pdc_host_intr(ap, qc); 867 } 868 } 869 870 VPRINTK("EXIT\n"); 871 872 done_irq: 873 spin_unlock(&host->lock); 874 return IRQ_RETVAL(handled); 875 } 876 877 static void pdc_packet_start(struct ata_queued_cmd *qc) 878 { 879 struct ata_port *ap = qc->ap; 880 struct pdc_port_priv *pp = ap->private_data; 881 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; 882 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 883 unsigned int port_no = ap->port_no; 884 u8 seq = (u8) (port_no + 1); 885 886 VPRINTK("ENTER, ap %p\n", ap); 887 888 writel(0x00000001, host_mmio + (seq * 4)); 889 readl(host_mmio + (seq * 4)); /* flush */ 890 891 pp->pkt[2] = seq; 892 wmb(); /* flush PRD, pkt writes */ 893 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT); 894 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */ 895 } 896 897 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) 898 { 899 switch (qc->tf.protocol) { 900 case ATAPI_PROT_NODATA: 901 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 902 break; 903 /*FALLTHROUGH*/ 904 case ATA_PROT_NODATA: 905 if (qc->tf.flags & ATA_TFLAG_POLLING) 906 break; 907 /*FALLTHROUGH*/ 908 case ATAPI_PROT_DMA: 909 case ATA_PROT_DMA: 910 pdc_packet_start(qc); 911 return 0; 912 default: 913 break; 914 } 915 return ata_sff_qc_issue(qc); 916 } 917 918 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 919 { 920 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 921 ata_sff_tf_load(ap, tf); 922 } 923 924 static void pdc_exec_command_mmio(struct ata_port *ap, 925 const struct ata_taskfile *tf) 926 { 927 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 928 ata_sff_exec_command(ap, tf); 929 } 930 931 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) 932 { 933 u8 *scsicmd = qc->scsicmd->cmnd; 934 int pio = 1; /* atapi dma off by default */ 935 936 /* Whitelist commands that may use DMA. */ 937 switch (scsicmd[0]) { 938 case WRITE_12: 939 case WRITE_10: 940 case WRITE_6: 941 case READ_12: 942 case READ_10: 943 case READ_6: 944 case 0xad: /* READ_DVD_STRUCTURE */ 945 case 0xbe: /* READ_CD */ 946 pio = 0; 947 } 948 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ 949 if (scsicmd[0] == WRITE_10) { 950 unsigned int lba = 951 (scsicmd[2] << 24) | 952 (scsicmd[3] << 16) | 953 (scsicmd[4] << 8) | 954 scsicmd[5]; 955 if (lba >= 0xFFFF4FA2) 956 pio = 1; 957 } 958 return pio; 959 } 960 961 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) 962 { 963 /* First generation chips cannot use ATAPI DMA on SATA ports */ 964 return 1; 965 } 966 967 static void pdc_ata_setup_port(struct ata_port *ap, 968 void __iomem *base, void __iomem *scr_addr) 969 { 970 ap->ioaddr.cmd_addr = base; 971 ap->ioaddr.data_addr = base; 972 ap->ioaddr.feature_addr = 973 ap->ioaddr.error_addr = base + 0x4; 974 ap->ioaddr.nsect_addr = base + 0x8; 975 ap->ioaddr.lbal_addr = base + 0xc; 976 ap->ioaddr.lbam_addr = base + 0x10; 977 ap->ioaddr.lbah_addr = base + 0x14; 978 ap->ioaddr.device_addr = base + 0x18; 979 ap->ioaddr.command_addr = 980 ap->ioaddr.status_addr = base + 0x1c; 981 ap->ioaddr.altstatus_addr = 982 ap->ioaddr.ctl_addr = base + 0x38; 983 ap->ioaddr.scr_addr = scr_addr; 984 } 985 986 static void pdc_host_init(struct ata_host *host) 987 { 988 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 989 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 990 int hotplug_offset; 991 u32 tmp; 992 993 if (is_gen2) 994 hotplug_offset = PDC2_SATA_PLUG_CSR; 995 else 996 hotplug_offset = PDC_SATA_PLUG_CSR; 997 998 /* 999 * Except for the hotplug stuff, this is voodoo from the 1000 * Promise driver. Label this entire section 1001 * "TODO: figure out why we do this" 1002 */ 1003 1004 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 1005 tmp = readl(host_mmio + PDC_FLASH_CTL); 1006 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 1007 if (!is_gen2) 1008 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 1009 writel(tmp, host_mmio + PDC_FLASH_CTL); 1010 1011 /* clear plug/unplug flags for all ports */ 1012 tmp = readl(host_mmio + hotplug_offset); 1013 writel(tmp | 0xff, host_mmio + hotplug_offset); 1014 1015 /* unmask plug/unplug ints */ 1016 tmp = readl(host_mmio + hotplug_offset); 1017 writel(tmp & ~0xff0000, host_mmio + hotplug_offset); 1018 1019 /* don't initialise TBG or SLEW on 2nd generation chips */ 1020 if (is_gen2) 1021 return; 1022 1023 /* reduce TBG clock to 133 Mhz. */ 1024 tmp = readl(host_mmio + PDC_TBG_MODE); 1025 tmp &= ~0x30000; /* clear bit 17, 16*/ 1026 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 1027 writel(tmp, host_mmio + PDC_TBG_MODE); 1028 1029 readl(host_mmio + PDC_TBG_MODE); /* flush */ 1030 msleep(10); 1031 1032 /* adjust slew rate control register. */ 1033 tmp = readl(host_mmio + PDC_SLEW_CTL); 1034 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 1035 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 1036 writel(tmp, host_mmio + PDC_SLEW_CTL); 1037 } 1038 1039 static int pdc_ata_init_one(struct pci_dev *pdev, 1040 const struct pci_device_id *ent) 1041 { 1042 static int printed_version; 1043 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 1044 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 1045 struct ata_host *host; 1046 void __iomem *host_mmio; 1047 int n_ports, i, rc; 1048 int is_sataii_tx4; 1049 1050 if (!printed_version++) 1051 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1052 1053 /* enable and acquire resources */ 1054 rc = pcim_enable_device(pdev); 1055 if (rc) 1056 return rc; 1057 1058 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 1059 if (rc == -EBUSY) 1060 pcim_pin_device(pdev); 1061 if (rc) 1062 return rc; 1063 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 1064 1065 /* determine port configuration and setup host */ 1066 n_ports = 2; 1067 if (pi->flags & PDC_FLAG_4_PORTS) 1068 n_ports = 4; 1069 for (i = 0; i < n_ports; i++) 1070 ppi[i] = pi; 1071 1072 if (pi->flags & PDC_FLAG_SATA_PATA) { 1073 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1); 1074 if (!(tmp & 0x80)) 1075 ppi[n_ports++] = pi + 1; 1076 } 1077 1078 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1079 if (!host) { 1080 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); 1081 return -ENOMEM; 1082 } 1083 host->iomap = pcim_iomap_table(pdev); 1084 1085 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); 1086 for (i = 0; i < host->n_ports; i++) { 1087 struct ata_port *ap = host->ports[i]; 1088 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 1089 unsigned int ata_offset = 0x200 + ata_no * 0x80; 1090 unsigned int scr_offset = 0x400 + ata_no * 0x100; 1091 1092 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset); 1093 1094 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 1095 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata"); 1096 } 1097 1098 /* initialize adapter */ 1099 pdc_host_init(host); 1100 1101 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 1102 if (rc) 1103 return rc; 1104 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 1105 if (rc) 1106 return rc; 1107 1108 /* start host, request IRQ and attach */ 1109 pci_set_master(pdev); 1110 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, 1111 &pdc_ata_sht); 1112 } 1113 1114 static int __init pdc_ata_init(void) 1115 { 1116 return pci_register_driver(&pdc_ata_pci_driver); 1117 } 1118 1119 static void __exit pdc_ata_exit(void) 1120 { 1121 pci_unregister_driver(&pdc_ata_pci_driver); 1122 } 1123 1124 MODULE_AUTHOR("Jeff Garzik"); 1125 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); 1126 MODULE_LICENSE("GPL"); 1127 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); 1128 MODULE_VERSION(DRV_VERSION); 1129 1130 module_init(pdc_ata_init); 1131 module_exit(pdc_ata_exit); 1132