1 /* 2 * sata_promise.c - Promise SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2004 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * Hardware information only available under NDA. 30 * 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/init.h> 37 #include <linux/blkdev.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/device.h> 41 #include <scsi/scsi.h> 42 #include <scsi/scsi_host.h> 43 #include <scsi/scsi_cmnd.h> 44 #include <linux/libata.h> 45 #include "sata_promise.h" 46 47 #define DRV_NAME "sata_promise" 48 #define DRV_VERSION "2.08" 49 50 enum { 51 PDC_MAX_PORTS = 4, 52 PDC_MMIO_BAR = 3, 53 54 /* register offsets */ 55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ 59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ 60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ 61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 65 PDC_FLASH_CTL = 0x44, /* Flash control register */ 66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 72 73 /* PDC_GLOBAL_CTL bit definitions */ 74 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 75 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ 76 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ 77 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ 78 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ 79 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ 80 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ 81 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ 82 PDC_DRIVE_ERR = (1 << 21), /* drive error */ 83 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ 84 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ 85 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, 86 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR, 87 PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR 88 | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR 89 | PDC1_ERR_MASK | PDC2_ERR_MASK), 90 91 board_2037x = 0, /* FastTrak S150 TX2plus */ 92 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ 93 board_20319 = 2, /* FastTrak S150 TX4 */ 94 board_20619 = 3, /* FastTrak TX4000 */ 95 board_2057x = 4, /* SATAII150 Tx2plus */ 96 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ 97 board_40518 = 6, /* SATAII150 Tx4 */ 98 99 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 100 101 /* Sequence counter control registers bit definitions */ 102 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ 103 104 /* Feature register values */ 105 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ 106 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ 107 108 /* Device/Head register values */ 109 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ 110 111 /* PDC_CTLSTAT bit definitions */ 112 PDC_DMA_ENABLE = (1 << 7), 113 PDC_IRQ_DISABLE = (1 << 10), 114 PDC_RESET = (1 << 11), /* HDMA reset */ 115 116 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | 117 ATA_FLAG_MMIO | 118 ATA_FLAG_PIO_POLLING, 119 120 /* ap->flags bits */ 121 PDC_FLAG_GEN_II = (1 << 24), 122 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ 123 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ 124 }; 125 126 struct pdc_port_priv { 127 u8 *pkt; 128 dma_addr_t pkt_dma; 129 }; 130 131 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); 132 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 133 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 134 static int pdc_common_port_start(struct ata_port *ap); 135 static int pdc_sata_port_start(struct ata_port *ap); 136 static void pdc_qc_prep(struct ata_queued_cmd *qc); 137 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 138 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 139 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 140 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); 141 static void pdc_irq_clear(struct ata_port *ap); 142 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); 143 static void pdc_freeze(struct ata_port *ap); 144 static void pdc_thaw(struct ata_port *ap); 145 static void pdc_pata_error_handler(struct ata_port *ap); 146 static void pdc_sata_error_handler(struct ata_port *ap); 147 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 148 static int pdc_pata_cable_detect(struct ata_port *ap); 149 static int pdc_sata_cable_detect(struct ata_port *ap); 150 151 static struct scsi_host_template pdc_ata_sht = { 152 .module = THIS_MODULE, 153 .name = DRV_NAME, 154 .ioctl = ata_scsi_ioctl, 155 .queuecommand = ata_scsi_queuecmd, 156 .can_queue = ATA_DEF_QUEUE, 157 .this_id = ATA_SHT_THIS_ID, 158 .sg_tablesize = LIBATA_MAX_PRD, 159 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 160 .emulated = ATA_SHT_EMULATED, 161 .use_clustering = ATA_SHT_USE_CLUSTERING, 162 .proc_name = DRV_NAME, 163 .dma_boundary = ATA_DMA_BOUNDARY, 164 .slave_configure = ata_scsi_slave_config, 165 .slave_destroy = ata_scsi_slave_destroy, 166 .bios_param = ata_std_bios_param, 167 }; 168 169 static const struct ata_port_operations pdc_sata_ops = { 170 .port_disable = ata_port_disable, 171 .tf_load = pdc_tf_load_mmio, 172 .tf_read = ata_tf_read, 173 .check_status = ata_check_status, 174 .exec_command = pdc_exec_command_mmio, 175 .dev_select = ata_std_dev_select, 176 .check_atapi_dma = pdc_check_atapi_dma, 177 178 .qc_prep = pdc_qc_prep, 179 .qc_issue = pdc_qc_issue_prot, 180 .freeze = pdc_freeze, 181 .thaw = pdc_thaw, 182 .error_handler = pdc_sata_error_handler, 183 .post_internal_cmd = pdc_post_internal_cmd, 184 .cable_detect = pdc_sata_cable_detect, 185 .data_xfer = ata_data_xfer, 186 .irq_clear = pdc_irq_clear, 187 .irq_on = ata_irq_on, 188 .irq_ack = ata_irq_ack, 189 190 .scr_read = pdc_sata_scr_read, 191 .scr_write = pdc_sata_scr_write, 192 .port_start = pdc_sata_port_start, 193 }; 194 195 /* First-generation chips need a more restrictive ->check_atapi_dma op */ 196 static const struct ata_port_operations pdc_old_sata_ops = { 197 .port_disable = ata_port_disable, 198 .tf_load = pdc_tf_load_mmio, 199 .tf_read = ata_tf_read, 200 .check_status = ata_check_status, 201 .exec_command = pdc_exec_command_mmio, 202 .dev_select = ata_std_dev_select, 203 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 204 205 .qc_prep = pdc_qc_prep, 206 .qc_issue = pdc_qc_issue_prot, 207 .freeze = pdc_freeze, 208 .thaw = pdc_thaw, 209 .error_handler = pdc_sata_error_handler, 210 .post_internal_cmd = pdc_post_internal_cmd, 211 .cable_detect = pdc_sata_cable_detect, 212 .data_xfer = ata_data_xfer, 213 .irq_clear = pdc_irq_clear, 214 .irq_on = ata_irq_on, 215 .irq_ack = ata_irq_ack, 216 217 .scr_read = pdc_sata_scr_read, 218 .scr_write = pdc_sata_scr_write, 219 .port_start = pdc_sata_port_start, 220 }; 221 222 static const struct ata_port_operations pdc_pata_ops = { 223 .port_disable = ata_port_disable, 224 .tf_load = pdc_tf_load_mmio, 225 .tf_read = ata_tf_read, 226 .check_status = ata_check_status, 227 .exec_command = pdc_exec_command_mmio, 228 .dev_select = ata_std_dev_select, 229 .check_atapi_dma = pdc_check_atapi_dma, 230 231 .qc_prep = pdc_qc_prep, 232 .qc_issue = pdc_qc_issue_prot, 233 .freeze = pdc_freeze, 234 .thaw = pdc_thaw, 235 .error_handler = pdc_pata_error_handler, 236 .post_internal_cmd = pdc_post_internal_cmd, 237 .cable_detect = pdc_pata_cable_detect, 238 .data_xfer = ata_data_xfer, 239 .irq_clear = pdc_irq_clear, 240 .irq_on = ata_irq_on, 241 .irq_ack = ata_irq_ack, 242 243 .port_start = pdc_common_port_start, 244 }; 245 246 static const struct ata_port_info pdc_port_info[] = { 247 /* board_2037x */ 248 { 249 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 250 PDC_FLAG_SATA_PATA, 251 .pio_mask = 0x1f, /* pio0-4 */ 252 .mwdma_mask = 0x07, /* mwdma0-2 */ 253 .udma_mask = ATA_UDMA6, 254 .port_ops = &pdc_old_sata_ops, 255 }, 256 257 /* board_2037x_pata */ 258 { 259 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 260 .pio_mask = 0x1f, /* pio0-4 */ 261 .mwdma_mask = 0x07, /* mwdma0-2 */ 262 .udma_mask = ATA_UDMA6, 263 .port_ops = &pdc_pata_ops, 264 }, 265 266 /* board_20319 */ 267 { 268 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 269 PDC_FLAG_4_PORTS, 270 .pio_mask = 0x1f, /* pio0-4 */ 271 .mwdma_mask = 0x07, /* mwdma0-2 */ 272 .udma_mask = ATA_UDMA6, 273 .port_ops = &pdc_old_sata_ops, 274 }, 275 276 /* board_20619 */ 277 { 278 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 279 PDC_FLAG_4_PORTS, 280 .pio_mask = 0x1f, /* pio0-4 */ 281 .mwdma_mask = 0x07, /* mwdma0-2 */ 282 .udma_mask = ATA_UDMA6, 283 .port_ops = &pdc_pata_ops, 284 }, 285 286 /* board_2057x */ 287 { 288 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 289 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, 290 .pio_mask = 0x1f, /* pio0-4 */ 291 .mwdma_mask = 0x07, /* mwdma0-2 */ 292 .udma_mask = ATA_UDMA6, 293 .port_ops = &pdc_sata_ops, 294 }, 295 296 /* board_2057x_pata */ 297 { 298 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 299 PDC_FLAG_GEN_II, 300 .pio_mask = 0x1f, /* pio0-4 */ 301 .mwdma_mask = 0x07, /* mwdma0-2 */ 302 .udma_mask = ATA_UDMA6, 303 .port_ops = &pdc_pata_ops, 304 }, 305 306 /* board_40518 */ 307 { 308 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 309 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, 310 .pio_mask = 0x1f, /* pio0-4 */ 311 .mwdma_mask = 0x07, /* mwdma0-2 */ 312 .udma_mask = ATA_UDMA6, 313 .port_ops = &pdc_sata_ops, 314 }, 315 }; 316 317 static const struct pci_device_id pdc_ata_pci_tbl[] = { 318 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 319 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 320 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 321 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 322 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, 323 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, 324 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 325 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, 326 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, 327 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 328 329 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 330 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 331 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, 332 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, 333 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, 334 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 335 336 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 337 338 { } /* terminate list */ 339 }; 340 341 static struct pci_driver pdc_ata_pci_driver = { 342 .name = DRV_NAME, 343 .id_table = pdc_ata_pci_tbl, 344 .probe = pdc_ata_init_one, 345 .remove = ata_pci_remove_one, 346 }; 347 348 static int pdc_common_port_start(struct ata_port *ap) 349 { 350 struct device *dev = ap->host->dev; 351 struct pdc_port_priv *pp; 352 int rc; 353 354 rc = ata_port_start(ap); 355 if (rc) 356 return rc; 357 358 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 359 if (!pp) 360 return -ENOMEM; 361 362 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 363 if (!pp->pkt) 364 return -ENOMEM; 365 366 ap->private_data = pp; 367 368 return 0; 369 } 370 371 static int pdc_sata_port_start(struct ata_port *ap) 372 { 373 int rc; 374 375 rc = pdc_common_port_start(ap); 376 if (rc) 377 return rc; 378 379 /* fix up PHYMODE4 align timing */ 380 if (ap->flags & PDC_FLAG_GEN_II) { 381 void __iomem *mmio = ap->ioaddr.scr_addr; 382 unsigned int tmp; 383 384 tmp = readl(mmio + 0x014); 385 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 386 writel(tmp, mmio + 0x014); 387 } 388 389 return 0; 390 } 391 392 static void pdc_reset_port(struct ata_port *ap) 393 { 394 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 395 unsigned int i; 396 u32 tmp; 397 398 for (i = 11; i > 0; i--) { 399 tmp = readl(mmio); 400 if (tmp & PDC_RESET) 401 break; 402 403 udelay(100); 404 405 tmp |= PDC_RESET; 406 writel(tmp, mmio); 407 } 408 409 tmp &= ~PDC_RESET; 410 writel(tmp, mmio); 411 readl(mmio); /* flush */ 412 } 413 414 static int pdc_pata_cable_detect(struct ata_port *ap) 415 { 416 u8 tmp; 417 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; 418 419 tmp = readb(mmio); 420 if (tmp & 0x01) 421 return ATA_CBL_PATA40; 422 return ATA_CBL_PATA80; 423 } 424 425 static int pdc_sata_cable_detect(struct ata_port *ap) 426 { 427 return ATA_CBL_SATA; 428 } 429 430 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) 431 { 432 if (sc_reg > SCR_CONTROL) 433 return 0xffffffffU; 434 return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 435 } 436 437 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, 438 u32 val) 439 { 440 if (sc_reg > SCR_CONTROL) 441 return; 442 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 443 } 444 445 static void pdc_atapi_pkt(struct ata_queued_cmd *qc) 446 { 447 struct ata_port *ap = qc->ap; 448 dma_addr_t sg_table = ap->prd_dma; 449 unsigned int cdb_len = qc->dev->cdb_len; 450 u8 *cdb = qc->cdb; 451 struct pdc_port_priv *pp = ap->private_data; 452 u8 *buf = pp->pkt; 453 u32 *buf32 = (u32 *) buf; 454 unsigned int dev_sel, feature, nbytes; 455 456 /* set control bits (byte 0), zero delay seq id (byte 3), 457 * and seq id (byte 2) 458 */ 459 switch (qc->tf.protocol) { 460 case ATA_PROT_ATAPI_DMA: 461 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 462 buf32[0] = cpu_to_le32(PDC_PKT_READ); 463 else 464 buf32[0] = 0; 465 break; 466 case ATA_PROT_ATAPI_NODATA: 467 buf32[0] = cpu_to_le32(PDC_PKT_NODATA); 468 break; 469 default: 470 BUG(); 471 break; 472 } 473 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 474 buf32[2] = 0; /* no next-packet */ 475 476 /* select drive */ 477 if (sata_scr_valid(ap)) { 478 dev_sel = PDC_DEVICE_SATA; 479 } else { 480 dev_sel = ATA_DEVICE_OBS; 481 if (qc->dev->devno != 0) 482 dev_sel |= ATA_DEV1; 483 } 484 buf[12] = (1 << 5) | ATA_REG_DEVICE; 485 buf[13] = dev_sel; 486 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; 487 buf[15] = dev_sel; /* once more, waiting for BSY to clear */ 488 489 buf[16] = (1 << 5) | ATA_REG_NSECT; 490 buf[17] = 0x00; 491 buf[18] = (1 << 5) | ATA_REG_LBAL; 492 buf[19] = 0x00; 493 494 /* set feature and byte counter registers */ 495 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { 496 feature = PDC_FEATURE_ATAPI_PIO; 497 /* set byte counter register to real transfer byte count */ 498 nbytes = qc->nbytes; 499 if (nbytes > 0xffff) 500 nbytes = 0xffff; 501 } else { 502 feature = PDC_FEATURE_ATAPI_DMA; 503 /* set byte counter register to 0 */ 504 nbytes = 0; 505 } 506 buf[20] = (1 << 5) | ATA_REG_FEATURE; 507 buf[21] = feature; 508 buf[22] = (1 << 5) | ATA_REG_BYTEL; 509 buf[23] = nbytes & 0xFF; 510 buf[24] = (1 << 5) | ATA_REG_BYTEH; 511 buf[25] = (nbytes >> 8) & 0xFF; 512 513 /* send ATAPI packet command 0xA0 */ 514 buf[26] = (1 << 5) | ATA_REG_CMD; 515 buf[27] = ATA_CMD_PACKET; 516 517 /* select drive and check DRQ */ 518 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; 519 buf[29] = dev_sel; 520 521 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 522 BUG_ON(cdb_len & ~0x1E); 523 524 /* append the CDB as the final part */ 525 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 526 memcpy(buf+31, cdb, cdb_len); 527 } 528 529 static void pdc_qc_prep(struct ata_queued_cmd *qc) 530 { 531 struct pdc_port_priv *pp = qc->ap->private_data; 532 unsigned int i; 533 534 VPRINTK("ENTER\n"); 535 536 switch (qc->tf.protocol) { 537 case ATA_PROT_DMA: 538 ata_qc_prep(qc); 539 /* fall through */ 540 541 case ATA_PROT_NODATA: 542 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, 543 qc->dev->devno, pp->pkt); 544 545 if (qc->tf.flags & ATA_TFLAG_LBA48) 546 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 547 else 548 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 549 550 pdc_pkt_footer(&qc->tf, pp->pkt, i); 551 break; 552 553 case ATA_PROT_ATAPI: 554 ata_qc_prep(qc); 555 break; 556 557 case ATA_PROT_ATAPI_DMA: 558 ata_qc_prep(qc); 559 /*FALLTHROUGH*/ 560 case ATA_PROT_ATAPI_NODATA: 561 pdc_atapi_pkt(qc); 562 break; 563 564 default: 565 break; 566 } 567 } 568 569 static void pdc_freeze(struct ata_port *ap) 570 { 571 void __iomem *mmio = ap->ioaddr.cmd_addr; 572 u32 tmp; 573 574 tmp = readl(mmio + PDC_CTLSTAT); 575 tmp |= PDC_IRQ_DISABLE; 576 tmp &= ~PDC_DMA_ENABLE; 577 writel(tmp, mmio + PDC_CTLSTAT); 578 readl(mmio + PDC_CTLSTAT); /* flush */ 579 } 580 581 static void pdc_thaw(struct ata_port *ap) 582 { 583 void __iomem *mmio = ap->ioaddr.cmd_addr; 584 u32 tmp; 585 586 /* clear IRQ */ 587 readl(mmio + PDC_INT_SEQMASK); 588 589 /* turn IRQ back on */ 590 tmp = readl(mmio + PDC_CTLSTAT); 591 tmp &= ~PDC_IRQ_DISABLE; 592 writel(tmp, mmio + PDC_CTLSTAT); 593 readl(mmio + PDC_CTLSTAT); /* flush */ 594 } 595 596 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset) 597 { 598 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 599 pdc_reset_port(ap); 600 601 /* perform recovery */ 602 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, 603 ata_std_postreset); 604 } 605 606 static void pdc_pata_error_handler(struct ata_port *ap) 607 { 608 pdc_common_error_handler(ap, NULL); 609 } 610 611 static void pdc_sata_error_handler(struct ata_port *ap) 612 { 613 pdc_common_error_handler(ap, sata_std_hardreset); 614 } 615 616 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 617 { 618 struct ata_port *ap = qc->ap; 619 620 /* make DMA engine forget about the failed command */ 621 if (qc->flags & ATA_QCFLAG_FAILED) 622 pdc_reset_port(ap); 623 } 624 625 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, 626 u32 port_status, u32 err_mask) 627 { 628 struct ata_eh_info *ehi = &ap->eh_info; 629 unsigned int ac_err_mask = 0; 630 631 ata_ehi_clear_desc(ehi); 632 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); 633 port_status &= err_mask; 634 635 if (port_status & PDC_DRIVE_ERR) 636 ac_err_mask |= AC_ERR_DEV; 637 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) 638 ac_err_mask |= AC_ERR_HSM; 639 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) 640 ac_err_mask |= AC_ERR_ATA_BUS; 641 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR 642 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) 643 ac_err_mask |= AC_ERR_HOST_BUS; 644 645 if (sata_scr_valid(ap)) 646 ehi->serror |= pdc_sata_scr_read(ap, SCR_ERROR); 647 648 qc->err_mask |= ac_err_mask; 649 650 pdc_reset_port(ap); 651 652 ata_port_abort(ap); 653 } 654 655 static inline unsigned int pdc_host_intr(struct ata_port *ap, 656 struct ata_queued_cmd *qc) 657 { 658 unsigned int handled = 0; 659 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 660 u32 port_status, err_mask; 661 662 err_mask = PDC_ERR_MASK; 663 if (ap->flags & PDC_FLAG_GEN_II) 664 err_mask &= ~PDC1_ERR_MASK; 665 else 666 err_mask &= ~PDC2_ERR_MASK; 667 port_status = readl(port_mmio + PDC_GLOBAL_CTL); 668 if (unlikely(port_status & err_mask)) { 669 pdc_error_intr(ap, qc, port_status, err_mask); 670 return 1; 671 } 672 673 switch (qc->tf.protocol) { 674 case ATA_PROT_DMA: 675 case ATA_PROT_NODATA: 676 case ATA_PROT_ATAPI_DMA: 677 case ATA_PROT_ATAPI_NODATA: 678 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 679 ata_qc_complete(qc); 680 handled = 1; 681 break; 682 683 default: 684 ap->stats.idle_irq++; 685 break; 686 } 687 688 return handled; 689 } 690 691 static void pdc_irq_clear(struct ata_port *ap) 692 { 693 struct ata_host *host = ap->host; 694 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 695 696 readl(mmio + PDC_INT_SEQMASK); 697 } 698 699 static inline int pdc_is_sataii_tx4(unsigned long flags) 700 { 701 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; 702 return (flags & mask) == mask; 703 } 704 705 static inline unsigned int pdc_port_no_to_ata_no(unsigned int port_no, int is_sataii_tx4) 706 { 707 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; 708 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; 709 } 710 711 static irqreturn_t pdc_interrupt (int irq, void *dev_instance) 712 { 713 struct ata_host *host = dev_instance; 714 struct ata_port *ap; 715 u32 mask = 0; 716 unsigned int i, tmp; 717 unsigned int handled = 0; 718 void __iomem *mmio_base; 719 720 VPRINTK("ENTER\n"); 721 722 if (!host || !host->iomap[PDC_MMIO_BAR]) { 723 VPRINTK("QUICK EXIT\n"); 724 return IRQ_NONE; 725 } 726 727 mmio_base = host->iomap[PDC_MMIO_BAR]; 728 729 /* reading should also clear interrupts */ 730 mask = readl(mmio_base + PDC_INT_SEQMASK); 731 732 if (mask == 0xffffffff) { 733 VPRINTK("QUICK EXIT 2\n"); 734 return IRQ_NONE; 735 } 736 737 spin_lock(&host->lock); 738 739 mask &= 0xffff; /* only 16 tags possible */ 740 if (!mask) { 741 VPRINTK("QUICK EXIT 3\n"); 742 goto done_irq; 743 } 744 745 writel(mask, mmio_base + PDC_INT_SEQMASK); 746 747 for (i = 0; i < host->n_ports; i++) { 748 VPRINTK("port %u\n", i); 749 ap = host->ports[i]; 750 tmp = mask & (1 << (i + 1)); 751 if (tmp && ap && 752 !(ap->flags & ATA_FLAG_DISABLED)) { 753 struct ata_queued_cmd *qc; 754 755 qc = ata_qc_from_tag(ap, ap->active_tag); 756 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 757 handled += pdc_host_intr(ap, qc); 758 } 759 } 760 761 VPRINTK("EXIT\n"); 762 763 done_irq: 764 spin_unlock(&host->lock); 765 return IRQ_RETVAL(handled); 766 } 767 768 static inline void pdc_packet_start(struct ata_queued_cmd *qc) 769 { 770 struct ata_port *ap = qc->ap; 771 struct pdc_port_priv *pp = ap->private_data; 772 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; 773 unsigned int port_no = ap->port_no; 774 u8 seq = (u8) (port_no + 1); 775 776 VPRINTK("ENTER, ap %p\n", ap); 777 778 writel(0x00000001, mmio + (seq * 4)); 779 readl(mmio + (seq * 4)); /* flush */ 780 781 pp->pkt[2] = seq; 782 wmb(); /* flush PRD, pkt writes */ 783 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 784 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ 785 } 786 787 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) 788 { 789 switch (qc->tf.protocol) { 790 case ATA_PROT_ATAPI_NODATA: 791 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 792 break; 793 /*FALLTHROUGH*/ 794 case ATA_PROT_NODATA: 795 if (qc->tf.flags & ATA_TFLAG_POLLING) 796 break; 797 /*FALLTHROUGH*/ 798 case ATA_PROT_ATAPI_DMA: 799 case ATA_PROT_DMA: 800 pdc_packet_start(qc); 801 return 0; 802 803 default: 804 break; 805 } 806 807 return ata_qc_issue_prot(qc); 808 } 809 810 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 811 { 812 WARN_ON (tf->protocol == ATA_PROT_DMA || 813 tf->protocol == ATA_PROT_ATAPI_DMA); 814 ata_tf_load(ap, tf); 815 } 816 817 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 818 { 819 WARN_ON (tf->protocol == ATA_PROT_DMA || 820 tf->protocol == ATA_PROT_ATAPI_DMA); 821 ata_exec_command(ap, tf); 822 } 823 824 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) 825 { 826 u8 *scsicmd = qc->scsicmd->cmnd; 827 int pio = 1; /* atapi dma off by default */ 828 829 /* Whitelist commands that may use DMA. */ 830 switch (scsicmd[0]) { 831 case WRITE_12: 832 case WRITE_10: 833 case WRITE_6: 834 case READ_12: 835 case READ_10: 836 case READ_6: 837 case 0xad: /* READ_DVD_STRUCTURE */ 838 case 0xbe: /* READ_CD */ 839 pio = 0; 840 } 841 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ 842 if (scsicmd[0] == WRITE_10) { 843 unsigned int lba; 844 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; 845 if (lba >= 0xFFFF4FA2) 846 pio = 1; 847 } 848 return pio; 849 } 850 851 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) 852 { 853 /* First generation chips cannot use ATAPI DMA on SATA ports */ 854 return 1; 855 } 856 857 static void pdc_ata_setup_port(struct ata_port *ap, 858 void __iomem *base, void __iomem *scr_addr) 859 { 860 ap->ioaddr.cmd_addr = base; 861 ap->ioaddr.data_addr = base; 862 ap->ioaddr.feature_addr = 863 ap->ioaddr.error_addr = base + 0x4; 864 ap->ioaddr.nsect_addr = base + 0x8; 865 ap->ioaddr.lbal_addr = base + 0xc; 866 ap->ioaddr.lbam_addr = base + 0x10; 867 ap->ioaddr.lbah_addr = base + 0x14; 868 ap->ioaddr.device_addr = base + 0x18; 869 ap->ioaddr.command_addr = 870 ap->ioaddr.status_addr = base + 0x1c; 871 ap->ioaddr.altstatus_addr = 872 ap->ioaddr.ctl_addr = base + 0x38; 873 ap->ioaddr.scr_addr = scr_addr; 874 } 875 876 static void pdc_host_init(struct ata_host *host) 877 { 878 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 879 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 880 int hotplug_offset; 881 u32 tmp; 882 883 if (is_gen2) 884 hotplug_offset = PDC2_SATA_PLUG_CSR; 885 else 886 hotplug_offset = PDC_SATA_PLUG_CSR; 887 888 /* 889 * Except for the hotplug stuff, this is voodoo from the 890 * Promise driver. Label this entire section 891 * "TODO: figure out why we do this" 892 */ 893 894 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 895 tmp = readl(mmio + PDC_FLASH_CTL); 896 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 897 if (!is_gen2) 898 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 899 writel(tmp, mmio + PDC_FLASH_CTL); 900 901 /* clear plug/unplug flags for all ports */ 902 tmp = readl(mmio + hotplug_offset); 903 writel(tmp | 0xff, mmio + hotplug_offset); 904 905 /* mask plug/unplug ints */ 906 tmp = readl(mmio + hotplug_offset); 907 writel(tmp | 0xff0000, mmio + hotplug_offset); 908 909 /* don't initialise TBG or SLEW on 2nd generation chips */ 910 if (is_gen2) 911 return; 912 913 /* reduce TBG clock to 133 Mhz. */ 914 tmp = readl(mmio + PDC_TBG_MODE); 915 tmp &= ~0x30000; /* clear bit 17, 16*/ 916 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 917 writel(tmp, mmio + PDC_TBG_MODE); 918 919 readl(mmio + PDC_TBG_MODE); /* flush */ 920 msleep(10); 921 922 /* adjust slew rate control register. */ 923 tmp = readl(mmio + PDC_SLEW_CTL); 924 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 925 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 926 writel(tmp, mmio + PDC_SLEW_CTL); 927 } 928 929 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 930 { 931 static int printed_version; 932 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 933 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 934 struct ata_host *host; 935 void __iomem *base; 936 int n_ports, i, rc; 937 int is_sataii_tx4; 938 939 if (!printed_version++) 940 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 941 942 /* enable and acquire resources */ 943 rc = pcim_enable_device(pdev); 944 if (rc) 945 return rc; 946 947 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 948 if (rc == -EBUSY) 949 pcim_pin_device(pdev); 950 if (rc) 951 return rc; 952 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 953 954 /* determine port configuration and setup host */ 955 n_ports = 2; 956 if (pi->flags & PDC_FLAG_4_PORTS) 957 n_ports = 4; 958 for (i = 0; i < n_ports; i++) 959 ppi[i] = pi; 960 961 if (pi->flags & PDC_FLAG_SATA_PATA) { 962 u8 tmp = readb(base + PDC_FLASH_CTL+1); 963 if (!(tmp & 0x80)) 964 ppi[n_ports++] = pi + 1; 965 } 966 967 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 968 if (!host) { 969 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); 970 return -ENOMEM; 971 } 972 host->iomap = pcim_iomap_table(pdev); 973 974 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); 975 for (i = 0; i < host->n_ports; i++) { 976 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 977 pdc_ata_setup_port(host->ports[i], 978 base + 0x200 + ata_no * 0x80, 979 base + 0x400 + ata_no * 0x100); 980 } 981 982 /* initialize adapter */ 983 pdc_host_init(host); 984 985 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 986 if (rc) 987 return rc; 988 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 989 if (rc) 990 return rc; 991 992 /* start host, request IRQ and attach */ 993 pci_set_master(pdev); 994 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, 995 &pdc_ata_sht); 996 } 997 998 static int __init pdc_ata_init(void) 999 { 1000 return pci_register_driver(&pdc_ata_pci_driver); 1001 } 1002 1003 static void __exit pdc_ata_exit(void) 1004 { 1005 pci_unregister_driver(&pdc_ata_pci_driver); 1006 } 1007 1008 MODULE_AUTHOR("Jeff Garzik"); 1009 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); 1010 MODULE_LICENSE("GPL"); 1011 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); 1012 MODULE_VERSION(DRV_VERSION); 1013 1014 module_init(pdc_ata_init); 1015 module_exit(pdc_ata_exit); 1016