1 /* 2 * sata_promise.c - Promise SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Mikael Pettersson <mikpe@it.uu.se> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2003-2004 Red Hat, Inc. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * 27 * libata documentation is available via 'make {ps|pdf}docs', 28 * as Documentation/DocBook/libata.* 29 * 30 * Hardware information only available under NDA. 31 * 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/init.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/device.h> 42 #include <scsi/scsi.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include "sata_promise.h" 47 48 #define DRV_NAME "sata_promise" 49 #define DRV_VERSION "2.12" 50 51 enum { 52 PDC_MAX_PORTS = 4, 53 PDC_MMIO_BAR = 3, 54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ 55 56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */ 57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 58 PDC_FLASH_CTL = 0x44, /* Flash control register */ 59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 60 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 61 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 62 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 63 64 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */ 65 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 66 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 67 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 68 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ 69 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ 70 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ 71 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 72 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 73 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 74 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 75 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 76 77 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */ 78 PDC_PHYMODE4 = 0x14, 79 80 /* PDC_GLOBAL_CTL bit definitions */ 81 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 82 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ 83 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ 84 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ 85 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ 86 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ 87 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ 88 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ 89 PDC_DRIVE_ERR = (1 << 21), /* drive error */ 90 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ 91 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ 92 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, 93 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | 94 PDC2_ATA_DMA_CNT_ERR, 95 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | 96 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | 97 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | 98 PDC1_ERR_MASK | PDC2_ERR_MASK, 99 100 board_2037x = 0, /* FastTrak S150 TX2plus */ 101 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ 102 board_20319 = 2, /* FastTrak S150 TX4 */ 103 board_20619 = 3, /* FastTrak TX4000 */ 104 board_2057x = 4, /* SATAII150 Tx2plus */ 105 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ 106 board_40518 = 6, /* SATAII150 Tx4 */ 107 108 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 109 110 /* Sequence counter control registers bit definitions */ 111 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ 112 113 /* Feature register values */ 114 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ 115 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ 116 117 /* Device/Head register values */ 118 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ 119 120 /* PDC_CTLSTAT bit definitions */ 121 PDC_DMA_ENABLE = (1 << 7), 122 PDC_IRQ_DISABLE = (1 << 10), 123 PDC_RESET = (1 << 11), /* HDMA reset */ 124 125 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | 126 ATA_FLAG_MMIO | 127 ATA_FLAG_PIO_POLLING, 128 129 /* ap->flags bits */ 130 PDC_FLAG_GEN_II = (1 << 24), 131 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ 132 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ 133 }; 134 135 struct pdc_port_priv { 136 u8 *pkt; 137 dma_addr_t pkt_dma; 138 }; 139 140 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); 141 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); 142 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 143 static int pdc_common_port_start(struct ata_port *ap); 144 static int pdc_sata_port_start(struct ata_port *ap); 145 static void pdc_qc_prep(struct ata_queued_cmd *qc); 146 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 147 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 148 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 149 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); 150 static void pdc_irq_clear(struct ata_port *ap); 151 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc); 152 static void pdc_freeze(struct ata_port *ap); 153 static void pdc_sata_freeze(struct ata_port *ap); 154 static void pdc_thaw(struct ata_port *ap); 155 static void pdc_sata_thaw(struct ata_port *ap); 156 static void pdc_error_handler(struct ata_port *ap); 157 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 158 static int pdc_pata_cable_detect(struct ata_port *ap); 159 static int pdc_sata_cable_detect(struct ata_port *ap); 160 161 static struct scsi_host_template pdc_ata_sht = { 162 ATA_BASE_SHT(DRV_NAME), 163 .sg_tablesize = PDC_MAX_PRD, 164 .dma_boundary = ATA_DMA_BOUNDARY, 165 }; 166 167 static const struct ata_port_operations pdc_common_ops = { 168 .inherits = &ata_sff_port_ops, 169 170 .sff_tf_load = pdc_tf_load_mmio, 171 .sff_exec_command = pdc_exec_command_mmio, 172 .check_atapi_dma = pdc_check_atapi_dma, 173 .qc_prep = pdc_qc_prep, 174 .qc_issue = pdc_qc_issue, 175 .sff_irq_clear = pdc_irq_clear, 176 177 .post_internal_cmd = pdc_post_internal_cmd, 178 .error_handler = pdc_error_handler, 179 }; 180 181 static struct ata_port_operations pdc_sata_ops = { 182 .inherits = &pdc_common_ops, 183 .cable_detect = pdc_sata_cable_detect, 184 .freeze = pdc_sata_freeze, 185 .thaw = pdc_sata_thaw, 186 .scr_read = pdc_sata_scr_read, 187 .scr_write = pdc_sata_scr_write, 188 .port_start = pdc_sata_port_start, 189 }; 190 191 /* First-generation chips need a more restrictive ->check_atapi_dma op */ 192 static struct ata_port_operations pdc_old_sata_ops = { 193 .inherits = &pdc_sata_ops, 194 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 195 }; 196 197 static struct ata_port_operations pdc_pata_ops = { 198 .inherits = &pdc_common_ops, 199 .cable_detect = pdc_pata_cable_detect, 200 .freeze = pdc_freeze, 201 .thaw = pdc_thaw, 202 .port_start = pdc_common_port_start, 203 }; 204 205 static const struct ata_port_info pdc_port_info[] = { 206 [board_2037x] = 207 { 208 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 209 PDC_FLAG_SATA_PATA, 210 .pio_mask = 0x1f, /* pio0-4 */ 211 .mwdma_mask = 0x07, /* mwdma0-2 */ 212 .udma_mask = ATA_UDMA6, 213 .port_ops = &pdc_old_sata_ops, 214 }, 215 216 [board_2037x_pata] = 217 { 218 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 219 .pio_mask = 0x1f, /* pio0-4 */ 220 .mwdma_mask = 0x07, /* mwdma0-2 */ 221 .udma_mask = ATA_UDMA6, 222 .port_ops = &pdc_pata_ops, 223 }, 224 225 [board_20319] = 226 { 227 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 228 PDC_FLAG_4_PORTS, 229 .pio_mask = 0x1f, /* pio0-4 */ 230 .mwdma_mask = 0x07, /* mwdma0-2 */ 231 .udma_mask = ATA_UDMA6, 232 .port_ops = &pdc_old_sata_ops, 233 }, 234 235 [board_20619] = 236 { 237 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 238 PDC_FLAG_4_PORTS, 239 .pio_mask = 0x1f, /* pio0-4 */ 240 .mwdma_mask = 0x07, /* mwdma0-2 */ 241 .udma_mask = ATA_UDMA6, 242 .port_ops = &pdc_pata_ops, 243 }, 244 245 [board_2057x] = 246 { 247 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 248 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, 249 .pio_mask = 0x1f, /* pio0-4 */ 250 .mwdma_mask = 0x07, /* mwdma0-2 */ 251 .udma_mask = ATA_UDMA6, 252 .port_ops = &pdc_sata_ops, 253 }, 254 255 [board_2057x_pata] = 256 { 257 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 258 PDC_FLAG_GEN_II, 259 .pio_mask = 0x1f, /* pio0-4 */ 260 .mwdma_mask = 0x07, /* mwdma0-2 */ 261 .udma_mask = ATA_UDMA6, 262 .port_ops = &pdc_pata_ops, 263 }, 264 265 [board_40518] = 266 { 267 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 268 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, 269 .pio_mask = 0x1f, /* pio0-4 */ 270 .mwdma_mask = 0x07, /* mwdma0-2 */ 271 .udma_mask = ATA_UDMA6, 272 .port_ops = &pdc_sata_ops, 273 }, 274 }; 275 276 static const struct pci_device_id pdc_ata_pci_tbl[] = { 277 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 278 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 279 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 280 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 281 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, 282 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, 283 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 284 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, 285 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, 286 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 287 288 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 289 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 290 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, 291 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, 292 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, 293 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 294 295 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 296 297 { } /* terminate list */ 298 }; 299 300 static struct pci_driver pdc_ata_pci_driver = { 301 .name = DRV_NAME, 302 .id_table = pdc_ata_pci_tbl, 303 .probe = pdc_ata_init_one, 304 .remove = ata_pci_remove_one, 305 }; 306 307 static int pdc_common_port_start(struct ata_port *ap) 308 { 309 struct device *dev = ap->host->dev; 310 struct pdc_port_priv *pp; 311 int rc; 312 313 rc = ata_port_start(ap); 314 if (rc) 315 return rc; 316 317 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 318 if (!pp) 319 return -ENOMEM; 320 321 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 322 if (!pp->pkt) 323 return -ENOMEM; 324 325 ap->private_data = pp; 326 327 return 0; 328 } 329 330 static int pdc_sata_port_start(struct ata_port *ap) 331 { 332 int rc; 333 334 rc = pdc_common_port_start(ap); 335 if (rc) 336 return rc; 337 338 /* fix up PHYMODE4 align timing */ 339 if (ap->flags & PDC_FLAG_GEN_II) { 340 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 341 unsigned int tmp; 342 343 tmp = readl(sata_mmio + PDC_PHYMODE4); 344 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 345 writel(tmp, sata_mmio + PDC_PHYMODE4); 346 } 347 348 return 0; 349 } 350 351 static void pdc_reset_port(struct ata_port *ap) 352 { 353 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 354 unsigned int i; 355 u32 tmp; 356 357 for (i = 11; i > 0; i--) { 358 tmp = readl(ata_ctlstat_mmio); 359 if (tmp & PDC_RESET) 360 break; 361 362 udelay(100); 363 364 tmp |= PDC_RESET; 365 writel(tmp, ata_ctlstat_mmio); 366 } 367 368 tmp &= ~PDC_RESET; 369 writel(tmp, ata_ctlstat_mmio); 370 readl(ata_ctlstat_mmio); /* flush */ 371 } 372 373 static int pdc_pata_cable_detect(struct ata_port *ap) 374 { 375 u8 tmp; 376 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 377 378 tmp = readb(ata_mmio + PDC_CTLSTAT + 3); 379 if (tmp & 0x01) 380 return ATA_CBL_PATA40; 381 return ATA_CBL_PATA80; 382 } 383 384 static int pdc_sata_cable_detect(struct ata_port *ap) 385 { 386 return ATA_CBL_SATA; 387 } 388 389 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) 390 { 391 if (sc_reg > SCR_CONTROL) 392 return -EINVAL; 393 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 394 return 0; 395 } 396 397 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) 398 { 399 if (sc_reg > SCR_CONTROL) 400 return -EINVAL; 401 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 402 return 0; 403 } 404 405 static void pdc_atapi_pkt(struct ata_queued_cmd *qc) 406 { 407 struct ata_port *ap = qc->ap; 408 dma_addr_t sg_table = ap->prd_dma; 409 unsigned int cdb_len = qc->dev->cdb_len; 410 u8 *cdb = qc->cdb; 411 struct pdc_port_priv *pp = ap->private_data; 412 u8 *buf = pp->pkt; 413 __le32 *buf32 = (__le32 *) buf; 414 unsigned int dev_sel, feature; 415 416 /* set control bits (byte 0), zero delay seq id (byte 3), 417 * and seq id (byte 2) 418 */ 419 switch (qc->tf.protocol) { 420 case ATAPI_PROT_DMA: 421 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 422 buf32[0] = cpu_to_le32(PDC_PKT_READ); 423 else 424 buf32[0] = 0; 425 break; 426 case ATAPI_PROT_NODATA: 427 buf32[0] = cpu_to_le32(PDC_PKT_NODATA); 428 break; 429 default: 430 BUG(); 431 break; 432 } 433 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 434 buf32[2] = 0; /* no next-packet */ 435 436 /* select drive */ 437 if (sata_scr_valid(&ap->link)) 438 dev_sel = PDC_DEVICE_SATA; 439 else 440 dev_sel = qc->tf.device; 441 442 buf[12] = (1 << 5) | ATA_REG_DEVICE; 443 buf[13] = dev_sel; 444 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; 445 buf[15] = dev_sel; /* once more, waiting for BSY to clear */ 446 447 buf[16] = (1 << 5) | ATA_REG_NSECT; 448 buf[17] = qc->tf.nsect; 449 buf[18] = (1 << 5) | ATA_REG_LBAL; 450 buf[19] = qc->tf.lbal; 451 452 /* set feature and byte counter registers */ 453 if (qc->tf.protocol != ATAPI_PROT_DMA) 454 feature = PDC_FEATURE_ATAPI_PIO; 455 else 456 feature = PDC_FEATURE_ATAPI_DMA; 457 458 buf[20] = (1 << 5) | ATA_REG_FEATURE; 459 buf[21] = feature; 460 buf[22] = (1 << 5) | ATA_REG_BYTEL; 461 buf[23] = qc->tf.lbam; 462 buf[24] = (1 << 5) | ATA_REG_BYTEH; 463 buf[25] = qc->tf.lbah; 464 465 /* send ATAPI packet command 0xA0 */ 466 buf[26] = (1 << 5) | ATA_REG_CMD; 467 buf[27] = qc->tf.command; 468 469 /* select drive and check DRQ */ 470 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; 471 buf[29] = dev_sel; 472 473 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 474 BUG_ON(cdb_len & ~0x1E); 475 476 /* append the CDB as the final part */ 477 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 478 memcpy(buf+31, cdb, cdb_len); 479 } 480 481 /** 482 * pdc_fill_sg - Fill PCI IDE PRD table 483 * @qc: Metadata associated with taskfile to be transferred 484 * 485 * Fill PCI IDE PRD (scatter-gather) table with segments 486 * associated with the current disk command. 487 * Make sure hardware does not choke on it. 488 * 489 * LOCKING: 490 * spin_lock_irqsave(host lock) 491 * 492 */ 493 static void pdc_fill_sg(struct ata_queued_cmd *qc) 494 { 495 struct ata_port *ap = qc->ap; 496 struct scatterlist *sg; 497 const u32 SG_COUNT_ASIC_BUG = 41*4; 498 unsigned int si, idx; 499 u32 len; 500 501 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 502 return; 503 504 idx = 0; 505 for_each_sg(qc->sg, sg, qc->n_elem, si) { 506 u32 addr, offset; 507 u32 sg_len; 508 509 /* determine if physical DMA addr spans 64K boundary. 510 * Note h/w doesn't support 64-bit, so we unconditionally 511 * truncate dma_addr_t to u32. 512 */ 513 addr = (u32) sg_dma_address(sg); 514 sg_len = sg_dma_len(sg); 515 516 while (sg_len) { 517 offset = addr & 0xffff; 518 len = sg_len; 519 if ((offset + sg_len) > 0x10000) 520 len = 0x10000 - offset; 521 522 ap->prd[idx].addr = cpu_to_le32(addr); 523 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff); 524 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 525 526 idx++; 527 sg_len -= len; 528 addr += len; 529 } 530 } 531 532 len = le32_to_cpu(ap->prd[idx - 1].flags_len); 533 534 if (len > SG_COUNT_ASIC_BUG) { 535 u32 addr; 536 537 VPRINTK("Splitting last PRD.\n"); 538 539 addr = le32_to_cpu(ap->prd[idx - 1].addr); 540 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG); 541 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG); 542 543 addr = addr + len - SG_COUNT_ASIC_BUG; 544 len = SG_COUNT_ASIC_BUG; 545 ap->prd[idx].addr = cpu_to_le32(addr); 546 ap->prd[idx].flags_len = cpu_to_le32(len); 547 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 548 549 idx++; 550 } 551 552 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 553 } 554 555 static void pdc_qc_prep(struct ata_queued_cmd *qc) 556 { 557 struct pdc_port_priv *pp = qc->ap->private_data; 558 unsigned int i; 559 560 VPRINTK("ENTER\n"); 561 562 switch (qc->tf.protocol) { 563 case ATA_PROT_DMA: 564 pdc_fill_sg(qc); 565 /*FALLTHROUGH*/ 566 case ATA_PROT_NODATA: 567 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, 568 qc->dev->devno, pp->pkt); 569 if (qc->tf.flags & ATA_TFLAG_LBA48) 570 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 571 else 572 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 573 pdc_pkt_footer(&qc->tf, pp->pkt, i); 574 break; 575 case ATAPI_PROT_PIO: 576 pdc_fill_sg(qc); 577 break; 578 case ATAPI_PROT_DMA: 579 pdc_fill_sg(qc); 580 /*FALLTHROUGH*/ 581 case ATAPI_PROT_NODATA: 582 pdc_atapi_pkt(qc); 583 break; 584 default: 585 break; 586 } 587 } 588 589 static int pdc_is_sataii_tx4(unsigned long flags) 590 { 591 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; 592 return (flags & mask) == mask; 593 } 594 595 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, 596 int is_sataii_tx4) 597 { 598 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; 599 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; 600 } 601 602 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap) 603 { 604 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2; 605 } 606 607 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap) 608 { 609 const struct ata_host *host = ap->host; 610 unsigned int nr_ports = pdc_sata_nr_ports(ap); 611 unsigned int i; 612 613 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i) 614 ; 615 BUG_ON(i >= nr_ports); 616 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags)); 617 } 618 619 static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap) 620 { 621 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR; 622 } 623 624 static void pdc_freeze(struct ata_port *ap) 625 { 626 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 627 u32 tmp; 628 629 tmp = readl(ata_mmio + PDC_CTLSTAT); 630 tmp |= PDC_IRQ_DISABLE; 631 tmp &= ~PDC_DMA_ENABLE; 632 writel(tmp, ata_mmio + PDC_CTLSTAT); 633 readl(ata_mmio + PDC_CTLSTAT); /* flush */ 634 } 635 636 static void pdc_sata_freeze(struct ata_port *ap) 637 { 638 struct ata_host *host = ap->host; 639 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 640 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap); 641 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 642 u32 hotplug_status; 643 644 /* Disable hotplug events on this port. 645 * 646 * Locking: 647 * 1) hotplug register accesses must be serialised via host->lock 648 * 2) ap->lock == &ap->host->lock 649 * 3) ->freeze() and ->thaw() are called with ap->lock held 650 */ 651 hotplug_status = readl(host_mmio + hotplug_offset); 652 hotplug_status |= 0x11 << (ata_no + 16); 653 writel(hotplug_status, host_mmio + hotplug_offset); 654 readl(host_mmio + hotplug_offset); /* flush */ 655 656 pdc_freeze(ap); 657 } 658 659 static void pdc_thaw(struct ata_port *ap) 660 { 661 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 662 u32 tmp; 663 664 /* clear IRQ */ 665 readl(ata_mmio + PDC_COMMAND); 666 667 /* turn IRQ back on */ 668 tmp = readl(ata_mmio + PDC_CTLSTAT); 669 tmp &= ~PDC_IRQ_DISABLE; 670 writel(tmp, ata_mmio + PDC_CTLSTAT); 671 readl(ata_mmio + PDC_CTLSTAT); /* flush */ 672 } 673 674 static void pdc_sata_thaw(struct ata_port *ap) 675 { 676 struct ata_host *host = ap->host; 677 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 678 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap); 679 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 680 u32 hotplug_status; 681 682 pdc_thaw(ap); 683 684 /* Enable hotplug events on this port. 685 * Locking: see pdc_sata_freeze(). 686 */ 687 hotplug_status = readl(host_mmio + hotplug_offset); 688 hotplug_status |= 0x11 << ata_no; 689 hotplug_status &= ~(0x11 << (ata_no + 16)); 690 writel(hotplug_status, host_mmio + hotplug_offset); 691 readl(host_mmio + hotplug_offset); /* flush */ 692 } 693 694 static void pdc_error_handler(struct ata_port *ap) 695 { 696 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 697 pdc_reset_port(ap); 698 699 ata_std_error_handler(ap); 700 } 701 702 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 703 { 704 struct ata_port *ap = qc->ap; 705 706 /* make DMA engine forget about the failed command */ 707 if (qc->flags & ATA_QCFLAG_FAILED) 708 pdc_reset_port(ap); 709 } 710 711 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, 712 u32 port_status, u32 err_mask) 713 { 714 struct ata_eh_info *ehi = &ap->link.eh_info; 715 unsigned int ac_err_mask = 0; 716 717 ata_ehi_clear_desc(ehi); 718 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); 719 port_status &= err_mask; 720 721 if (port_status & PDC_DRIVE_ERR) 722 ac_err_mask |= AC_ERR_DEV; 723 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) 724 ac_err_mask |= AC_ERR_HSM; 725 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) 726 ac_err_mask |= AC_ERR_ATA_BUS; 727 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR 728 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) 729 ac_err_mask |= AC_ERR_HOST_BUS; 730 731 if (sata_scr_valid(&ap->link)) { 732 u32 serror; 733 734 pdc_sata_scr_read(ap, SCR_ERROR, &serror); 735 ehi->serror |= serror; 736 } 737 738 qc->err_mask |= ac_err_mask; 739 740 pdc_reset_port(ap); 741 742 ata_port_abort(ap); 743 } 744 745 static unsigned int pdc_host_intr(struct ata_port *ap, 746 struct ata_queued_cmd *qc) 747 { 748 unsigned int handled = 0; 749 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 750 u32 port_status, err_mask; 751 752 err_mask = PDC_ERR_MASK; 753 if (ap->flags & PDC_FLAG_GEN_II) 754 err_mask &= ~PDC1_ERR_MASK; 755 else 756 err_mask &= ~PDC2_ERR_MASK; 757 port_status = readl(ata_mmio + PDC_GLOBAL_CTL); 758 if (unlikely(port_status & err_mask)) { 759 pdc_error_intr(ap, qc, port_status, err_mask); 760 return 1; 761 } 762 763 switch (qc->tf.protocol) { 764 case ATA_PROT_DMA: 765 case ATA_PROT_NODATA: 766 case ATAPI_PROT_DMA: 767 case ATAPI_PROT_NODATA: 768 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 769 ata_qc_complete(qc); 770 handled = 1; 771 break; 772 default: 773 ap->stats.idle_irq++; 774 break; 775 } 776 777 return handled; 778 } 779 780 static void pdc_irq_clear(struct ata_port *ap) 781 { 782 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 783 784 readl(ata_mmio + PDC_COMMAND); 785 } 786 787 static irqreturn_t pdc_interrupt(int irq, void *dev_instance) 788 { 789 struct ata_host *host = dev_instance; 790 struct ata_port *ap; 791 u32 mask = 0; 792 unsigned int i, tmp; 793 unsigned int handled = 0; 794 void __iomem *host_mmio; 795 unsigned int hotplug_offset, ata_no; 796 u32 hotplug_status; 797 int is_sataii_tx4; 798 799 VPRINTK("ENTER\n"); 800 801 if (!host || !host->iomap[PDC_MMIO_BAR]) { 802 VPRINTK("QUICK EXIT\n"); 803 return IRQ_NONE; 804 } 805 806 host_mmio = host->iomap[PDC_MMIO_BAR]; 807 808 spin_lock(&host->lock); 809 810 /* read and clear hotplug flags for all ports */ 811 if (host->ports[0]->flags & PDC_FLAG_GEN_II) 812 hotplug_offset = PDC2_SATA_PLUG_CSR; 813 else 814 hotplug_offset = PDC_SATA_PLUG_CSR; 815 hotplug_status = readl(host_mmio + hotplug_offset); 816 if (hotplug_status & 0xff) 817 writel(hotplug_status | 0xff, host_mmio + hotplug_offset); 818 hotplug_status &= 0xff; /* clear uninteresting bits */ 819 820 /* reading should also clear interrupts */ 821 mask = readl(host_mmio + PDC_INT_SEQMASK); 822 823 if (mask == 0xffffffff && hotplug_status == 0) { 824 VPRINTK("QUICK EXIT 2\n"); 825 goto done_irq; 826 } 827 828 mask &= 0xffff; /* only 16 SEQIDs possible */ 829 if (mask == 0 && hotplug_status == 0) { 830 VPRINTK("QUICK EXIT 3\n"); 831 goto done_irq; 832 } 833 834 writel(mask, host_mmio + PDC_INT_SEQMASK); 835 836 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); 837 838 for (i = 0; i < host->n_ports; i++) { 839 VPRINTK("port %u\n", i); 840 ap = host->ports[i]; 841 842 /* check for a plug or unplug event */ 843 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 844 tmp = hotplug_status & (0x11 << ata_no); 845 if (tmp && ap && 846 !(ap->flags & ATA_FLAG_DISABLED)) { 847 struct ata_eh_info *ehi = &ap->link.eh_info; 848 ata_ehi_clear_desc(ehi); 849 ata_ehi_hotplugged(ehi); 850 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); 851 ata_port_freeze(ap); 852 ++handled; 853 continue; 854 } 855 856 /* check for a packet interrupt */ 857 tmp = mask & (1 << (i + 1)); 858 if (tmp && ap && 859 !(ap->flags & ATA_FLAG_DISABLED)) { 860 struct ata_queued_cmd *qc; 861 862 qc = ata_qc_from_tag(ap, ap->link.active_tag); 863 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 864 handled += pdc_host_intr(ap, qc); 865 } 866 } 867 868 VPRINTK("EXIT\n"); 869 870 done_irq: 871 spin_unlock(&host->lock); 872 return IRQ_RETVAL(handled); 873 } 874 875 static void pdc_packet_start(struct ata_queued_cmd *qc) 876 { 877 struct ata_port *ap = qc->ap; 878 struct pdc_port_priv *pp = ap->private_data; 879 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; 880 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 881 unsigned int port_no = ap->port_no; 882 u8 seq = (u8) (port_no + 1); 883 884 VPRINTK("ENTER, ap %p\n", ap); 885 886 writel(0x00000001, host_mmio + (seq * 4)); 887 readl(host_mmio + (seq * 4)); /* flush */ 888 889 pp->pkt[2] = seq; 890 wmb(); /* flush PRD, pkt writes */ 891 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT); 892 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */ 893 } 894 895 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) 896 { 897 switch (qc->tf.protocol) { 898 case ATAPI_PROT_NODATA: 899 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 900 break; 901 /*FALLTHROUGH*/ 902 case ATA_PROT_NODATA: 903 if (qc->tf.flags & ATA_TFLAG_POLLING) 904 break; 905 /*FALLTHROUGH*/ 906 case ATAPI_PROT_DMA: 907 case ATA_PROT_DMA: 908 pdc_packet_start(qc); 909 return 0; 910 default: 911 break; 912 } 913 return ata_sff_qc_issue(qc); 914 } 915 916 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 917 { 918 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 919 ata_sff_tf_load(ap, tf); 920 } 921 922 static void pdc_exec_command_mmio(struct ata_port *ap, 923 const struct ata_taskfile *tf) 924 { 925 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 926 ata_sff_exec_command(ap, tf); 927 } 928 929 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) 930 { 931 u8 *scsicmd = qc->scsicmd->cmnd; 932 int pio = 1; /* atapi dma off by default */ 933 934 /* Whitelist commands that may use DMA. */ 935 switch (scsicmd[0]) { 936 case WRITE_12: 937 case WRITE_10: 938 case WRITE_6: 939 case READ_12: 940 case READ_10: 941 case READ_6: 942 case 0xad: /* READ_DVD_STRUCTURE */ 943 case 0xbe: /* READ_CD */ 944 pio = 0; 945 } 946 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ 947 if (scsicmd[0] == WRITE_10) { 948 unsigned int lba = 949 (scsicmd[2] << 24) | 950 (scsicmd[3] << 16) | 951 (scsicmd[4] << 8) | 952 scsicmd[5]; 953 if (lba >= 0xFFFF4FA2) 954 pio = 1; 955 } 956 return pio; 957 } 958 959 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) 960 { 961 /* First generation chips cannot use ATAPI DMA on SATA ports */ 962 return 1; 963 } 964 965 static void pdc_ata_setup_port(struct ata_port *ap, 966 void __iomem *base, void __iomem *scr_addr) 967 { 968 ap->ioaddr.cmd_addr = base; 969 ap->ioaddr.data_addr = base; 970 ap->ioaddr.feature_addr = 971 ap->ioaddr.error_addr = base + 0x4; 972 ap->ioaddr.nsect_addr = base + 0x8; 973 ap->ioaddr.lbal_addr = base + 0xc; 974 ap->ioaddr.lbam_addr = base + 0x10; 975 ap->ioaddr.lbah_addr = base + 0x14; 976 ap->ioaddr.device_addr = base + 0x18; 977 ap->ioaddr.command_addr = 978 ap->ioaddr.status_addr = base + 0x1c; 979 ap->ioaddr.altstatus_addr = 980 ap->ioaddr.ctl_addr = base + 0x38; 981 ap->ioaddr.scr_addr = scr_addr; 982 } 983 984 static void pdc_host_init(struct ata_host *host) 985 { 986 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 987 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 988 int hotplug_offset; 989 u32 tmp; 990 991 if (is_gen2) 992 hotplug_offset = PDC2_SATA_PLUG_CSR; 993 else 994 hotplug_offset = PDC_SATA_PLUG_CSR; 995 996 /* 997 * Except for the hotplug stuff, this is voodoo from the 998 * Promise driver. Label this entire section 999 * "TODO: figure out why we do this" 1000 */ 1001 1002 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 1003 tmp = readl(host_mmio + PDC_FLASH_CTL); 1004 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 1005 if (!is_gen2) 1006 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 1007 writel(tmp, host_mmio + PDC_FLASH_CTL); 1008 1009 /* clear plug/unplug flags for all ports */ 1010 tmp = readl(host_mmio + hotplug_offset); 1011 writel(tmp | 0xff, host_mmio + hotplug_offset); 1012 1013 /* unmask plug/unplug ints */ 1014 tmp = readl(host_mmio + hotplug_offset); 1015 writel(tmp & ~0xff0000, host_mmio + hotplug_offset); 1016 1017 /* don't initialise TBG or SLEW on 2nd generation chips */ 1018 if (is_gen2) 1019 return; 1020 1021 /* reduce TBG clock to 133 Mhz. */ 1022 tmp = readl(host_mmio + PDC_TBG_MODE); 1023 tmp &= ~0x30000; /* clear bit 17, 16*/ 1024 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 1025 writel(tmp, host_mmio + PDC_TBG_MODE); 1026 1027 readl(host_mmio + PDC_TBG_MODE); /* flush */ 1028 msleep(10); 1029 1030 /* adjust slew rate control register. */ 1031 tmp = readl(host_mmio + PDC_SLEW_CTL); 1032 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 1033 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 1034 writel(tmp, host_mmio + PDC_SLEW_CTL); 1035 } 1036 1037 static int pdc_ata_init_one(struct pci_dev *pdev, 1038 const struct pci_device_id *ent) 1039 { 1040 static int printed_version; 1041 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 1042 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 1043 struct ata_host *host; 1044 void __iomem *host_mmio; 1045 int n_ports, i, rc; 1046 int is_sataii_tx4; 1047 1048 if (!printed_version++) 1049 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1050 1051 /* enable and acquire resources */ 1052 rc = pcim_enable_device(pdev); 1053 if (rc) 1054 return rc; 1055 1056 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 1057 if (rc == -EBUSY) 1058 pcim_pin_device(pdev); 1059 if (rc) 1060 return rc; 1061 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 1062 1063 /* determine port configuration and setup host */ 1064 n_ports = 2; 1065 if (pi->flags & PDC_FLAG_4_PORTS) 1066 n_ports = 4; 1067 for (i = 0; i < n_ports; i++) 1068 ppi[i] = pi; 1069 1070 if (pi->flags & PDC_FLAG_SATA_PATA) { 1071 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1); 1072 if (!(tmp & 0x80)) 1073 ppi[n_ports++] = pi + 1; 1074 } 1075 1076 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1077 if (!host) { 1078 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); 1079 return -ENOMEM; 1080 } 1081 host->iomap = pcim_iomap_table(pdev); 1082 1083 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); 1084 for (i = 0; i < host->n_ports; i++) { 1085 struct ata_port *ap = host->ports[i]; 1086 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 1087 unsigned int ata_offset = 0x200 + ata_no * 0x80; 1088 unsigned int scr_offset = 0x400 + ata_no * 0x100; 1089 1090 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset); 1091 1092 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 1093 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata"); 1094 } 1095 1096 /* initialize adapter */ 1097 pdc_host_init(host); 1098 1099 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 1100 if (rc) 1101 return rc; 1102 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 1103 if (rc) 1104 return rc; 1105 1106 /* start host, request IRQ and attach */ 1107 pci_set_master(pdev); 1108 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, 1109 &pdc_ata_sht); 1110 } 1111 1112 static int __init pdc_ata_init(void) 1113 { 1114 return pci_register_driver(&pdc_ata_pci_driver); 1115 } 1116 1117 static void __exit pdc_ata_exit(void) 1118 { 1119 pci_unregister_driver(&pdc_ata_pci_driver); 1120 } 1121 1122 MODULE_AUTHOR("Jeff Garzik"); 1123 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); 1124 MODULE_LICENSE("GPL"); 1125 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); 1126 MODULE_VERSION(DRV_VERSION); 1127 1128 module_init(pdc_ata_init); 1129 module_exit(pdc_ata_exit); 1130