1 /* 2 * sata_mv.c - Marvell SATA support 3 * 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved. 5 * Copyright 2005: EMC Corporation, all rights reserved. 6 * Copyright 2005 Red Hat, Inc. All rights reserved. 7 * 8 * Originally written by Brett Russ. 9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 10 * 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; version 2 of the License. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 /* 29 * sata_mv TODO list: 30 * 31 * --> Develop a low-power-consumption strategy, and implement it. 32 * 33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 34 * 35 * --> [Experiment, Marvell value added] Is it possible to use target 36 * mode to cross-connect two Linux boxes with Marvell cards? If so, 37 * creating LibATA target mode support would be very interesting. 38 * 39 * Target mode, for those without docs, is the ability to directly 40 * connect two SATA ports. 41 */ 42 43 /* 44 * 80x1-B2 errata PCI#11: 45 * 46 * Users of the 6041/6081 Rev.B2 chips (current is C0) 47 * should be careful to insert those cards only onto PCI-X bus #0, 48 * and only in device slots 0..7, not higher. The chips may not 49 * work correctly otherwise (note: this is a pretty rare condition). 50 */ 51 52 #include <linux/kernel.h> 53 #include <linux/module.h> 54 #include <linux/pci.h> 55 #include <linux/init.h> 56 #include <linux/blkdev.h> 57 #include <linux/delay.h> 58 #include <linux/interrupt.h> 59 #include <linux/dmapool.h> 60 #include <linux/dma-mapping.h> 61 #include <linux/device.h> 62 #include <linux/platform_device.h> 63 #include <linux/ata_platform.h> 64 #include <linux/mbus.h> 65 #include <linux/bitops.h> 66 #include <scsi/scsi_host.h> 67 #include <scsi/scsi_cmnd.h> 68 #include <scsi/scsi_device.h> 69 #include <linux/libata.h> 70 71 #define DRV_NAME "sata_mv" 72 #define DRV_VERSION "1.28" 73 74 /* 75 * module options 76 */ 77 78 static int msi; 79 #ifdef CONFIG_PCI 80 module_param(msi, int, S_IRUGO); 81 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 82 #endif 83 84 static int irq_coalescing_io_count; 85 module_param(irq_coalescing_io_count, int, S_IRUGO); 86 MODULE_PARM_DESC(irq_coalescing_io_count, 87 "IRQ coalescing I/O count threshold (0..255)"); 88 89 static int irq_coalescing_usecs; 90 module_param(irq_coalescing_usecs, int, S_IRUGO); 91 MODULE_PARM_DESC(irq_coalescing_usecs, 92 "IRQ coalescing time threshold in usecs"); 93 94 enum { 95 /* BAR's are enumerated in terms of pci_resource_start() terms */ 96 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 97 MV_IO_BAR = 2, /* offset 0x18: IO space */ 98 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 99 100 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 101 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 102 103 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 104 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 105 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 106 MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 107 108 MV_PCI_REG_BASE = 0, 109 110 /* 111 * Per-chip ("all ports") interrupt coalescing feature. 112 * This is only for GEN_II / GEN_IIE hardware. 113 * 114 * Coalescing defers the interrupt until either the IO_THRESHOLD 115 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 116 */ 117 COAL_REG_BASE = 0x18000, 118 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 119 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 120 121 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 122 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 123 124 /* 125 * Registers for the (unused here) transaction coalescing feature: 126 */ 127 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 128 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 129 130 SATAHC0_REG_BASE = 0x20000, 131 FLASH_CTL = 0x1046c, 132 GPIO_PORT_CTL = 0x104f0, 133 RESET_CFG = 0x180d8, 134 135 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 136 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 137 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 138 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 139 140 MV_MAX_Q_DEPTH = 32, 141 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 142 143 /* CRQB needs alignment on a 1KB boundary. Size == 1KB 144 * CRPB needs alignment on a 256B boundary. Size == 256B 145 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 146 */ 147 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 148 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 149 MV_MAX_SG_CT = 256, 150 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 151 152 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 153 MV_PORT_HC_SHIFT = 2, 154 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 155 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 156 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 157 158 /* Host Flags */ 159 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 160 161 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 162 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, 163 164 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 165 166 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 167 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 168 169 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 170 171 CRQB_FLAG_READ = (1 << 0), 172 CRQB_TAG_SHIFT = 1, 173 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 174 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 175 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 176 CRQB_CMD_ADDR_SHIFT = 8, 177 CRQB_CMD_CS = (0x2 << 11), 178 CRQB_CMD_LAST = (1 << 15), 179 180 CRPB_FLAG_STATUS_SHIFT = 8, 181 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 182 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 183 184 EPRD_FLAG_END_OF_TBL = (1 << 31), 185 186 /* PCI interface registers */ 187 188 MV_PCI_COMMAND = 0xc00, 189 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 190 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 191 192 PCI_MAIN_CMD_STS = 0xd30, 193 STOP_PCI_MASTER = (1 << 2), 194 PCI_MASTER_EMPTY = (1 << 3), 195 GLOB_SFT_RST = (1 << 4), 196 197 MV_PCI_MODE = 0xd00, 198 MV_PCI_MODE_MASK = 0x30, 199 200 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 201 MV_PCI_DISC_TIMER = 0xd04, 202 MV_PCI_MSI_TRIGGER = 0xc38, 203 MV_PCI_SERR_MASK = 0xc28, 204 MV_PCI_XBAR_TMOUT = 0x1d04, 205 MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 206 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 207 MV_PCI_ERR_ATTRIBUTE = 0x1d48, 208 MV_PCI_ERR_COMMAND = 0x1d50, 209 210 PCI_IRQ_CAUSE = 0x1d58, 211 PCI_IRQ_MASK = 0x1d5c, 212 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 213 214 PCIE_IRQ_CAUSE = 0x1900, 215 PCIE_IRQ_MASK = 0x1910, 216 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 217 218 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 219 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 220 PCI_HC_MAIN_IRQ_MASK = 0x1d64, 221 SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 222 SOC_HC_MAIN_IRQ_MASK = 0x20024, 223 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 224 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 225 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 226 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 227 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 228 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 229 PCI_ERR = (1 << 18), 230 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 231 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 232 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 233 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 234 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 235 GPIO_INT = (1 << 22), 236 SELF_INT = (1 << 23), 237 TWSI_INT = (1 << 24), 238 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 239 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 240 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 241 242 /* SATAHC registers */ 243 HC_CFG = 0x00, 244 245 HC_IRQ_CAUSE = 0x14, 246 DMA_IRQ = (1 << 0), /* shift by port # */ 247 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 248 DEV_IRQ = (1 << 8), /* shift by port # */ 249 250 /* 251 * Per-HC (Host-Controller) interrupt coalescing feature. 252 * This is present on all chip generations. 253 * 254 * Coalescing defers the interrupt until either the IO_THRESHOLD 255 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 256 */ 257 HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 258 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 259 260 SOC_LED_CTRL = 0x2c, 261 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 262 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 263 /* with dev activity LED */ 264 265 /* Shadow block registers */ 266 SHD_BLK = 0x100, 267 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 268 269 /* SATA registers */ 270 SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 271 SATA_ACTIVE = 0x350, 272 FIS_IRQ_CAUSE = 0x364, 273 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 274 275 LTMODE = 0x30c, /* requires read-after-write */ 276 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 277 278 PHY_MODE2 = 0x330, 279 PHY_MODE3 = 0x310, 280 281 PHY_MODE4 = 0x314, /* requires read-after-write */ 282 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 283 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 284 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 285 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 286 287 SATA_IFCTL = 0x344, 288 SATA_TESTCTL = 0x348, 289 SATA_IFSTAT = 0x34c, 290 VENDOR_UNIQUE_FIS = 0x35c, 291 292 FISCFG = 0x360, 293 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 294 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 295 296 MV5_PHY_MODE = 0x74, 297 MV5_LTMODE = 0x30, 298 MV5_PHY_CTL = 0x0C, 299 SATA_IFCFG = 0x050, 300 301 MV_M2_PREAMP_MASK = 0x7e0, 302 303 /* Port registers */ 304 EDMA_CFG = 0, 305 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 306 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 307 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 308 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 309 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 310 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 311 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 312 313 EDMA_ERR_IRQ_CAUSE = 0x8, 314 EDMA_ERR_IRQ_MASK = 0xc, 315 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 316 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 317 EDMA_ERR_DEV = (1 << 2), /* device error */ 318 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 319 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 320 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 321 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 322 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 323 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 324 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 325 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 326 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 327 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 328 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 329 330 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 331 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 332 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 333 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 334 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 335 336 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 337 338 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 339 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 340 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 341 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 342 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 343 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 344 345 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 346 347 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 348 EDMA_ERR_OVERRUN_5 = (1 << 5), 349 EDMA_ERR_UNDERRUN_5 = (1 << 6), 350 351 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 352 EDMA_ERR_LNK_CTRL_RX_1 | 353 EDMA_ERR_LNK_CTRL_RX_3 | 354 EDMA_ERR_LNK_CTRL_TX, 355 356 EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 357 EDMA_ERR_PRD_PAR | 358 EDMA_ERR_DEV_DCON | 359 EDMA_ERR_DEV_CON | 360 EDMA_ERR_SERR | 361 EDMA_ERR_SELF_DIS | 362 EDMA_ERR_CRQB_PAR | 363 EDMA_ERR_CRPB_PAR | 364 EDMA_ERR_INTRL_PAR | 365 EDMA_ERR_IORDY | 366 EDMA_ERR_LNK_CTRL_RX_2 | 367 EDMA_ERR_LNK_DATA_RX | 368 EDMA_ERR_LNK_DATA_TX | 369 EDMA_ERR_TRANS_PROTO, 370 371 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 372 EDMA_ERR_PRD_PAR | 373 EDMA_ERR_DEV_DCON | 374 EDMA_ERR_DEV_CON | 375 EDMA_ERR_OVERRUN_5 | 376 EDMA_ERR_UNDERRUN_5 | 377 EDMA_ERR_SELF_DIS_5 | 378 EDMA_ERR_CRQB_PAR | 379 EDMA_ERR_CRPB_PAR | 380 EDMA_ERR_INTRL_PAR | 381 EDMA_ERR_IORDY, 382 383 EDMA_REQ_Q_BASE_HI = 0x10, 384 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 385 386 EDMA_REQ_Q_OUT_PTR = 0x18, 387 EDMA_REQ_Q_PTR_SHIFT = 5, 388 389 EDMA_RSP_Q_BASE_HI = 0x1c, 390 EDMA_RSP_Q_IN_PTR = 0x20, 391 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 392 EDMA_RSP_Q_PTR_SHIFT = 3, 393 394 EDMA_CMD = 0x28, /* EDMA command register */ 395 EDMA_EN = (1 << 0), /* enable EDMA */ 396 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 397 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 398 399 EDMA_STATUS = 0x30, /* EDMA engine status */ 400 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 401 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 402 403 EDMA_IORDY_TMOUT = 0x34, 404 EDMA_ARB_CFG = 0x38, 405 406 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 407 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 408 409 BMDMA_CMD = 0x224, /* bmdma command register */ 410 BMDMA_STATUS = 0x228, /* bmdma status register */ 411 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 412 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 413 414 /* Host private flags (hp_flags) */ 415 MV_HP_FLAG_MSI = (1 << 0), 416 MV_HP_ERRATA_50XXB0 = (1 << 1), 417 MV_HP_ERRATA_50XXB2 = (1 << 2), 418 MV_HP_ERRATA_60X1B2 = (1 << 3), 419 MV_HP_ERRATA_60X1C0 = (1 << 4), 420 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 421 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 422 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 423 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 424 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 425 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 426 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 427 428 /* Port private flags (pp_flags) */ 429 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 430 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 431 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 432 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 433 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 434 }; 435 436 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 437 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 438 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 439 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 440 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 441 442 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 443 #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 444 445 enum { 446 /* DMA boundary 0xffff is required by the s/g splitting 447 * we need on /length/ in mv_fill-sg(). 448 */ 449 MV_DMA_BOUNDARY = 0xffffU, 450 451 /* mask of register bits containing lower 32 bits 452 * of EDMA request queue DMA address 453 */ 454 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 455 456 /* ditto, for response queue */ 457 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 458 }; 459 460 enum chip_type { 461 chip_504x, 462 chip_508x, 463 chip_5080, 464 chip_604x, 465 chip_608x, 466 chip_6042, 467 chip_7042, 468 chip_soc, 469 }; 470 471 /* Command ReQuest Block: 32B */ 472 struct mv_crqb { 473 __le32 sg_addr; 474 __le32 sg_addr_hi; 475 __le16 ctrl_flags; 476 __le16 ata_cmd[11]; 477 }; 478 479 struct mv_crqb_iie { 480 __le32 addr; 481 __le32 addr_hi; 482 __le32 flags; 483 __le32 len; 484 __le32 ata_cmd[4]; 485 }; 486 487 /* Command ResPonse Block: 8B */ 488 struct mv_crpb { 489 __le16 id; 490 __le16 flags; 491 __le32 tmstmp; 492 }; 493 494 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 495 struct mv_sg { 496 __le32 addr; 497 __le32 flags_size; 498 __le32 addr_hi; 499 __le32 reserved; 500 }; 501 502 /* 503 * We keep a local cache of a few frequently accessed port 504 * registers here, to avoid having to read them (very slow) 505 * when switching between EDMA and non-EDMA modes. 506 */ 507 struct mv_cached_regs { 508 u32 fiscfg; 509 u32 ltmode; 510 u32 haltcond; 511 u32 unknown_rsvd; 512 }; 513 514 struct mv_port_priv { 515 struct mv_crqb *crqb; 516 dma_addr_t crqb_dma; 517 struct mv_crpb *crpb; 518 dma_addr_t crpb_dma; 519 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 520 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 521 522 unsigned int req_idx; 523 unsigned int resp_idx; 524 525 u32 pp_flags; 526 struct mv_cached_regs cached; 527 unsigned int delayed_eh_pmp_map; 528 }; 529 530 struct mv_port_signal { 531 u32 amps; 532 u32 pre; 533 }; 534 535 struct mv_host_priv { 536 u32 hp_flags; 537 u32 main_irq_mask; 538 struct mv_port_signal signal[8]; 539 const struct mv_hw_ops *ops; 540 int n_ports; 541 void __iomem *base; 542 void __iomem *main_irq_cause_addr; 543 void __iomem *main_irq_mask_addr; 544 u32 irq_cause_offset; 545 u32 irq_mask_offset; 546 u32 unmask_all_irqs; 547 /* 548 * These consistent DMA memory pools give us guaranteed 549 * alignment for hardware-accessed data structures, 550 * and less memory waste in accomplishing the alignment. 551 */ 552 struct dma_pool *crqb_pool; 553 struct dma_pool *crpb_pool; 554 struct dma_pool *sg_tbl_pool; 555 }; 556 557 struct mv_hw_ops { 558 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 559 unsigned int port); 560 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 561 void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 562 void __iomem *mmio); 563 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 564 unsigned int n_hc); 565 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 566 void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 567 }; 568 569 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 570 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 571 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 572 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 573 static int mv_port_start(struct ata_port *ap); 574 static void mv_port_stop(struct ata_port *ap); 575 static int mv_qc_defer(struct ata_queued_cmd *qc); 576 static void mv_qc_prep(struct ata_queued_cmd *qc); 577 static void mv_qc_prep_iie(struct ata_queued_cmd *qc); 578 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 579 static int mv_hardreset(struct ata_link *link, unsigned int *class, 580 unsigned long deadline); 581 static void mv_eh_freeze(struct ata_port *ap); 582 static void mv_eh_thaw(struct ata_port *ap); 583 static void mv6_dev_config(struct ata_device *dev); 584 585 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 586 unsigned int port); 587 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 588 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 589 void __iomem *mmio); 590 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 591 unsigned int n_hc); 592 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 593 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 594 595 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 596 unsigned int port); 597 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 598 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 599 void __iomem *mmio); 600 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 601 unsigned int n_hc); 602 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 603 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 604 void __iomem *mmio); 605 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 606 void __iomem *mmio); 607 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 608 void __iomem *mmio, unsigned int n_hc); 609 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 610 void __iomem *mmio); 611 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 612 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 613 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 614 unsigned int port_no); 615 static int mv_stop_edma(struct ata_port *ap); 616 static int mv_stop_edma_engine(void __iomem *port_mmio); 617 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 618 619 static void mv_pmp_select(struct ata_port *ap, int pmp); 620 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 621 unsigned long deadline); 622 static int mv_softreset(struct ata_link *link, unsigned int *class, 623 unsigned long deadline); 624 static void mv_pmp_error_handler(struct ata_port *ap); 625 static void mv_process_crpb_entries(struct ata_port *ap, 626 struct mv_port_priv *pp); 627 628 static void mv_sff_irq_clear(struct ata_port *ap); 629 static int mv_check_atapi_dma(struct ata_queued_cmd *qc); 630 static void mv_bmdma_setup(struct ata_queued_cmd *qc); 631 static void mv_bmdma_start(struct ata_queued_cmd *qc); 632 static void mv_bmdma_stop(struct ata_queued_cmd *qc); 633 static u8 mv_bmdma_status(struct ata_port *ap); 634 static u8 mv_sff_check_status(struct ata_port *ap); 635 636 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 637 * because we have to allow room for worst case splitting of 638 * PRDs for 64K boundaries in mv_fill_sg(). 639 */ 640 static struct scsi_host_template mv5_sht = { 641 ATA_BASE_SHT(DRV_NAME), 642 .sg_tablesize = MV_MAX_SG_CT / 2, 643 .dma_boundary = MV_DMA_BOUNDARY, 644 }; 645 646 static struct scsi_host_template mv6_sht = { 647 ATA_NCQ_SHT(DRV_NAME), 648 .can_queue = MV_MAX_Q_DEPTH - 1, 649 .sg_tablesize = MV_MAX_SG_CT / 2, 650 .dma_boundary = MV_DMA_BOUNDARY, 651 }; 652 653 static struct ata_port_operations mv5_ops = { 654 .inherits = &ata_sff_port_ops, 655 656 .lost_interrupt = ATA_OP_NULL, 657 658 .qc_defer = mv_qc_defer, 659 .qc_prep = mv_qc_prep, 660 .qc_issue = mv_qc_issue, 661 662 .freeze = mv_eh_freeze, 663 .thaw = mv_eh_thaw, 664 .hardreset = mv_hardreset, 665 .error_handler = ata_std_error_handler, /* avoid SFF EH */ 666 .post_internal_cmd = ATA_OP_NULL, 667 668 .scr_read = mv5_scr_read, 669 .scr_write = mv5_scr_write, 670 671 .port_start = mv_port_start, 672 .port_stop = mv_port_stop, 673 }; 674 675 static struct ata_port_operations mv6_ops = { 676 .inherits = &mv5_ops, 677 .dev_config = mv6_dev_config, 678 .scr_read = mv_scr_read, 679 .scr_write = mv_scr_write, 680 681 .pmp_hardreset = mv_pmp_hardreset, 682 .pmp_softreset = mv_softreset, 683 .softreset = mv_softreset, 684 .error_handler = mv_pmp_error_handler, 685 686 .sff_check_status = mv_sff_check_status, 687 .sff_irq_clear = mv_sff_irq_clear, 688 .check_atapi_dma = mv_check_atapi_dma, 689 .bmdma_setup = mv_bmdma_setup, 690 .bmdma_start = mv_bmdma_start, 691 .bmdma_stop = mv_bmdma_stop, 692 .bmdma_status = mv_bmdma_status, 693 }; 694 695 static struct ata_port_operations mv_iie_ops = { 696 .inherits = &mv6_ops, 697 .dev_config = ATA_OP_NULL, 698 .qc_prep = mv_qc_prep_iie, 699 }; 700 701 static const struct ata_port_info mv_port_info[] = { 702 { /* chip_504x */ 703 .flags = MV_GEN_I_FLAGS, 704 .pio_mask = ATA_PIO4, 705 .udma_mask = ATA_UDMA6, 706 .port_ops = &mv5_ops, 707 }, 708 { /* chip_508x */ 709 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 710 .pio_mask = ATA_PIO4, 711 .udma_mask = ATA_UDMA6, 712 .port_ops = &mv5_ops, 713 }, 714 { /* chip_5080 */ 715 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 716 .pio_mask = ATA_PIO4, 717 .udma_mask = ATA_UDMA6, 718 .port_ops = &mv5_ops, 719 }, 720 { /* chip_604x */ 721 .flags = MV_GEN_II_FLAGS, 722 .pio_mask = ATA_PIO4, 723 .udma_mask = ATA_UDMA6, 724 .port_ops = &mv6_ops, 725 }, 726 { /* chip_608x */ 727 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 728 .pio_mask = ATA_PIO4, 729 .udma_mask = ATA_UDMA6, 730 .port_ops = &mv6_ops, 731 }, 732 { /* chip_6042 */ 733 .flags = MV_GEN_IIE_FLAGS, 734 .pio_mask = ATA_PIO4, 735 .udma_mask = ATA_UDMA6, 736 .port_ops = &mv_iie_ops, 737 }, 738 { /* chip_7042 */ 739 .flags = MV_GEN_IIE_FLAGS, 740 .pio_mask = ATA_PIO4, 741 .udma_mask = ATA_UDMA6, 742 .port_ops = &mv_iie_ops, 743 }, 744 { /* chip_soc */ 745 .flags = MV_GEN_IIE_FLAGS, 746 .pio_mask = ATA_PIO4, 747 .udma_mask = ATA_UDMA6, 748 .port_ops = &mv_iie_ops, 749 }, 750 }; 751 752 static const struct pci_device_id mv_pci_tbl[] = { 753 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 754 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 755 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 756 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 757 /* RocketRAID 1720/174x have different identifiers */ 758 { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 759 { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 760 { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 761 762 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 763 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 764 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 765 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 766 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 767 768 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 769 770 /* Adaptec 1430SA */ 771 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 772 773 /* Marvell 7042 support */ 774 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 775 776 /* Highpoint RocketRAID PCIe series */ 777 { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 778 { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 779 780 { } /* terminate list */ 781 }; 782 783 static const struct mv_hw_ops mv5xxx_ops = { 784 .phy_errata = mv5_phy_errata, 785 .enable_leds = mv5_enable_leds, 786 .read_preamp = mv5_read_preamp, 787 .reset_hc = mv5_reset_hc, 788 .reset_flash = mv5_reset_flash, 789 .reset_bus = mv5_reset_bus, 790 }; 791 792 static const struct mv_hw_ops mv6xxx_ops = { 793 .phy_errata = mv6_phy_errata, 794 .enable_leds = mv6_enable_leds, 795 .read_preamp = mv6_read_preamp, 796 .reset_hc = mv6_reset_hc, 797 .reset_flash = mv6_reset_flash, 798 .reset_bus = mv_reset_pci_bus, 799 }; 800 801 static const struct mv_hw_ops mv_soc_ops = { 802 .phy_errata = mv6_phy_errata, 803 .enable_leds = mv_soc_enable_leds, 804 .read_preamp = mv_soc_read_preamp, 805 .reset_hc = mv_soc_reset_hc, 806 .reset_flash = mv_soc_reset_flash, 807 .reset_bus = mv_soc_reset_bus, 808 }; 809 810 /* 811 * Functions 812 */ 813 814 static inline void writelfl(unsigned long data, void __iomem *addr) 815 { 816 writel(data, addr); 817 (void) readl(addr); /* flush to avoid PCI posted write */ 818 } 819 820 static inline unsigned int mv_hc_from_port(unsigned int port) 821 { 822 return port >> MV_PORT_HC_SHIFT; 823 } 824 825 static inline unsigned int mv_hardport_from_port(unsigned int port) 826 { 827 return port & MV_PORT_MASK; 828 } 829 830 /* 831 * Consolidate some rather tricky bit shift calculations. 832 * This is hot-path stuff, so not a function. 833 * Simple code, with two return values, so macro rather than inline. 834 * 835 * port is the sole input, in range 0..7. 836 * shift is one output, for use with main_irq_cause / main_irq_mask registers. 837 * hardport is the other output, in range 0..3. 838 * 839 * Note that port and hardport may be the same variable in some cases. 840 */ 841 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 842 { \ 843 shift = mv_hc_from_port(port) * HC_SHIFT; \ 844 hardport = mv_hardport_from_port(port); \ 845 shift += hardport * 2; \ 846 } 847 848 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 849 { 850 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 851 } 852 853 static inline void __iomem *mv_hc_base_from_port(void __iomem *base, 854 unsigned int port) 855 { 856 return mv_hc_base(base, mv_hc_from_port(port)); 857 } 858 859 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 860 { 861 return mv_hc_base_from_port(base, port) + 862 MV_SATAHC_ARBTR_REG_SZ + 863 (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 864 } 865 866 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 867 { 868 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 869 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 870 871 return hc_mmio + ofs; 872 } 873 874 static inline void __iomem *mv_host_base(struct ata_host *host) 875 { 876 struct mv_host_priv *hpriv = host->private_data; 877 return hpriv->base; 878 } 879 880 static inline void __iomem *mv_ap_base(struct ata_port *ap) 881 { 882 return mv_port_base(mv_host_base(ap->host), ap->port_no); 883 } 884 885 static inline int mv_get_hc_count(unsigned long port_flags) 886 { 887 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 888 } 889 890 /** 891 * mv_save_cached_regs - (re-)initialize cached port registers 892 * @ap: the port whose registers we are caching 893 * 894 * Initialize the local cache of port registers, 895 * so that reading them over and over again can 896 * be avoided on the hotter paths of this driver. 897 * This saves a few microseconds each time we switch 898 * to/from EDMA mode to perform (eg.) a drive cache flush. 899 */ 900 static void mv_save_cached_regs(struct ata_port *ap) 901 { 902 void __iomem *port_mmio = mv_ap_base(ap); 903 struct mv_port_priv *pp = ap->private_data; 904 905 pp->cached.fiscfg = readl(port_mmio + FISCFG); 906 pp->cached.ltmode = readl(port_mmio + LTMODE); 907 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 908 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 909 } 910 911 /** 912 * mv_write_cached_reg - write to a cached port register 913 * @addr: hardware address of the register 914 * @old: pointer to cached value of the register 915 * @new: new value for the register 916 * 917 * Write a new value to a cached register, 918 * but only if the value is different from before. 919 */ 920 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 921 { 922 if (new != *old) { 923 unsigned long laddr; 924 *old = new; 925 /* 926 * Workaround for 88SX60x1-B2 FEr SATA#13: 927 * Read-after-write is needed to prevent generating 64-bit 928 * write cycles on the PCI bus for SATA interface registers 929 * at offsets ending in 0x4 or 0xc. 930 * 931 * Looks like a lot of fuss, but it avoids an unnecessary 932 * +1 usec read-after-write delay for unaffected registers. 933 */ 934 laddr = (long)addr & 0xffff; 935 if (laddr >= 0x300 && laddr <= 0x33c) { 936 laddr &= 0x000f; 937 if (laddr == 0x4 || laddr == 0xc) { 938 writelfl(new, addr); /* read after write */ 939 return; 940 } 941 } 942 writel(new, addr); /* unaffected by the errata */ 943 } 944 } 945 946 static void mv_set_edma_ptrs(void __iomem *port_mmio, 947 struct mv_host_priv *hpriv, 948 struct mv_port_priv *pp) 949 { 950 u32 index; 951 952 /* 953 * initialize request queue 954 */ 955 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 956 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 957 958 WARN_ON(pp->crqb_dma & 0x3ff); 959 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 960 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 961 port_mmio + EDMA_REQ_Q_IN_PTR); 962 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 963 964 /* 965 * initialize response queue 966 */ 967 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 968 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 969 970 WARN_ON(pp->crpb_dma & 0xff); 971 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 972 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 973 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 974 port_mmio + EDMA_RSP_Q_OUT_PTR); 975 } 976 977 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 978 { 979 /* 980 * When writing to the main_irq_mask in hardware, 981 * we must ensure exclusivity between the interrupt coalescing bits 982 * and the corresponding individual port DONE_IRQ bits. 983 * 984 * Note that this register is really an "IRQ enable" register, 985 * not an "IRQ mask" register as Marvell's naming might suggest. 986 */ 987 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 988 mask &= ~DONE_IRQ_0_3; 989 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 990 mask &= ~DONE_IRQ_4_7; 991 writelfl(mask, hpriv->main_irq_mask_addr); 992 } 993 994 static void mv_set_main_irq_mask(struct ata_host *host, 995 u32 disable_bits, u32 enable_bits) 996 { 997 struct mv_host_priv *hpriv = host->private_data; 998 u32 old_mask, new_mask; 999 1000 old_mask = hpriv->main_irq_mask; 1001 new_mask = (old_mask & ~disable_bits) | enable_bits; 1002 if (new_mask != old_mask) { 1003 hpriv->main_irq_mask = new_mask; 1004 mv_write_main_irq_mask(new_mask, hpriv); 1005 } 1006 } 1007 1008 static void mv_enable_port_irqs(struct ata_port *ap, 1009 unsigned int port_bits) 1010 { 1011 unsigned int shift, hardport, port = ap->port_no; 1012 u32 disable_bits, enable_bits; 1013 1014 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1015 1016 disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1017 enable_bits = port_bits << shift; 1018 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1019 } 1020 1021 static void mv_clear_and_enable_port_irqs(struct ata_port *ap, 1022 void __iomem *port_mmio, 1023 unsigned int port_irqs) 1024 { 1025 struct mv_host_priv *hpriv = ap->host->private_data; 1026 int hardport = mv_hardport_from_port(ap->port_no); 1027 void __iomem *hc_mmio = mv_hc_base_from_port( 1028 mv_host_base(ap->host), ap->port_no); 1029 u32 hc_irq_cause; 1030 1031 /* clear EDMA event indicators, if any */ 1032 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 1033 1034 /* clear pending irq events */ 1035 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1036 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 1037 1038 /* clear FIS IRQ Cause */ 1039 if (IS_GEN_IIE(hpriv)) 1040 writelfl(0, port_mmio + FIS_IRQ_CAUSE); 1041 1042 mv_enable_port_irqs(ap, port_irqs); 1043 } 1044 1045 static void mv_set_irq_coalescing(struct ata_host *host, 1046 unsigned int count, unsigned int usecs) 1047 { 1048 struct mv_host_priv *hpriv = host->private_data; 1049 void __iomem *mmio = hpriv->base, *hc_mmio; 1050 u32 coal_enable = 0; 1051 unsigned long flags; 1052 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 1053 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 1054 ALL_PORTS_COAL_DONE; 1055 1056 /* Disable IRQ coalescing if either threshold is zero */ 1057 if (!usecs || !count) { 1058 clks = count = 0; 1059 } else { 1060 /* Respect maximum limits of the hardware */ 1061 clks = usecs * COAL_CLOCKS_PER_USEC; 1062 if (clks > MAX_COAL_TIME_THRESHOLD) 1063 clks = MAX_COAL_TIME_THRESHOLD; 1064 if (count > MAX_COAL_IO_COUNT) 1065 count = MAX_COAL_IO_COUNT; 1066 } 1067 1068 spin_lock_irqsave(&host->lock, flags); 1069 mv_set_main_irq_mask(host, coal_disable, 0); 1070 1071 if (is_dual_hc && !IS_GEN_I(hpriv)) { 1072 /* 1073 * GEN_II/GEN_IIE with dual host controllers: 1074 * one set of global thresholds for the entire chip. 1075 */ 1076 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1077 writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 1078 /* clear leftover coal IRQ bit */ 1079 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 1080 if (count) 1081 coal_enable = ALL_PORTS_COAL_DONE; 1082 clks = count = 0; /* force clearing of regular regs below */ 1083 } 1084 1085 /* 1086 * All chips: independent thresholds for each HC on the chip. 1087 */ 1088 hc_mmio = mv_hc_base_from_port(mmio, 0); 1089 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1090 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1091 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 1092 if (count) 1093 coal_enable |= PORTS_0_3_COAL_DONE; 1094 if (is_dual_hc) { 1095 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1096 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1097 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1098 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 1099 if (count) 1100 coal_enable |= PORTS_4_7_COAL_DONE; 1101 } 1102 1103 mv_set_main_irq_mask(host, 0, coal_enable); 1104 spin_unlock_irqrestore(&host->lock, flags); 1105 } 1106 1107 /** 1108 * mv_start_edma - Enable eDMA engine 1109 * @base: port base address 1110 * @pp: port private data 1111 * 1112 * Verify the local cache of the eDMA state is accurate with a 1113 * WARN_ON. 1114 * 1115 * LOCKING: 1116 * Inherited from caller. 1117 */ 1118 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1119 struct mv_port_priv *pp, u8 protocol) 1120 { 1121 int want_ncq = (protocol == ATA_PROT_NCQ); 1122 1123 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1124 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1125 if (want_ncq != using_ncq) 1126 mv_stop_edma(ap); 1127 } 1128 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 1129 struct mv_host_priv *hpriv = ap->host->private_data; 1130 1131 mv_edma_cfg(ap, want_ncq, 1); 1132 1133 mv_set_edma_ptrs(port_mmio, hpriv, pp); 1134 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1135 1136 writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1137 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1138 } 1139 } 1140 1141 static void mv_wait_for_edma_empty_idle(struct ata_port *ap) 1142 { 1143 void __iomem *port_mmio = mv_ap_base(ap); 1144 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 1145 const int per_loop = 5, timeout = (15 * 1000 / per_loop); 1146 int i; 1147 1148 /* 1149 * Wait for the EDMA engine to finish transactions in progress. 1150 * No idea what a good "timeout" value might be, but measurements 1151 * indicate that it often requires hundreds of microseconds 1152 * with two drives in-use. So we use the 15msec value above 1153 * as a rough guess at what even more drives might require. 1154 */ 1155 for (i = 0; i < timeout; ++i) { 1156 u32 edma_stat = readl(port_mmio + EDMA_STATUS); 1157 if ((edma_stat & empty_idle) == empty_idle) 1158 break; 1159 udelay(per_loop); 1160 } 1161 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 1162 } 1163 1164 /** 1165 * mv_stop_edma_engine - Disable eDMA engine 1166 * @port_mmio: io base address 1167 * 1168 * LOCKING: 1169 * Inherited from caller. 1170 */ 1171 static int mv_stop_edma_engine(void __iomem *port_mmio) 1172 { 1173 int i; 1174 1175 /* Disable eDMA. The disable bit auto clears. */ 1176 writelfl(EDMA_DS, port_mmio + EDMA_CMD); 1177 1178 /* Wait for the chip to confirm eDMA is off. */ 1179 for (i = 10000; i > 0; i--) { 1180 u32 reg = readl(port_mmio + EDMA_CMD); 1181 if (!(reg & EDMA_EN)) 1182 return 0; 1183 udelay(10); 1184 } 1185 return -EIO; 1186 } 1187 1188 static int mv_stop_edma(struct ata_port *ap) 1189 { 1190 void __iomem *port_mmio = mv_ap_base(ap); 1191 struct mv_port_priv *pp = ap->private_data; 1192 int err = 0; 1193 1194 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1195 return 0; 1196 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1197 mv_wait_for_edma_empty_idle(ap); 1198 if (mv_stop_edma_engine(port_mmio)) { 1199 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 1200 err = -EIO; 1201 } 1202 mv_edma_cfg(ap, 0, 0); 1203 return err; 1204 } 1205 1206 #ifdef ATA_DEBUG 1207 static void mv_dump_mem(void __iomem *start, unsigned bytes) 1208 { 1209 int b, w; 1210 for (b = 0; b < bytes; ) { 1211 DPRINTK("%p: ", start + b); 1212 for (w = 0; b < bytes && w < 4; w++) { 1213 printk("%08x ", readl(start + b)); 1214 b += sizeof(u32); 1215 } 1216 printk("\n"); 1217 } 1218 } 1219 #endif 1220 1221 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 1222 { 1223 #ifdef ATA_DEBUG 1224 int b, w; 1225 u32 dw; 1226 for (b = 0; b < bytes; ) { 1227 DPRINTK("%02x: ", b); 1228 for (w = 0; b < bytes && w < 4; w++) { 1229 (void) pci_read_config_dword(pdev, b, &dw); 1230 printk("%08x ", dw); 1231 b += sizeof(u32); 1232 } 1233 printk("\n"); 1234 } 1235 #endif 1236 } 1237 static void mv_dump_all_regs(void __iomem *mmio_base, int port, 1238 struct pci_dev *pdev) 1239 { 1240 #ifdef ATA_DEBUG 1241 void __iomem *hc_base = mv_hc_base(mmio_base, 1242 port >> MV_PORT_HC_SHIFT); 1243 void __iomem *port_base; 1244 int start_port, num_ports, p, start_hc, num_hcs, hc; 1245 1246 if (0 > port) { 1247 start_hc = start_port = 0; 1248 num_ports = 8; /* shld be benign for 4 port devs */ 1249 num_hcs = 2; 1250 } else { 1251 start_hc = port >> MV_PORT_HC_SHIFT; 1252 start_port = port; 1253 num_ports = num_hcs = 1; 1254 } 1255 DPRINTK("All registers for port(s) %u-%u:\n", start_port, 1256 num_ports > 1 ? num_ports - 1 : start_port); 1257 1258 if (NULL != pdev) { 1259 DPRINTK("PCI config space regs:\n"); 1260 mv_dump_pci_cfg(pdev, 0x68); 1261 } 1262 DPRINTK("PCI regs:\n"); 1263 mv_dump_mem(mmio_base+0xc00, 0x3c); 1264 mv_dump_mem(mmio_base+0xd00, 0x34); 1265 mv_dump_mem(mmio_base+0xf00, 0x4); 1266 mv_dump_mem(mmio_base+0x1d00, 0x6c); 1267 for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1268 hc_base = mv_hc_base(mmio_base, hc); 1269 DPRINTK("HC regs (HC %i):\n", hc); 1270 mv_dump_mem(hc_base, 0x1c); 1271 } 1272 for (p = start_port; p < start_port + num_ports; p++) { 1273 port_base = mv_port_base(mmio_base, p); 1274 DPRINTK("EDMA regs (port %i):\n", p); 1275 mv_dump_mem(port_base, 0x54); 1276 DPRINTK("SATA regs (port %i):\n", p); 1277 mv_dump_mem(port_base+0x300, 0x60); 1278 } 1279 #endif 1280 } 1281 1282 static unsigned int mv_scr_offset(unsigned int sc_reg_in) 1283 { 1284 unsigned int ofs; 1285 1286 switch (sc_reg_in) { 1287 case SCR_STATUS: 1288 case SCR_CONTROL: 1289 case SCR_ERROR: 1290 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 1291 break; 1292 case SCR_ACTIVE: 1293 ofs = SATA_ACTIVE; /* active is not with the others */ 1294 break; 1295 default: 1296 ofs = 0xffffffffU; 1297 break; 1298 } 1299 return ofs; 1300 } 1301 1302 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 1303 { 1304 unsigned int ofs = mv_scr_offset(sc_reg_in); 1305 1306 if (ofs != 0xffffffffU) { 1307 *val = readl(mv_ap_base(link->ap) + ofs); 1308 return 0; 1309 } else 1310 return -EINVAL; 1311 } 1312 1313 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 1314 { 1315 unsigned int ofs = mv_scr_offset(sc_reg_in); 1316 1317 if (ofs != 0xffffffffU) { 1318 void __iomem *addr = mv_ap_base(link->ap) + ofs; 1319 if (sc_reg_in == SCR_CONTROL) { 1320 /* 1321 * Workaround for 88SX60x1 FEr SATA#26: 1322 * 1323 * COMRESETs have to take care not to accidently 1324 * put the drive to sleep when writing SCR_CONTROL. 1325 * Setting bits 12..15 prevents this problem. 1326 * 1327 * So if we see an outbound COMMRESET, set those bits. 1328 * Ditto for the followup write that clears the reset. 1329 * 1330 * The proprietary driver does this for 1331 * all chip versions, and so do we. 1332 */ 1333 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 1334 val |= 0xf000; 1335 } 1336 writelfl(val, addr); 1337 return 0; 1338 } else 1339 return -EINVAL; 1340 } 1341 1342 static void mv6_dev_config(struct ata_device *adev) 1343 { 1344 /* 1345 * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1346 * 1347 * Gen-II does not support NCQ over a port multiplier 1348 * (no FIS-based switching). 1349 */ 1350 if (adev->flags & ATA_DFLAG_NCQ) { 1351 if (sata_pmp_attached(adev->link->ap)) { 1352 adev->flags &= ~ATA_DFLAG_NCQ; 1353 ata_dev_printk(adev, KERN_INFO, 1354 "NCQ disabled for command-based switching\n"); 1355 } 1356 } 1357 } 1358 1359 static int mv_qc_defer(struct ata_queued_cmd *qc) 1360 { 1361 struct ata_link *link = qc->dev->link; 1362 struct ata_port *ap = link->ap; 1363 struct mv_port_priv *pp = ap->private_data; 1364 1365 /* 1366 * Don't allow new commands if we're in a delayed EH state 1367 * for NCQ and/or FIS-based switching. 1368 */ 1369 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 1370 return ATA_DEFER_PORT; 1371 /* 1372 * If the port is completely idle, then allow the new qc. 1373 */ 1374 if (ap->nr_active_links == 0) 1375 return 0; 1376 1377 /* 1378 * The port is operating in host queuing mode (EDMA) with NCQ 1379 * enabled, allow multiple NCQ commands. EDMA also allows 1380 * queueing multiple DMA commands but libata core currently 1381 * doesn't allow it. 1382 */ 1383 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 1384 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol)) 1385 return 0; 1386 1387 return ATA_DEFER_PORT; 1388 } 1389 1390 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1391 { 1392 struct mv_port_priv *pp = ap->private_data; 1393 void __iomem *port_mmio; 1394 1395 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 1396 u32 ltmode, *old_ltmode = &pp->cached.ltmode; 1397 u32 haltcond, *old_haltcond = &pp->cached.haltcond; 1398 1399 ltmode = *old_ltmode & ~LTMODE_BIT8; 1400 haltcond = *old_haltcond | EDMA_ERR_DEV; 1401 1402 if (want_fbs) { 1403 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 1404 ltmode = *old_ltmode | LTMODE_BIT8; 1405 if (want_ncq) 1406 haltcond &= ~EDMA_ERR_DEV; 1407 else 1408 fiscfg |= FISCFG_WAIT_DEV_ERR; 1409 } else { 1410 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1411 } 1412 1413 port_mmio = mv_ap_base(ap); 1414 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1415 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1416 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1417 } 1418 1419 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1420 { 1421 struct mv_host_priv *hpriv = ap->host->private_data; 1422 u32 old, new; 1423 1424 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1425 old = readl(hpriv->base + GPIO_PORT_CTL); 1426 if (want_ncq) 1427 new = old | (1 << 22); 1428 else 1429 new = old & ~(1 << 22); 1430 if (new != old) 1431 writel(new, hpriv->base + GPIO_PORT_CTL); 1432 } 1433 1434 /** 1435 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 1436 * @ap: Port being initialized 1437 * 1438 * There are two DMA modes on these chips: basic DMA, and EDMA. 1439 * 1440 * Bit-0 of the "EDMA RESERVED" register enables/disables use 1441 * of basic DMA on the GEN_IIE versions of the chips. 1442 * 1443 * This bit survives EDMA resets, and must be set for basic DMA 1444 * to function, and should be cleared when EDMA is active. 1445 */ 1446 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1447 { 1448 struct mv_port_priv *pp = ap->private_data; 1449 u32 new, *old = &pp->cached.unknown_rsvd; 1450 1451 if (enable_bmdma) 1452 new = *old | 1; 1453 else 1454 new = *old & ~1; 1455 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1456 } 1457 1458 /* 1459 * SOC chips have an issue whereby the HDD LEDs don't always blink 1460 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1461 * of the SOC takes care of it, generating a steady blink rate when 1462 * any drive on the chip is active. 1463 * 1464 * Unfortunately, the blink mode is a global hardware setting for the SOC, 1465 * so we must use it whenever at least one port on the SOC has NCQ enabled. 1466 * 1467 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1468 * LED operation works then, and provides better (more accurate) feedback. 1469 * 1470 * Note that this code assumes that an SOC never has more than one HC onboard. 1471 */ 1472 static void mv_soc_led_blink_enable(struct ata_port *ap) 1473 { 1474 struct ata_host *host = ap->host; 1475 struct mv_host_priv *hpriv = host->private_data; 1476 void __iomem *hc_mmio; 1477 u32 led_ctrl; 1478 1479 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1480 return; 1481 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1482 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1483 led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1484 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1485 } 1486 1487 static void mv_soc_led_blink_disable(struct ata_port *ap) 1488 { 1489 struct ata_host *host = ap->host; 1490 struct mv_host_priv *hpriv = host->private_data; 1491 void __iomem *hc_mmio; 1492 u32 led_ctrl; 1493 unsigned int port; 1494 1495 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1496 return; 1497 1498 /* disable led-blink only if no ports are using NCQ */ 1499 for (port = 0; port < hpriv->n_ports; port++) { 1500 struct ata_port *this_ap = host->ports[port]; 1501 struct mv_port_priv *pp = this_ap->private_data; 1502 1503 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1504 return; 1505 } 1506 1507 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1508 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1509 led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1510 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1511 } 1512 1513 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1514 { 1515 u32 cfg; 1516 struct mv_port_priv *pp = ap->private_data; 1517 struct mv_host_priv *hpriv = ap->host->private_data; 1518 void __iomem *port_mmio = mv_ap_base(ap); 1519 1520 /* set up non-NCQ EDMA configuration */ 1521 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1522 pp->pp_flags &= 1523 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1524 1525 if (IS_GEN_I(hpriv)) 1526 cfg |= (1 << 8); /* enab config burst size mask */ 1527 1528 else if (IS_GEN_II(hpriv)) { 1529 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1530 mv_60x1_errata_sata25(ap, want_ncq); 1531 1532 } else if (IS_GEN_IIE(hpriv)) { 1533 int want_fbs = sata_pmp_attached(ap); 1534 /* 1535 * Possible future enhancement: 1536 * 1537 * The chip can use FBS with non-NCQ, if we allow it, 1538 * But first we need to have the error handling in place 1539 * for this mode (datasheet section 7.3.15.4.2.3). 1540 * So disallow non-NCQ FBS for now. 1541 */ 1542 want_fbs &= want_ncq; 1543 1544 mv_config_fbs(ap, want_ncq, want_fbs); 1545 1546 if (want_fbs) { 1547 pp->pp_flags |= MV_PP_FLAG_FBS_EN; 1548 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1549 } 1550 1551 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1552 if (want_edma) { 1553 cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1554 if (!IS_SOC(hpriv)) 1555 cfg |= (1 << 18); /* enab early completion */ 1556 } 1557 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1558 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1559 mv_bmdma_enable_iie(ap, !want_edma); 1560 1561 if (IS_SOC(hpriv)) { 1562 if (want_ncq) 1563 mv_soc_led_blink_enable(ap); 1564 else 1565 mv_soc_led_blink_disable(ap); 1566 } 1567 } 1568 1569 if (want_ncq) { 1570 cfg |= EDMA_CFG_NCQ; 1571 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1572 } 1573 1574 writelfl(cfg, port_mmio + EDMA_CFG); 1575 } 1576 1577 static void mv_port_free_dma_mem(struct ata_port *ap) 1578 { 1579 struct mv_host_priv *hpriv = ap->host->private_data; 1580 struct mv_port_priv *pp = ap->private_data; 1581 int tag; 1582 1583 if (pp->crqb) { 1584 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1585 pp->crqb = NULL; 1586 } 1587 if (pp->crpb) { 1588 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1589 pp->crpb = NULL; 1590 } 1591 /* 1592 * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1593 * For later hardware, we have one unique sg_tbl per NCQ tag. 1594 */ 1595 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1596 if (pp->sg_tbl[tag]) { 1597 if (tag == 0 || !IS_GEN_I(hpriv)) 1598 dma_pool_free(hpriv->sg_tbl_pool, 1599 pp->sg_tbl[tag], 1600 pp->sg_tbl_dma[tag]); 1601 pp->sg_tbl[tag] = NULL; 1602 } 1603 } 1604 } 1605 1606 /** 1607 * mv_port_start - Port specific init/start routine. 1608 * @ap: ATA channel to manipulate 1609 * 1610 * Allocate and point to DMA memory, init port private memory, 1611 * zero indices. 1612 * 1613 * LOCKING: 1614 * Inherited from caller. 1615 */ 1616 static int mv_port_start(struct ata_port *ap) 1617 { 1618 struct device *dev = ap->host->dev; 1619 struct mv_host_priv *hpriv = ap->host->private_data; 1620 struct mv_port_priv *pp; 1621 unsigned long flags; 1622 int tag; 1623 1624 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1625 if (!pp) 1626 return -ENOMEM; 1627 ap->private_data = pp; 1628 1629 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1630 if (!pp->crqb) 1631 return -ENOMEM; 1632 memset(pp->crqb, 0, MV_CRQB_Q_SZ); 1633 1634 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1635 if (!pp->crpb) 1636 goto out_port_free_dma_mem; 1637 memset(pp->crpb, 0, MV_CRPB_Q_SZ); 1638 1639 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 1640 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 1641 ap->flags |= ATA_FLAG_AN; 1642 /* 1643 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1644 * For later hardware, we need one unique sg_tbl per NCQ tag. 1645 */ 1646 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1647 if (tag == 0 || !IS_GEN_I(hpriv)) { 1648 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1649 GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1650 if (!pp->sg_tbl[tag]) 1651 goto out_port_free_dma_mem; 1652 } else { 1653 pp->sg_tbl[tag] = pp->sg_tbl[0]; 1654 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1655 } 1656 } 1657 1658 spin_lock_irqsave(ap->lock, flags); 1659 mv_save_cached_regs(ap); 1660 mv_edma_cfg(ap, 0, 0); 1661 spin_unlock_irqrestore(ap->lock, flags); 1662 1663 return 0; 1664 1665 out_port_free_dma_mem: 1666 mv_port_free_dma_mem(ap); 1667 return -ENOMEM; 1668 } 1669 1670 /** 1671 * mv_port_stop - Port specific cleanup/stop routine. 1672 * @ap: ATA channel to manipulate 1673 * 1674 * Stop DMA, cleanup port memory. 1675 * 1676 * LOCKING: 1677 * This routine uses the host lock to protect the DMA stop. 1678 */ 1679 static void mv_port_stop(struct ata_port *ap) 1680 { 1681 unsigned long flags; 1682 1683 spin_lock_irqsave(ap->lock, flags); 1684 mv_stop_edma(ap); 1685 mv_enable_port_irqs(ap, 0); 1686 spin_unlock_irqrestore(ap->lock, flags); 1687 mv_port_free_dma_mem(ap); 1688 } 1689 1690 /** 1691 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 1692 * @qc: queued command whose SG list to source from 1693 * 1694 * Populate the SG list and mark the last entry. 1695 * 1696 * LOCKING: 1697 * Inherited from caller. 1698 */ 1699 static void mv_fill_sg(struct ata_queued_cmd *qc) 1700 { 1701 struct mv_port_priv *pp = qc->ap->private_data; 1702 struct scatterlist *sg; 1703 struct mv_sg *mv_sg, *last_sg = NULL; 1704 unsigned int si; 1705 1706 mv_sg = pp->sg_tbl[qc->tag]; 1707 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1708 dma_addr_t addr = sg_dma_address(sg); 1709 u32 sg_len = sg_dma_len(sg); 1710 1711 while (sg_len) { 1712 u32 offset = addr & 0xffff; 1713 u32 len = sg_len; 1714 1715 if (offset + len > 0x10000) 1716 len = 0x10000 - offset; 1717 1718 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 1719 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 1720 mv_sg->flags_size = cpu_to_le32(len & 0xffff); 1721 mv_sg->reserved = 0; 1722 1723 sg_len -= len; 1724 addr += len; 1725 1726 last_sg = mv_sg; 1727 mv_sg++; 1728 } 1729 } 1730 1731 if (likely(last_sg)) 1732 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 1733 mb(); /* ensure data structure is visible to the chipset */ 1734 } 1735 1736 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 1737 { 1738 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 1739 (last ? CRQB_CMD_LAST : 0); 1740 *cmdw = cpu_to_le16(tmp); 1741 } 1742 1743 /** 1744 * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1745 * @ap: Port associated with this ATA transaction. 1746 * 1747 * We need this only for ATAPI bmdma transactions, 1748 * as otherwise we experience spurious interrupts 1749 * after libata-sff handles the bmdma interrupts. 1750 */ 1751 static void mv_sff_irq_clear(struct ata_port *ap) 1752 { 1753 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1754 } 1755 1756 /** 1757 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1758 * @qc: queued command to check for chipset/DMA compatibility. 1759 * 1760 * The bmdma engines cannot handle speculative data sizes 1761 * (bytecount under/over flow). So only allow DMA for 1762 * data transfer commands with known data sizes. 1763 * 1764 * LOCKING: 1765 * Inherited from caller. 1766 */ 1767 static int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1768 { 1769 struct scsi_cmnd *scmd = qc->scsicmd; 1770 1771 if (scmd) { 1772 switch (scmd->cmnd[0]) { 1773 case READ_6: 1774 case READ_10: 1775 case READ_12: 1776 case WRITE_6: 1777 case WRITE_10: 1778 case WRITE_12: 1779 case GPCMD_READ_CD: 1780 case GPCMD_SEND_DVD_STRUCTURE: 1781 case GPCMD_SEND_CUE_SHEET: 1782 return 0; /* DMA is safe */ 1783 } 1784 } 1785 return -EOPNOTSUPP; /* use PIO instead */ 1786 } 1787 1788 /** 1789 * mv_bmdma_setup - Set up BMDMA transaction 1790 * @qc: queued command to prepare DMA for. 1791 * 1792 * LOCKING: 1793 * Inherited from caller. 1794 */ 1795 static void mv_bmdma_setup(struct ata_queued_cmd *qc) 1796 { 1797 struct ata_port *ap = qc->ap; 1798 void __iomem *port_mmio = mv_ap_base(ap); 1799 struct mv_port_priv *pp = ap->private_data; 1800 1801 mv_fill_sg(qc); 1802 1803 /* clear all DMA cmd bits */ 1804 writel(0, port_mmio + BMDMA_CMD); 1805 1806 /* load PRD table addr. */ 1807 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1808 port_mmio + BMDMA_PRD_HIGH); 1809 writelfl(pp->sg_tbl_dma[qc->tag], 1810 port_mmio + BMDMA_PRD_LOW); 1811 1812 /* issue r/w command */ 1813 ap->ops->sff_exec_command(ap, &qc->tf); 1814 } 1815 1816 /** 1817 * mv_bmdma_start - Start a BMDMA transaction 1818 * @qc: queued command to start DMA on. 1819 * 1820 * LOCKING: 1821 * Inherited from caller. 1822 */ 1823 static void mv_bmdma_start(struct ata_queued_cmd *qc) 1824 { 1825 struct ata_port *ap = qc->ap; 1826 void __iomem *port_mmio = mv_ap_base(ap); 1827 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1828 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1829 1830 /* start host DMA transaction */ 1831 writelfl(cmd, port_mmio + BMDMA_CMD); 1832 } 1833 1834 /** 1835 * mv_bmdma_stop - Stop BMDMA transfer 1836 * @qc: queued command to stop DMA on. 1837 * 1838 * Clears the ATA_DMA_START flag in the bmdma control register 1839 * 1840 * LOCKING: 1841 * Inherited from caller. 1842 */ 1843 static void mv_bmdma_stop(struct ata_queued_cmd *qc) 1844 { 1845 struct ata_port *ap = qc->ap; 1846 void __iomem *port_mmio = mv_ap_base(ap); 1847 u32 cmd; 1848 1849 /* clear start/stop bit */ 1850 cmd = readl(port_mmio + BMDMA_CMD); 1851 cmd &= ~ATA_DMA_START; 1852 writelfl(cmd, port_mmio + BMDMA_CMD); 1853 1854 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1855 ata_sff_dma_pause(ap); 1856 } 1857 1858 /** 1859 * mv_bmdma_status - Read BMDMA status 1860 * @ap: port for which to retrieve DMA status. 1861 * 1862 * Read and return equivalent of the sff BMDMA status register. 1863 * 1864 * LOCKING: 1865 * Inherited from caller. 1866 */ 1867 static u8 mv_bmdma_status(struct ata_port *ap) 1868 { 1869 void __iomem *port_mmio = mv_ap_base(ap); 1870 u32 reg, status; 1871 1872 /* 1873 * Other bits are valid only if ATA_DMA_ACTIVE==0, 1874 * and the ATA_DMA_INTR bit doesn't exist. 1875 */ 1876 reg = readl(port_mmio + BMDMA_STATUS); 1877 if (reg & ATA_DMA_ACTIVE) 1878 status = ATA_DMA_ACTIVE; 1879 else 1880 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1881 return status; 1882 } 1883 1884 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1885 { 1886 struct ata_taskfile *tf = &qc->tf; 1887 /* 1888 * Workaround for 88SX60x1 FEr SATA#24. 1889 * 1890 * Chip may corrupt WRITEs if multi_count >= 4kB. 1891 * Note that READs are unaffected. 1892 * 1893 * It's not clear if this errata really means "4K bytes", 1894 * or if it always happens for multi_count > 7 1895 * regardless of device sector_size. 1896 * 1897 * So, for safety, any write with multi_count > 7 1898 * gets converted here into a regular PIO write instead: 1899 */ 1900 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 1901 if (qc->dev->multi_count > 7) { 1902 switch (tf->command) { 1903 case ATA_CMD_WRITE_MULTI: 1904 tf->command = ATA_CMD_PIO_WRITE; 1905 break; 1906 case ATA_CMD_WRITE_MULTI_FUA_EXT: 1907 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 1908 /* fall through */ 1909 case ATA_CMD_WRITE_MULTI_EXT: 1910 tf->command = ATA_CMD_PIO_WRITE_EXT; 1911 break; 1912 } 1913 } 1914 } 1915 } 1916 1917 /** 1918 * mv_qc_prep - Host specific command preparation. 1919 * @qc: queued command to prepare 1920 * 1921 * This routine simply redirects to the general purpose routine 1922 * if command is not DMA. Else, it handles prep of the CRQB 1923 * (command request block), does some sanity checking, and calls 1924 * the SG load routine. 1925 * 1926 * LOCKING: 1927 * Inherited from caller. 1928 */ 1929 static void mv_qc_prep(struct ata_queued_cmd *qc) 1930 { 1931 struct ata_port *ap = qc->ap; 1932 struct mv_port_priv *pp = ap->private_data; 1933 __le16 *cw; 1934 struct ata_taskfile *tf = &qc->tf; 1935 u16 flags = 0; 1936 unsigned in_index; 1937 1938 switch (tf->protocol) { 1939 case ATA_PROT_DMA: 1940 case ATA_PROT_NCQ: 1941 break; /* continue below */ 1942 case ATA_PROT_PIO: 1943 mv_rw_multi_errata_sata24(qc); 1944 return; 1945 default: 1946 return; 1947 } 1948 1949 /* Fill in command request block 1950 */ 1951 if (!(tf->flags & ATA_TFLAG_WRITE)) 1952 flags |= CRQB_FLAG_READ; 1953 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1954 flags |= qc->tag << CRQB_TAG_SHIFT; 1955 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1956 1957 /* get current queue index from software */ 1958 in_index = pp->req_idx; 1959 1960 pp->crqb[in_index].sg_addr = 1961 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1962 pp->crqb[in_index].sg_addr_hi = 1963 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1964 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 1965 1966 cw = &pp->crqb[in_index].ata_cmd[0]; 1967 1968 /* Sadly, the CRQB cannot accomodate all registers--there are 1969 * only 11 bytes...so we must pick and choose required 1970 * registers based on the command. So, we drop feature and 1971 * hob_feature for [RW] DMA commands, but they are needed for 1972 * NCQ. NCQ will drop hob_nsect, which is not needed there 1973 * (nsect is used only for the tag; feat/hob_feat hold true nsect). 1974 */ 1975 switch (tf->command) { 1976 case ATA_CMD_READ: 1977 case ATA_CMD_READ_EXT: 1978 case ATA_CMD_WRITE: 1979 case ATA_CMD_WRITE_EXT: 1980 case ATA_CMD_WRITE_FUA_EXT: 1981 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 1982 break; 1983 case ATA_CMD_FPDMA_READ: 1984 case ATA_CMD_FPDMA_WRITE: 1985 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 1986 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 1987 break; 1988 default: 1989 /* The only other commands EDMA supports in non-queued and 1990 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 1991 * of which are defined/used by Linux. If we get here, this 1992 * driver needs work. 1993 * 1994 * FIXME: modify libata to give qc_prep a return value and 1995 * return error here. 1996 */ 1997 BUG_ON(tf->command); 1998 break; 1999 } 2000 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 2001 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 2002 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 2003 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 2004 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 2005 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 2006 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 2007 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 2008 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 2009 2010 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2011 return; 2012 mv_fill_sg(qc); 2013 } 2014 2015 /** 2016 * mv_qc_prep_iie - Host specific command preparation. 2017 * @qc: queued command to prepare 2018 * 2019 * This routine simply redirects to the general purpose routine 2020 * if command is not DMA. Else, it handles prep of the CRQB 2021 * (command request block), does some sanity checking, and calls 2022 * the SG load routine. 2023 * 2024 * LOCKING: 2025 * Inherited from caller. 2026 */ 2027 static void mv_qc_prep_iie(struct ata_queued_cmd *qc) 2028 { 2029 struct ata_port *ap = qc->ap; 2030 struct mv_port_priv *pp = ap->private_data; 2031 struct mv_crqb_iie *crqb; 2032 struct ata_taskfile *tf = &qc->tf; 2033 unsigned in_index; 2034 u32 flags = 0; 2035 2036 if ((tf->protocol != ATA_PROT_DMA) && 2037 (tf->protocol != ATA_PROT_NCQ)) 2038 return; 2039 2040 /* Fill in Gen IIE command request block */ 2041 if (!(tf->flags & ATA_TFLAG_WRITE)) 2042 flags |= CRQB_FLAG_READ; 2043 2044 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2045 flags |= qc->tag << CRQB_TAG_SHIFT; 2046 flags |= qc->tag << CRQB_HOSTQ_SHIFT; 2047 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2048 2049 /* get current queue index from software */ 2050 in_index = pp->req_idx; 2051 2052 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2053 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2054 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2055 crqb->flags = cpu_to_le32(flags); 2056 2057 crqb->ata_cmd[0] = cpu_to_le32( 2058 (tf->command << 16) | 2059 (tf->feature << 24) 2060 ); 2061 crqb->ata_cmd[1] = cpu_to_le32( 2062 (tf->lbal << 0) | 2063 (tf->lbam << 8) | 2064 (tf->lbah << 16) | 2065 (tf->device << 24) 2066 ); 2067 crqb->ata_cmd[2] = cpu_to_le32( 2068 (tf->hob_lbal << 0) | 2069 (tf->hob_lbam << 8) | 2070 (tf->hob_lbah << 16) | 2071 (tf->hob_feature << 24) 2072 ); 2073 crqb->ata_cmd[3] = cpu_to_le32( 2074 (tf->nsect << 0) | 2075 (tf->hob_nsect << 8) 2076 ); 2077 2078 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2079 return; 2080 mv_fill_sg(qc); 2081 } 2082 2083 /** 2084 * mv_sff_check_status - fetch device status, if valid 2085 * @ap: ATA port to fetch status from 2086 * 2087 * When using command issue via mv_qc_issue_fis(), 2088 * the initial ATA_BUSY state does not show up in the 2089 * ATA status (shadow) register. This can confuse libata! 2090 * 2091 * So we have a hook here to fake ATA_BUSY for that situation, 2092 * until the first time a BUSY, DRQ, or ERR bit is seen. 2093 * 2094 * The rest of the time, it simply returns the ATA status register. 2095 */ 2096 static u8 mv_sff_check_status(struct ata_port *ap) 2097 { 2098 u8 stat = ioread8(ap->ioaddr.status_addr); 2099 struct mv_port_priv *pp = ap->private_data; 2100 2101 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2102 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2103 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2104 else 2105 stat = ATA_BUSY; 2106 } 2107 return stat; 2108 } 2109 2110 /** 2111 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 2112 * @fis: fis to be sent 2113 * @nwords: number of 32-bit words in the fis 2114 */ 2115 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 2116 { 2117 void __iomem *port_mmio = mv_ap_base(ap); 2118 u32 ifctl, old_ifctl, ifstat; 2119 int i, timeout = 200, final_word = nwords - 1; 2120 2121 /* Initiate FIS transmission mode */ 2122 old_ifctl = readl(port_mmio + SATA_IFCTL); 2123 ifctl = 0x100 | (old_ifctl & 0xf); 2124 writelfl(ifctl, port_mmio + SATA_IFCTL); 2125 2126 /* Send all words of the FIS except for the final word */ 2127 for (i = 0; i < final_word; ++i) 2128 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 2129 2130 /* Flag end-of-transmission, and then send the final word */ 2131 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2132 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 2133 2134 /* 2135 * Wait for FIS transmission to complete. 2136 * This typically takes just a single iteration. 2137 */ 2138 do { 2139 ifstat = readl(port_mmio + SATA_IFSTAT); 2140 } while (!(ifstat & 0x1000) && --timeout); 2141 2142 /* Restore original port configuration */ 2143 writelfl(old_ifctl, port_mmio + SATA_IFCTL); 2144 2145 /* See if it worked */ 2146 if ((ifstat & 0x3000) != 0x1000) { 2147 ata_port_printk(ap, KERN_WARNING, 2148 "%s transmission error, ifstat=%08x\n", 2149 __func__, ifstat); 2150 return AC_ERR_OTHER; 2151 } 2152 return 0; 2153 } 2154 2155 /** 2156 * mv_qc_issue_fis - Issue a command directly as a FIS 2157 * @qc: queued command to start 2158 * 2159 * Note that the ATA shadow registers are not updated 2160 * after command issue, so the device will appear "READY" 2161 * if polled, even while it is BUSY processing the command. 2162 * 2163 * So we use a status hook to fake ATA_BUSY until the drive changes state. 2164 * 2165 * Note: we don't get updated shadow regs on *completion* 2166 * of non-data commands. So avoid sending them via this function, 2167 * as they will appear to have completed immediately. 2168 * 2169 * GEN_IIE has special registers that we could get the result tf from, 2170 * but earlier chipsets do not. For now, we ignore those registers. 2171 */ 2172 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 2173 { 2174 struct ata_port *ap = qc->ap; 2175 struct mv_port_priv *pp = ap->private_data; 2176 struct ata_link *link = qc->dev->link; 2177 u32 fis[5]; 2178 int err = 0; 2179 2180 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 2181 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0])); 2182 if (err) 2183 return err; 2184 2185 switch (qc->tf.protocol) { 2186 case ATAPI_PROT_PIO: 2187 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 2188 /* fall through */ 2189 case ATAPI_PROT_NODATA: 2190 ap->hsm_task_state = HSM_ST_FIRST; 2191 break; 2192 case ATA_PROT_PIO: 2193 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 2194 if (qc->tf.flags & ATA_TFLAG_WRITE) 2195 ap->hsm_task_state = HSM_ST_FIRST; 2196 else 2197 ap->hsm_task_state = HSM_ST; 2198 break; 2199 default: 2200 ap->hsm_task_state = HSM_ST_LAST; 2201 break; 2202 } 2203 2204 if (qc->tf.flags & ATA_TFLAG_POLLING) 2205 ata_pio_queue_task(ap, qc, 0); 2206 return 0; 2207 } 2208 2209 /** 2210 * mv_qc_issue - Initiate a command to the host 2211 * @qc: queued command to start 2212 * 2213 * This routine simply redirects to the general purpose routine 2214 * if command is not DMA. Else, it sanity checks our local 2215 * caches of the request producer/consumer indices then enables 2216 * DMA and bumps the request producer index. 2217 * 2218 * LOCKING: 2219 * Inherited from caller. 2220 */ 2221 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 2222 { 2223 static int limit_warnings = 10; 2224 struct ata_port *ap = qc->ap; 2225 void __iomem *port_mmio = mv_ap_base(ap); 2226 struct mv_port_priv *pp = ap->private_data; 2227 u32 in_index; 2228 unsigned int port_irqs; 2229 2230 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2231 2232 switch (qc->tf.protocol) { 2233 case ATA_PROT_DMA: 2234 case ATA_PROT_NCQ: 2235 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2236 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2237 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2238 2239 /* Write the request in pointer to kick the EDMA to life */ 2240 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2241 port_mmio + EDMA_REQ_Q_IN_PTR); 2242 return 0; 2243 2244 case ATA_PROT_PIO: 2245 /* 2246 * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2247 * 2248 * Someday, we might implement special polling workarounds 2249 * for these, but it all seems rather unnecessary since we 2250 * normally use only DMA for commands which transfer more 2251 * than a single block of data. 2252 * 2253 * Much of the time, this could just work regardless. 2254 * So for now, just log the incident, and allow the attempt. 2255 */ 2256 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2257 --limit_warnings; 2258 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 2259 ": attempting PIO w/multiple DRQ: " 2260 "this may fail due to h/w errata\n"); 2261 } 2262 /* drop through */ 2263 case ATA_PROT_NODATA: 2264 case ATAPI_PROT_PIO: 2265 case ATAPI_PROT_NODATA: 2266 if (ap->flags & ATA_FLAG_PIO_POLLING) 2267 qc->tf.flags |= ATA_TFLAG_POLLING; 2268 break; 2269 } 2270 2271 if (qc->tf.flags & ATA_TFLAG_POLLING) 2272 port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 2273 else 2274 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 2275 2276 /* 2277 * We're about to send a non-EDMA capable command to the 2278 * port. Turn off EDMA so there won't be problems accessing 2279 * shadow block, etc registers. 2280 */ 2281 mv_stop_edma(ap); 2282 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 2283 mv_pmp_select(ap, qc->dev->link->pmp); 2284 2285 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 2286 struct mv_host_priv *hpriv = ap->host->private_data; 2287 /* 2288 * Workaround for 88SX60x1 FEr SATA#25 (part 2). 2289 * 2290 * After any NCQ error, the READ_LOG_EXT command 2291 * from libata-eh *must* use mv_qc_issue_fis(). 2292 * Otherwise it might fail, due to chip errata. 2293 * 2294 * Rather than special-case it, we'll just *always* 2295 * use this method here for READ_LOG_EXT, making for 2296 * easier testing. 2297 */ 2298 if (IS_GEN_II(hpriv)) 2299 return mv_qc_issue_fis(qc); 2300 } 2301 return ata_sff_qc_issue(qc); 2302 } 2303 2304 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 2305 { 2306 struct mv_port_priv *pp = ap->private_data; 2307 struct ata_queued_cmd *qc; 2308 2309 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 2310 return NULL; 2311 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2312 if (qc) { 2313 if (qc->tf.flags & ATA_TFLAG_POLLING) 2314 qc = NULL; 2315 else if (!(qc->flags & ATA_QCFLAG_ACTIVE)) 2316 qc = NULL; 2317 } 2318 return qc; 2319 } 2320 2321 static void mv_pmp_error_handler(struct ata_port *ap) 2322 { 2323 unsigned int pmp, pmp_map; 2324 struct mv_port_priv *pp = ap->private_data; 2325 2326 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 2327 /* 2328 * Perform NCQ error analysis on failed PMPs 2329 * before we freeze the port entirely. 2330 * 2331 * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 2332 */ 2333 pmp_map = pp->delayed_eh_pmp_map; 2334 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 2335 for (pmp = 0; pmp_map != 0; pmp++) { 2336 unsigned int this_pmp = (1 << pmp); 2337 if (pmp_map & this_pmp) { 2338 struct ata_link *link = &ap->pmp_link[pmp]; 2339 pmp_map &= ~this_pmp; 2340 ata_eh_analyze_ncq_error(link); 2341 } 2342 } 2343 ata_port_freeze(ap); 2344 } 2345 sata_pmp_error_handler(ap); 2346 } 2347 2348 static unsigned int mv_get_err_pmp_map(struct ata_port *ap) 2349 { 2350 void __iomem *port_mmio = mv_ap_base(ap); 2351 2352 return readl(port_mmio + SATA_TESTCTL) >> 16; 2353 } 2354 2355 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 2356 { 2357 struct ata_eh_info *ehi; 2358 unsigned int pmp; 2359 2360 /* 2361 * Initialize EH info for PMPs which saw device errors 2362 */ 2363 ehi = &ap->link.eh_info; 2364 for (pmp = 0; pmp_map != 0; pmp++) { 2365 unsigned int this_pmp = (1 << pmp); 2366 if (pmp_map & this_pmp) { 2367 struct ata_link *link = &ap->pmp_link[pmp]; 2368 2369 pmp_map &= ~this_pmp; 2370 ehi = &link->eh_info; 2371 ata_ehi_clear_desc(ehi); 2372 ata_ehi_push_desc(ehi, "dev err"); 2373 ehi->err_mask |= AC_ERR_DEV; 2374 ehi->action |= ATA_EH_RESET; 2375 ata_link_abort(link); 2376 } 2377 } 2378 } 2379 2380 static int mv_req_q_empty(struct ata_port *ap) 2381 { 2382 void __iomem *port_mmio = mv_ap_base(ap); 2383 u32 in_ptr, out_ptr; 2384 2385 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 2386 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2387 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 2388 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2389 return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 2390 } 2391 2392 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 2393 { 2394 struct mv_port_priv *pp = ap->private_data; 2395 int failed_links; 2396 unsigned int old_map, new_map; 2397 2398 /* 2399 * Device error during FBS+NCQ operation: 2400 * 2401 * Set a port flag to prevent further I/O being enqueued. 2402 * Leave the EDMA running to drain outstanding commands from this port. 2403 * Perform the post-mortem/EH only when all responses are complete. 2404 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 2405 */ 2406 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 2407 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 2408 pp->delayed_eh_pmp_map = 0; 2409 } 2410 old_map = pp->delayed_eh_pmp_map; 2411 new_map = old_map | mv_get_err_pmp_map(ap); 2412 2413 if (old_map != new_map) { 2414 pp->delayed_eh_pmp_map = new_map; 2415 mv_pmp_eh_prep(ap, new_map & ~old_map); 2416 } 2417 failed_links = hweight16(new_map); 2418 2419 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 2420 "failed_links=%d nr_active_links=%d\n", 2421 __func__, pp->delayed_eh_pmp_map, 2422 ap->qc_active, failed_links, 2423 ap->nr_active_links); 2424 2425 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 2426 mv_process_crpb_entries(ap, pp); 2427 mv_stop_edma(ap); 2428 mv_eh_freeze(ap); 2429 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 2430 return 1; /* handled */ 2431 } 2432 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 2433 return 1; /* handled */ 2434 } 2435 2436 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 2437 { 2438 /* 2439 * Possible future enhancement: 2440 * 2441 * FBS+non-NCQ operation is not yet implemented. 2442 * See related notes in mv_edma_cfg(). 2443 * 2444 * Device error during FBS+non-NCQ operation: 2445 * 2446 * We need to snapshot the shadow registers for each failed command. 2447 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 2448 */ 2449 return 0; /* not handled */ 2450 } 2451 2452 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 2453 { 2454 struct mv_port_priv *pp = ap->private_data; 2455 2456 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 2457 return 0; /* EDMA was not active: not handled */ 2458 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 2459 return 0; /* FBS was not active: not handled */ 2460 2461 if (!(edma_err_cause & EDMA_ERR_DEV)) 2462 return 0; /* non DEV error: not handled */ 2463 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 2464 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 2465 return 0; /* other problems: not handled */ 2466 2467 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 2468 /* 2469 * EDMA should NOT have self-disabled for this case. 2470 * If it did, then something is wrong elsewhere, 2471 * and we cannot handle it here. 2472 */ 2473 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2474 ata_port_printk(ap, KERN_WARNING, 2475 "%s: err_cause=0x%x pp_flags=0x%x\n", 2476 __func__, edma_err_cause, pp->pp_flags); 2477 return 0; /* not handled */ 2478 } 2479 return mv_handle_fbs_ncq_dev_err(ap); 2480 } else { 2481 /* 2482 * EDMA should have self-disabled for this case. 2483 * If it did not, then something is wrong elsewhere, 2484 * and we cannot handle it here. 2485 */ 2486 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 2487 ata_port_printk(ap, KERN_WARNING, 2488 "%s: err_cause=0x%x pp_flags=0x%x\n", 2489 __func__, edma_err_cause, pp->pp_flags); 2490 return 0; /* not handled */ 2491 } 2492 return mv_handle_fbs_non_ncq_dev_err(ap); 2493 } 2494 return 0; /* not handled */ 2495 } 2496 2497 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 2498 { 2499 struct ata_eh_info *ehi = &ap->link.eh_info; 2500 char *when = "idle"; 2501 2502 ata_ehi_clear_desc(ehi); 2503 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2504 when = "disabled"; 2505 } else if (edma_was_enabled) { 2506 when = "EDMA enabled"; 2507 } else { 2508 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 2509 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2510 when = "polling"; 2511 } 2512 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 2513 ehi->err_mask |= AC_ERR_OTHER; 2514 ehi->action |= ATA_EH_RESET; 2515 ata_port_freeze(ap); 2516 } 2517 2518 /** 2519 * mv_err_intr - Handle error interrupts on the port 2520 * @ap: ATA channel to manipulate 2521 * 2522 * Most cases require a full reset of the chip's state machine, 2523 * which also performs a COMRESET. 2524 * Also, if the port disabled DMA, update our cached copy to match. 2525 * 2526 * LOCKING: 2527 * Inherited from caller. 2528 */ 2529 static void mv_err_intr(struct ata_port *ap) 2530 { 2531 void __iomem *port_mmio = mv_ap_base(ap); 2532 u32 edma_err_cause, eh_freeze_mask, serr = 0; 2533 u32 fis_cause = 0; 2534 struct mv_port_priv *pp = ap->private_data; 2535 struct mv_host_priv *hpriv = ap->host->private_data; 2536 unsigned int action = 0, err_mask = 0; 2537 struct ata_eh_info *ehi = &ap->link.eh_info; 2538 struct ata_queued_cmd *qc; 2539 int abort = 0; 2540 2541 /* 2542 * Read and clear the SError and err_cause bits. 2543 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2544 * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 2545 */ 2546 sata_scr_read(&ap->link, SCR_ERROR, &serr); 2547 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 2548 2549 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2550 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2551 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2552 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2553 } 2554 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2555 2556 if (edma_err_cause & EDMA_ERR_DEV) { 2557 /* 2558 * Device errors during FIS-based switching operation 2559 * require special handling. 2560 */ 2561 if (mv_handle_dev_err(ap, edma_err_cause)) 2562 return; 2563 } 2564 2565 qc = mv_get_active_qc(ap); 2566 ata_ehi_clear_desc(ehi); 2567 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 2568 edma_err_cause, pp->pp_flags); 2569 2570 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2571 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2572 if (fis_cause & FIS_IRQ_CAUSE_AN) { 2573 u32 ec = edma_err_cause & 2574 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2575 sata_async_notification(ap); 2576 if (!ec) 2577 return; /* Just an AN; no need for the nukes */ 2578 ata_ehi_push_desc(ehi, "SDB notify"); 2579 } 2580 } 2581 /* 2582 * All generations share these EDMA error cause bits: 2583 */ 2584 if (edma_err_cause & EDMA_ERR_DEV) { 2585 err_mask |= AC_ERR_DEV; 2586 action |= ATA_EH_RESET; 2587 ata_ehi_push_desc(ehi, "dev error"); 2588 } 2589 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 2590 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2591 EDMA_ERR_INTRL_PAR)) { 2592 err_mask |= AC_ERR_ATA_BUS; 2593 action |= ATA_EH_RESET; 2594 ata_ehi_push_desc(ehi, "parity error"); 2595 } 2596 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2597 ata_ehi_hotplugged(ehi); 2598 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2599 "dev disconnect" : "dev connect"); 2600 action |= ATA_EH_RESET; 2601 } 2602 2603 /* 2604 * Gen-I has a different SELF_DIS bit, 2605 * different FREEZE bits, and no SERR bit: 2606 */ 2607 if (IS_GEN_I(hpriv)) { 2608 eh_freeze_mask = EDMA_EH_FREEZE_5; 2609 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2610 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2611 ata_ehi_push_desc(ehi, "EDMA self-disable"); 2612 } 2613 } else { 2614 eh_freeze_mask = EDMA_EH_FREEZE; 2615 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2616 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2617 ata_ehi_push_desc(ehi, "EDMA self-disable"); 2618 } 2619 if (edma_err_cause & EDMA_ERR_SERR) { 2620 ata_ehi_push_desc(ehi, "SError=%08x", serr); 2621 err_mask |= AC_ERR_ATA_BUS; 2622 action |= ATA_EH_RESET; 2623 } 2624 } 2625 2626 if (!err_mask) { 2627 err_mask = AC_ERR_OTHER; 2628 action |= ATA_EH_RESET; 2629 } 2630 2631 ehi->serror |= serr; 2632 ehi->action |= action; 2633 2634 if (qc) 2635 qc->err_mask |= err_mask; 2636 else 2637 ehi->err_mask |= err_mask; 2638 2639 if (err_mask == AC_ERR_DEV) { 2640 /* 2641 * Cannot do ata_port_freeze() here, 2642 * because it would kill PIO access, 2643 * which is needed for further diagnosis. 2644 */ 2645 mv_eh_freeze(ap); 2646 abort = 1; 2647 } else if (edma_err_cause & eh_freeze_mask) { 2648 /* 2649 * Note to self: ata_port_freeze() calls ata_port_abort() 2650 */ 2651 ata_port_freeze(ap); 2652 } else { 2653 abort = 1; 2654 } 2655 2656 if (abort) { 2657 if (qc) 2658 ata_link_abort(qc->dev->link); 2659 else 2660 ata_port_abort(ap); 2661 } 2662 } 2663 2664 static void mv_process_crpb_response(struct ata_port *ap, 2665 struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2666 { 2667 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2668 2669 if (qc) { 2670 u8 ata_status; 2671 u16 edma_status = le16_to_cpu(response->flags); 2672 /* 2673 * edma_status from a response queue entry: 2674 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2675 * MSB is saved ATA status from command completion. 2676 */ 2677 if (!ncq_enabled) { 2678 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2679 if (err_cause) { 2680 /* 2681 * Error will be seen/handled by mv_err_intr(). 2682 * So do nothing at all here. 2683 */ 2684 return; 2685 } 2686 } 2687 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 2688 if (!ac_err_mask(ata_status)) 2689 ata_qc_complete(qc); 2690 /* else: leave it for mv_err_intr() */ 2691 } else { 2692 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2693 __func__, tag); 2694 } 2695 } 2696 2697 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2698 { 2699 void __iomem *port_mmio = mv_ap_base(ap); 2700 struct mv_host_priv *hpriv = ap->host->private_data; 2701 u32 in_index; 2702 bool work_done = false; 2703 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2704 2705 /* Get the hardware queue position index */ 2706 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2707 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2708 2709 /* Process new responses from since the last time we looked */ 2710 while (in_index != pp->resp_idx) { 2711 unsigned int tag; 2712 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2713 2714 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2715 2716 if (IS_GEN_I(hpriv)) { 2717 /* 50xx: no NCQ, only one command active at a time */ 2718 tag = ap->link.active_tag; 2719 } else { 2720 /* Gen II/IIE: get command tag from CRPB entry */ 2721 tag = le16_to_cpu(response->id) & 0x1f; 2722 } 2723 mv_process_crpb_response(ap, response, tag, ncq_enabled); 2724 work_done = true; 2725 } 2726 2727 /* Update the software queue position index in hardware */ 2728 if (work_done) 2729 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2730 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2731 port_mmio + EDMA_RSP_Q_OUT_PTR); 2732 } 2733 2734 static void mv_port_intr(struct ata_port *ap, u32 port_cause) 2735 { 2736 struct mv_port_priv *pp; 2737 int edma_was_enabled; 2738 2739 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2740 mv_unexpected_intr(ap, 0); 2741 return; 2742 } 2743 /* 2744 * Grab a snapshot of the EDMA_EN flag setting, 2745 * so that we have a consistent view for this port, 2746 * even if something we call of our routines changes it. 2747 */ 2748 pp = ap->private_data; 2749 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2750 /* 2751 * Process completed CRPB response(s) before other events. 2752 */ 2753 if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2754 mv_process_crpb_entries(ap, pp); 2755 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 2756 mv_handle_fbs_ncq_dev_err(ap); 2757 } 2758 /* 2759 * Handle chip-reported errors, or continue on to handle PIO. 2760 */ 2761 if (unlikely(port_cause & ERR_IRQ)) { 2762 mv_err_intr(ap); 2763 } else if (!edma_was_enabled) { 2764 struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2765 if (qc) 2766 ata_sff_host_intr(ap, qc); 2767 else 2768 mv_unexpected_intr(ap, edma_was_enabled); 2769 } 2770 } 2771 2772 /** 2773 * mv_host_intr - Handle all interrupts on the given host controller 2774 * @host: host specific structure 2775 * @main_irq_cause: Main interrupt cause register for the chip. 2776 * 2777 * LOCKING: 2778 * Inherited from caller. 2779 */ 2780 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 2781 { 2782 struct mv_host_priv *hpriv = host->private_data; 2783 void __iomem *mmio = hpriv->base, *hc_mmio; 2784 unsigned int handled = 0, port; 2785 2786 /* If asserted, clear the "all ports" IRQ coalescing bit */ 2787 if (main_irq_cause & ALL_PORTS_COAL_DONE) 2788 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 2789 2790 for (port = 0; port < hpriv->n_ports; port++) { 2791 struct ata_port *ap = host->ports[port]; 2792 unsigned int p, shift, hardport, port_cause; 2793 2794 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2795 /* 2796 * Each hc within the host has its own hc_irq_cause register, 2797 * where the interrupting ports bits get ack'd. 2798 */ 2799 if (hardport == 0) { /* first port on this hc ? */ 2800 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2801 u32 port_mask, ack_irqs; 2802 /* 2803 * Skip this entire hc if nothing pending for any ports 2804 */ 2805 if (!hc_cause) { 2806 port += MV_PORTS_PER_HC - 1; 2807 continue; 2808 } 2809 /* 2810 * We don't need/want to read the hc_irq_cause register, 2811 * because doing so hurts performance, and 2812 * main_irq_cause already gives us everything we need. 2813 * 2814 * But we do have to *write* to the hc_irq_cause to ack 2815 * the ports that we are handling this time through. 2816 * 2817 * This requires that we create a bitmap for those 2818 * ports which interrupted us, and use that bitmap 2819 * to ack (only) those ports via hc_irq_cause. 2820 */ 2821 ack_irqs = 0; 2822 if (hc_cause & PORTS_0_3_COAL_DONE) 2823 ack_irqs = HC_COAL_IRQ; 2824 for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2825 if ((port + p) >= hpriv->n_ports) 2826 break; 2827 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2828 if (hc_cause & port_mask) 2829 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2830 } 2831 hc_mmio = mv_hc_base_from_port(mmio, port); 2832 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2833 handled = 1; 2834 } 2835 /* 2836 * Handle interrupts signalled for this port: 2837 */ 2838 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2839 if (port_cause) 2840 mv_port_intr(ap, port_cause); 2841 } 2842 return handled; 2843 } 2844 2845 static int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2846 { 2847 struct mv_host_priv *hpriv = host->private_data; 2848 struct ata_port *ap; 2849 struct ata_queued_cmd *qc; 2850 struct ata_eh_info *ehi; 2851 unsigned int i, err_mask, printed = 0; 2852 u32 err_cause; 2853 2854 err_cause = readl(mmio + hpriv->irq_cause_offset); 2855 2856 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2857 err_cause); 2858 2859 DPRINTK("All regs @ PCI error\n"); 2860 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2861 2862 writelfl(0, mmio + hpriv->irq_cause_offset); 2863 2864 for (i = 0; i < host->n_ports; i++) { 2865 ap = host->ports[i]; 2866 if (!ata_link_offline(&ap->link)) { 2867 ehi = &ap->link.eh_info; 2868 ata_ehi_clear_desc(ehi); 2869 if (!printed++) 2870 ata_ehi_push_desc(ehi, 2871 "PCI err cause 0x%08x", err_cause); 2872 err_mask = AC_ERR_HOST_BUS; 2873 ehi->action = ATA_EH_RESET; 2874 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2875 if (qc) 2876 qc->err_mask |= err_mask; 2877 else 2878 ehi->err_mask |= err_mask; 2879 2880 ata_port_freeze(ap); 2881 } 2882 } 2883 return 1; /* handled */ 2884 } 2885 2886 /** 2887 * mv_interrupt - Main interrupt event handler 2888 * @irq: unused 2889 * @dev_instance: private data; in this case the host structure 2890 * 2891 * Read the read only register to determine if any host 2892 * controllers have pending interrupts. If so, call lower level 2893 * routine to handle. Also check for PCI errors which are only 2894 * reported here. 2895 * 2896 * LOCKING: 2897 * This routine holds the host lock while processing pending 2898 * interrupts. 2899 */ 2900 static irqreturn_t mv_interrupt(int irq, void *dev_instance) 2901 { 2902 struct ata_host *host = dev_instance; 2903 struct mv_host_priv *hpriv = host->private_data; 2904 unsigned int handled = 0; 2905 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 2906 u32 main_irq_cause, pending_irqs; 2907 2908 spin_lock(&host->lock); 2909 2910 /* for MSI: block new interrupts while in here */ 2911 if (using_msi) 2912 mv_write_main_irq_mask(0, hpriv); 2913 2914 main_irq_cause = readl(hpriv->main_irq_cause_addr); 2915 pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2916 /* 2917 * Deal with cases where we either have nothing pending, or have read 2918 * a bogus register value which can indicate HW removal or PCI fault. 2919 */ 2920 if (pending_irqs && main_irq_cause != 0xffffffffU) { 2921 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2922 handled = mv_pci_error(host, hpriv->base); 2923 else 2924 handled = mv_host_intr(host, pending_irqs); 2925 } 2926 2927 /* for MSI: unmask; interrupt cause bits will retrigger now */ 2928 if (using_msi) 2929 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 2930 2931 spin_unlock(&host->lock); 2932 2933 return IRQ_RETVAL(handled); 2934 } 2935 2936 static unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2937 { 2938 unsigned int ofs; 2939 2940 switch (sc_reg_in) { 2941 case SCR_STATUS: 2942 case SCR_ERROR: 2943 case SCR_CONTROL: 2944 ofs = sc_reg_in * sizeof(u32); 2945 break; 2946 default: 2947 ofs = 0xffffffffU; 2948 break; 2949 } 2950 return ofs; 2951 } 2952 2953 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 2954 { 2955 struct mv_host_priv *hpriv = link->ap->host->private_data; 2956 void __iomem *mmio = hpriv->base; 2957 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2958 unsigned int ofs = mv5_scr_offset(sc_reg_in); 2959 2960 if (ofs != 0xffffffffU) { 2961 *val = readl(addr + ofs); 2962 return 0; 2963 } else 2964 return -EINVAL; 2965 } 2966 2967 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 2968 { 2969 struct mv_host_priv *hpriv = link->ap->host->private_data; 2970 void __iomem *mmio = hpriv->base; 2971 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2972 unsigned int ofs = mv5_scr_offset(sc_reg_in); 2973 2974 if (ofs != 0xffffffffU) { 2975 writelfl(val, addr + ofs); 2976 return 0; 2977 } else 2978 return -EINVAL; 2979 } 2980 2981 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2982 { 2983 struct pci_dev *pdev = to_pci_dev(host->dev); 2984 int early_5080; 2985 2986 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2987 2988 if (!early_5080) { 2989 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2990 tmp |= (1 << 0); 2991 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2992 } 2993 2994 mv_reset_pci_bus(host, mmio); 2995 } 2996 2997 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2998 { 2999 writel(0x0fcfffff, mmio + FLASH_CTL); 3000 } 3001 3002 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3003 void __iomem *mmio) 3004 { 3005 void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3006 u32 tmp; 3007 3008 tmp = readl(phy_mmio + MV5_PHY_MODE); 3009 3010 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3011 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3012 } 3013 3014 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3015 { 3016 u32 tmp; 3017 3018 writel(0, mmio + GPIO_PORT_CTL); 3019 3020 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3021 3022 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3023 tmp |= ~(1 << 0); 3024 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3025 } 3026 3027 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 3028 unsigned int port) 3029 { 3030 void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3031 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3032 u32 tmp; 3033 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3034 3035 if (fix_apm_sq) { 3036 tmp = readl(phy_mmio + MV5_LTMODE); 3037 tmp |= (1 << 19); 3038 writel(tmp, phy_mmio + MV5_LTMODE); 3039 3040 tmp = readl(phy_mmio + MV5_PHY_CTL); 3041 tmp &= ~0x3; 3042 tmp |= 0x1; 3043 writel(tmp, phy_mmio + MV5_PHY_CTL); 3044 } 3045 3046 tmp = readl(phy_mmio + MV5_PHY_MODE); 3047 tmp &= ~mask; 3048 tmp |= hpriv->signal[port].pre; 3049 tmp |= hpriv->signal[port].amps; 3050 writel(tmp, phy_mmio + MV5_PHY_MODE); 3051 } 3052 3053 3054 #undef ZERO 3055 #define ZERO(reg) writel(0, port_mmio + (reg)) 3056 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3057 unsigned int port) 3058 { 3059 void __iomem *port_mmio = mv_port_base(mmio, port); 3060 3061 mv_reset_channel(hpriv, mmio, port); 3062 3063 ZERO(0x028); /* command */ 3064 writel(0x11f, port_mmio + EDMA_CFG); 3065 ZERO(0x004); /* timer */ 3066 ZERO(0x008); /* irq err cause */ 3067 ZERO(0x00c); /* irq err mask */ 3068 ZERO(0x010); /* rq bah */ 3069 ZERO(0x014); /* rq inp */ 3070 ZERO(0x018); /* rq outp */ 3071 ZERO(0x01c); /* respq bah */ 3072 ZERO(0x024); /* respq outp */ 3073 ZERO(0x020); /* respq inp */ 3074 ZERO(0x02c); /* test control */ 3075 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3076 } 3077 #undef ZERO 3078 3079 #define ZERO(reg) writel(0, hc_mmio + (reg)) 3080 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3081 unsigned int hc) 3082 { 3083 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3084 u32 tmp; 3085 3086 ZERO(0x00c); 3087 ZERO(0x010); 3088 ZERO(0x014); 3089 ZERO(0x018); 3090 3091 tmp = readl(hc_mmio + 0x20); 3092 tmp &= 0x1c1c1c1c; 3093 tmp |= 0x03030303; 3094 writel(tmp, hc_mmio + 0x20); 3095 } 3096 #undef ZERO 3097 3098 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3099 unsigned int n_hc) 3100 { 3101 unsigned int hc, port; 3102 3103 for (hc = 0; hc < n_hc; hc++) { 3104 for (port = 0; port < MV_PORTS_PER_HC; port++) 3105 mv5_reset_hc_port(hpriv, mmio, 3106 (hc * MV_PORTS_PER_HC) + port); 3107 3108 mv5_reset_one_hc(hpriv, mmio, hc); 3109 } 3110 3111 return 0; 3112 } 3113 3114 #undef ZERO 3115 #define ZERO(reg) writel(0, mmio + (reg)) 3116 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3117 { 3118 struct mv_host_priv *hpriv = host->private_data; 3119 u32 tmp; 3120 3121 tmp = readl(mmio + MV_PCI_MODE); 3122 tmp &= 0xff00ffff; 3123 writel(tmp, mmio + MV_PCI_MODE); 3124 3125 ZERO(MV_PCI_DISC_TIMER); 3126 ZERO(MV_PCI_MSI_TRIGGER); 3127 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3128 ZERO(MV_PCI_SERR_MASK); 3129 ZERO(hpriv->irq_cause_offset); 3130 ZERO(hpriv->irq_mask_offset); 3131 ZERO(MV_PCI_ERR_LOW_ADDRESS); 3132 ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3133 ZERO(MV_PCI_ERR_ATTRIBUTE); 3134 ZERO(MV_PCI_ERR_COMMAND); 3135 } 3136 #undef ZERO 3137 3138 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3139 { 3140 u32 tmp; 3141 3142 mv5_reset_flash(hpriv, mmio); 3143 3144 tmp = readl(mmio + GPIO_PORT_CTL); 3145 tmp &= 0x3; 3146 tmp |= (1 << 5) | (1 << 6); 3147 writel(tmp, mmio + GPIO_PORT_CTL); 3148 } 3149 3150 /** 3151 * mv6_reset_hc - Perform the 6xxx global soft reset 3152 * @mmio: base address of the HBA 3153 * 3154 * This routine only applies to 6xxx parts. 3155 * 3156 * LOCKING: 3157 * Inherited from caller. 3158 */ 3159 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3160 unsigned int n_hc) 3161 { 3162 void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3163 int i, rc = 0; 3164 u32 t; 3165 3166 /* Following procedure defined in PCI "main command and status 3167 * register" table. 3168 */ 3169 t = readl(reg); 3170 writel(t | STOP_PCI_MASTER, reg); 3171 3172 for (i = 0; i < 1000; i++) { 3173 udelay(1); 3174 t = readl(reg); 3175 if (PCI_MASTER_EMPTY & t) 3176 break; 3177 } 3178 if (!(PCI_MASTER_EMPTY & t)) { 3179 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3180 rc = 1; 3181 goto done; 3182 } 3183 3184 /* set reset */ 3185 i = 5; 3186 do { 3187 writel(t | GLOB_SFT_RST, reg); 3188 t = readl(reg); 3189 udelay(1); 3190 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3191 3192 if (!(GLOB_SFT_RST & t)) { 3193 printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3194 rc = 1; 3195 goto done; 3196 } 3197 3198 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3199 i = 5; 3200 do { 3201 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3202 t = readl(reg); 3203 udelay(1); 3204 } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3205 3206 if (GLOB_SFT_RST & t) { 3207 printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3208 rc = 1; 3209 } 3210 done: 3211 return rc; 3212 } 3213 3214 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3215 void __iomem *mmio) 3216 { 3217 void __iomem *port_mmio; 3218 u32 tmp; 3219 3220 tmp = readl(mmio + RESET_CFG); 3221 if ((tmp & (1 << 0)) == 0) { 3222 hpriv->signal[idx].amps = 0x7 << 8; 3223 hpriv->signal[idx].pre = 0x1 << 5; 3224 return; 3225 } 3226 3227 port_mmio = mv_port_base(mmio, idx); 3228 tmp = readl(port_mmio + PHY_MODE2); 3229 3230 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3231 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3232 } 3233 3234 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3235 { 3236 writel(0x00000060, mmio + GPIO_PORT_CTL); 3237 } 3238 3239 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 3240 unsigned int port) 3241 { 3242 void __iomem *port_mmio = mv_port_base(mmio, port); 3243 3244 u32 hp_flags = hpriv->hp_flags; 3245 int fix_phy_mode2 = 3246 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3247 int fix_phy_mode4 = 3248 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3249 u32 m2, m3; 3250 3251 if (fix_phy_mode2) { 3252 m2 = readl(port_mmio + PHY_MODE2); 3253 m2 &= ~(1 << 16); 3254 m2 |= (1 << 31); 3255 writel(m2, port_mmio + PHY_MODE2); 3256 3257 udelay(200); 3258 3259 m2 = readl(port_mmio + PHY_MODE2); 3260 m2 &= ~((1 << 16) | (1 << 31)); 3261 writel(m2, port_mmio + PHY_MODE2); 3262 3263 udelay(200); 3264 } 3265 3266 /* 3267 * Gen-II/IIe PHY_MODE3 errata RM#2: 3268 * Achieves better receiver noise performance than the h/w default: 3269 */ 3270 m3 = readl(port_mmio + PHY_MODE3); 3271 m3 = (m3 & 0x1f) | (0x5555601 << 5); 3272 3273 /* Guideline 88F5182 (GL# SATA-S11) */ 3274 if (IS_SOC(hpriv)) 3275 m3 &= ~0x1c; 3276 3277 if (fix_phy_mode4) { 3278 u32 m4 = readl(port_mmio + PHY_MODE4); 3279 /* 3280 * Enforce reserved-bit restrictions on GenIIe devices only. 3281 * For earlier chipsets, force only the internal config field 3282 * (workaround for errata FEr SATA#10 part 1). 3283 */ 3284 if (IS_GEN_IIE(hpriv)) 3285 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3286 else 3287 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 3288 writel(m4, port_mmio + PHY_MODE4); 3289 } 3290 /* 3291 * Workaround for 60x1-B2 errata SATA#13: 3292 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3293 * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3294 * Or ensure we use writelfl() when writing PHY_MODE4. 3295 */ 3296 writel(m3, port_mmio + PHY_MODE3); 3297 3298 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3299 m2 = readl(port_mmio + PHY_MODE2); 3300 3301 m2 &= ~MV_M2_PREAMP_MASK; 3302 m2 |= hpriv->signal[port].amps; 3303 m2 |= hpriv->signal[port].pre; 3304 m2 &= ~(1 << 16); 3305 3306 /* according to mvSata 3.6.1, some IIE values are fixed */ 3307 if (IS_GEN_IIE(hpriv)) { 3308 m2 &= ~0xC30FF01F; 3309 m2 |= 0x0000900F; 3310 } 3311 3312 writel(m2, port_mmio + PHY_MODE2); 3313 } 3314 3315 /* TODO: use the generic LED interface to configure the SATA Presence */ 3316 /* & Acitivy LEDs on the board */ 3317 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3318 void __iomem *mmio) 3319 { 3320 return; 3321 } 3322 3323 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3324 void __iomem *mmio) 3325 { 3326 void __iomem *port_mmio; 3327 u32 tmp; 3328 3329 port_mmio = mv_port_base(mmio, idx); 3330 tmp = readl(port_mmio + PHY_MODE2); 3331 3332 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3333 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3334 } 3335 3336 #undef ZERO 3337 #define ZERO(reg) writel(0, port_mmio + (reg)) 3338 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3339 void __iomem *mmio, unsigned int port) 3340 { 3341 void __iomem *port_mmio = mv_port_base(mmio, port); 3342 3343 mv_reset_channel(hpriv, mmio, port); 3344 3345 ZERO(0x028); /* command */ 3346 writel(0x101f, port_mmio + EDMA_CFG); 3347 ZERO(0x004); /* timer */ 3348 ZERO(0x008); /* irq err cause */ 3349 ZERO(0x00c); /* irq err mask */ 3350 ZERO(0x010); /* rq bah */ 3351 ZERO(0x014); /* rq inp */ 3352 ZERO(0x018); /* rq outp */ 3353 ZERO(0x01c); /* respq bah */ 3354 ZERO(0x024); /* respq outp */ 3355 ZERO(0x020); /* respq inp */ 3356 ZERO(0x02c); /* test control */ 3357 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3358 } 3359 3360 #undef ZERO 3361 3362 #define ZERO(reg) writel(0, hc_mmio + (reg)) 3363 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3364 void __iomem *mmio) 3365 { 3366 void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3367 3368 ZERO(0x00c); 3369 ZERO(0x010); 3370 ZERO(0x014); 3371 3372 } 3373 3374 #undef ZERO 3375 3376 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3377 void __iomem *mmio, unsigned int n_hc) 3378 { 3379 unsigned int port; 3380 3381 for (port = 0; port < hpriv->n_ports; port++) 3382 mv_soc_reset_hc_port(hpriv, mmio, port); 3383 3384 mv_soc_reset_one_hc(hpriv, mmio); 3385 3386 return 0; 3387 } 3388 3389 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3390 void __iomem *mmio) 3391 { 3392 return; 3393 } 3394 3395 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3396 { 3397 return; 3398 } 3399 3400 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3401 { 3402 u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3403 3404 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3405 if (want_gen2i) 3406 ifcfg |= (1 << 7); /* enable gen2i speed */ 3407 writelfl(ifcfg, port_mmio + SATA_IFCFG); 3408 } 3409 3410 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3411 unsigned int port_no) 3412 { 3413 void __iomem *port_mmio = mv_port_base(mmio, port_no); 3414 3415 /* 3416 * The datasheet warns against setting EDMA_RESET when EDMA is active 3417 * (but doesn't say what the problem might be). So we first try 3418 * to disable the EDMA engine before doing the EDMA_RESET operation. 3419 */ 3420 mv_stop_edma_engine(port_mmio); 3421 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3422 3423 if (!IS_GEN_I(hpriv)) { 3424 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 3425 mv_setup_ifcfg(port_mmio, 1); 3426 } 3427 /* 3428 * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3429 * link, and physical layers. It resets all SATA interface registers 3430 * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3431 */ 3432 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3433 udelay(25); /* allow reset propagation */ 3434 writelfl(0, port_mmio + EDMA_CMD); 3435 3436 hpriv->ops->phy_errata(hpriv, mmio, port_no); 3437 3438 if (IS_GEN_I(hpriv)) 3439 mdelay(1); 3440 } 3441 3442 static void mv_pmp_select(struct ata_port *ap, int pmp) 3443 { 3444 if (sata_pmp_supported(ap)) { 3445 void __iomem *port_mmio = mv_ap_base(ap); 3446 u32 reg = readl(port_mmio + SATA_IFCTL); 3447 int old = reg & 0xf; 3448 3449 if (old != pmp) { 3450 reg = (reg & ~0xf) | pmp; 3451 writelfl(reg, port_mmio + SATA_IFCTL); 3452 } 3453 } 3454 } 3455 3456 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3457 unsigned long deadline) 3458 { 3459 mv_pmp_select(link->ap, sata_srst_pmp(link)); 3460 return sata_std_hardreset(link, class, deadline); 3461 } 3462 3463 static int mv_softreset(struct ata_link *link, unsigned int *class, 3464 unsigned long deadline) 3465 { 3466 mv_pmp_select(link->ap, sata_srst_pmp(link)); 3467 return ata_sff_softreset(link, class, deadline); 3468 } 3469 3470 static int mv_hardreset(struct ata_link *link, unsigned int *class, 3471 unsigned long deadline) 3472 { 3473 struct ata_port *ap = link->ap; 3474 struct mv_host_priv *hpriv = ap->host->private_data; 3475 struct mv_port_priv *pp = ap->private_data; 3476 void __iomem *mmio = hpriv->base; 3477 int rc, attempts = 0, extra = 0; 3478 u32 sstatus; 3479 bool online; 3480 3481 mv_reset_channel(hpriv, mmio, ap->port_no); 3482 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3483 pp->pp_flags &= 3484 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3485 3486 /* Workaround for errata FEr SATA#10 (part 2) */ 3487 do { 3488 const unsigned long *timing = 3489 sata_ehc_deb_timing(&link->eh_context); 3490 3491 rc = sata_link_hardreset(link, timing, deadline + extra, 3492 &online, NULL); 3493 rc = online ? -EAGAIN : rc; 3494 if (rc) 3495 return rc; 3496 sata_scr_read(link, SCR_STATUS, &sstatus); 3497 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 3498 /* Force 1.5gb/s link speed and try again */ 3499 mv_setup_ifcfg(mv_ap_base(ap), 0); 3500 if (time_after(jiffies + HZ, deadline)) 3501 extra = HZ; /* only extend it once, max */ 3502 } 3503 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 3504 mv_save_cached_regs(ap); 3505 mv_edma_cfg(ap, 0, 0); 3506 3507 return rc; 3508 } 3509 3510 static void mv_eh_freeze(struct ata_port *ap) 3511 { 3512 mv_stop_edma(ap); 3513 mv_enable_port_irqs(ap, 0); 3514 } 3515 3516 static void mv_eh_thaw(struct ata_port *ap) 3517 { 3518 struct mv_host_priv *hpriv = ap->host->private_data; 3519 unsigned int port = ap->port_no; 3520 unsigned int hardport = mv_hardport_from_port(port); 3521 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3522 void __iomem *port_mmio = mv_ap_base(ap); 3523 u32 hc_irq_cause; 3524 3525 /* clear EDMA errors on this port */ 3526 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3527 3528 /* clear pending irq events */ 3529 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3530 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3531 3532 mv_enable_port_irqs(ap, ERR_IRQ); 3533 } 3534 3535 /** 3536 * mv_port_init - Perform some early initialization on a single port. 3537 * @port: libata data structure storing shadow register addresses 3538 * @port_mmio: base address of the port 3539 * 3540 * Initialize shadow register mmio addresses, clear outstanding 3541 * interrupts on the port, and unmask interrupts for the future 3542 * start of the port. 3543 * 3544 * LOCKING: 3545 * Inherited from caller. 3546 */ 3547 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 3548 { 3549 void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 3550 3551 /* PIO related setup 3552 */ 3553 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 3554 port->error_addr = 3555 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 3556 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 3557 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 3558 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 3559 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 3560 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 3561 port->status_addr = 3562 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 3563 /* special case: control/altstatus doesn't have ATA_REG_ address */ 3564 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 3565 3566 /* unused: */ 3567 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 3568 3569 /* Clear any currently outstanding port interrupt conditions */ 3570 serr = port_mmio + mv_scr_offset(SCR_ERROR); 3571 writelfl(readl(serr), serr); 3572 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3573 3574 /* unmask all non-transient EDMA error interrupts */ 3575 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 3576 3577 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 3578 readl(port_mmio + EDMA_CFG), 3579 readl(port_mmio + EDMA_ERR_IRQ_CAUSE), 3580 readl(port_mmio + EDMA_ERR_IRQ_MASK)); 3581 } 3582 3583 static unsigned int mv_in_pcix_mode(struct ata_host *host) 3584 { 3585 struct mv_host_priv *hpriv = host->private_data; 3586 void __iomem *mmio = hpriv->base; 3587 u32 reg; 3588 3589 if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3590 return 0; /* not PCI-X capable */ 3591 reg = readl(mmio + MV_PCI_MODE); 3592 if ((reg & MV_PCI_MODE_MASK) == 0) 3593 return 0; /* conventional PCI mode */ 3594 return 1; /* chip is in PCI-X mode */ 3595 } 3596 3597 static int mv_pci_cut_through_okay(struct ata_host *host) 3598 { 3599 struct mv_host_priv *hpriv = host->private_data; 3600 void __iomem *mmio = hpriv->base; 3601 u32 reg; 3602 3603 if (!mv_in_pcix_mode(host)) { 3604 reg = readl(mmio + MV_PCI_COMMAND); 3605 if (reg & MV_PCI_COMMAND_MRDTRIG) 3606 return 0; /* not okay */ 3607 } 3608 return 1; /* okay */ 3609 } 3610 3611 static void mv_60x1b2_errata_pci7(struct ata_host *host) 3612 { 3613 struct mv_host_priv *hpriv = host->private_data; 3614 void __iomem *mmio = hpriv->base; 3615 3616 /* workaround for 60x1-B2 errata PCI#7 */ 3617 if (mv_in_pcix_mode(host)) { 3618 u32 reg = readl(mmio + MV_PCI_COMMAND); 3619 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 3620 } 3621 } 3622 3623 static int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3624 { 3625 struct pci_dev *pdev = to_pci_dev(host->dev); 3626 struct mv_host_priv *hpriv = host->private_data; 3627 u32 hp_flags = hpriv->hp_flags; 3628 3629 switch (board_idx) { 3630 case chip_5080: 3631 hpriv->ops = &mv5xxx_ops; 3632 hp_flags |= MV_HP_GEN_I; 3633 3634 switch (pdev->revision) { 3635 case 0x1: 3636 hp_flags |= MV_HP_ERRATA_50XXB0; 3637 break; 3638 case 0x3: 3639 hp_flags |= MV_HP_ERRATA_50XXB2; 3640 break; 3641 default: 3642 dev_printk(KERN_WARNING, &pdev->dev, 3643 "Applying 50XXB2 workarounds to unknown rev\n"); 3644 hp_flags |= MV_HP_ERRATA_50XXB2; 3645 break; 3646 } 3647 break; 3648 3649 case chip_504x: 3650 case chip_508x: 3651 hpriv->ops = &mv5xxx_ops; 3652 hp_flags |= MV_HP_GEN_I; 3653 3654 switch (pdev->revision) { 3655 case 0x0: 3656 hp_flags |= MV_HP_ERRATA_50XXB0; 3657 break; 3658 case 0x3: 3659 hp_flags |= MV_HP_ERRATA_50XXB2; 3660 break; 3661 default: 3662 dev_printk(KERN_WARNING, &pdev->dev, 3663 "Applying B2 workarounds to unknown rev\n"); 3664 hp_flags |= MV_HP_ERRATA_50XXB2; 3665 break; 3666 } 3667 break; 3668 3669 case chip_604x: 3670 case chip_608x: 3671 hpriv->ops = &mv6xxx_ops; 3672 hp_flags |= MV_HP_GEN_II; 3673 3674 switch (pdev->revision) { 3675 case 0x7: 3676 mv_60x1b2_errata_pci7(host); 3677 hp_flags |= MV_HP_ERRATA_60X1B2; 3678 break; 3679 case 0x9: 3680 hp_flags |= MV_HP_ERRATA_60X1C0; 3681 break; 3682 default: 3683 dev_printk(KERN_WARNING, &pdev->dev, 3684 "Applying B2 workarounds to unknown rev\n"); 3685 hp_flags |= MV_HP_ERRATA_60X1B2; 3686 break; 3687 } 3688 break; 3689 3690 case chip_7042: 3691 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3692 if (pdev->vendor == PCI_VENDOR_ID_TTI && 3693 (pdev->device == 0x2300 || pdev->device == 0x2310)) 3694 { 3695 /* 3696 * Highpoint RocketRAID PCIe 23xx series cards: 3697 * 3698 * Unconfigured drives are treated as "Legacy" 3699 * by the BIOS, and it overwrites sector 8 with 3700 * a "Lgcy" metadata block prior to Linux boot. 3701 * 3702 * Configured drives (RAID or JBOD) leave sector 8 3703 * alone, but instead overwrite a high numbered 3704 * sector for the RAID metadata. This sector can 3705 * be determined exactly, by truncating the physical 3706 * drive capacity to a nice even GB value. 3707 * 3708 * RAID metadata is at: (dev->n_sectors & ~0xfffff) 3709 * 3710 * Warn the user, lest they think we're just buggy. 3711 */ 3712 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 3713 " BIOS CORRUPTS DATA on all attached drives," 3714 " regardless of if/how they are configured." 3715 " BEWARE!\n"); 3716 printk(KERN_WARNING DRV_NAME ": For data safety, do not" 3717 " use sectors 8-9 on \"Legacy\" drives," 3718 " and avoid the final two gigabytes on" 3719 " all RocketRAID BIOS initialized drives.\n"); 3720 } 3721 /* drop through */ 3722 case chip_6042: 3723 hpriv->ops = &mv6xxx_ops; 3724 hp_flags |= MV_HP_GEN_IIE; 3725 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3726 hp_flags |= MV_HP_CUT_THROUGH; 3727 3728 switch (pdev->revision) { 3729 case 0x2: /* Rev.B0: the first/only public release */ 3730 hp_flags |= MV_HP_ERRATA_60X1C0; 3731 break; 3732 default: 3733 dev_printk(KERN_WARNING, &pdev->dev, 3734 "Applying 60X1C0 workarounds to unknown rev\n"); 3735 hp_flags |= MV_HP_ERRATA_60X1C0; 3736 break; 3737 } 3738 break; 3739 case chip_soc: 3740 hpriv->ops = &mv_soc_ops; 3741 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3742 MV_HP_ERRATA_60X1C0; 3743 break; 3744 3745 default: 3746 dev_printk(KERN_ERR, host->dev, 3747 "BUG: invalid board index %u\n", board_idx); 3748 return 1; 3749 } 3750 3751 hpriv->hp_flags = hp_flags; 3752 if (hp_flags & MV_HP_PCIE) { 3753 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3754 hpriv->irq_mask_offset = PCIE_IRQ_MASK; 3755 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 3756 } else { 3757 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3758 hpriv->irq_mask_offset = PCI_IRQ_MASK; 3759 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 3760 } 3761 3762 return 0; 3763 } 3764 3765 /** 3766 * mv_init_host - Perform some early initialization of the host. 3767 * @host: ATA host to initialize 3768 * @board_idx: controller index 3769 * 3770 * If possible, do an early global reset of the host. Then do 3771 * our port init and clear/unmask all/relevant host interrupts. 3772 * 3773 * LOCKING: 3774 * Inherited from caller. 3775 */ 3776 static int mv_init_host(struct ata_host *host, unsigned int board_idx) 3777 { 3778 int rc = 0, n_hc, port, hc; 3779 struct mv_host_priv *hpriv = host->private_data; 3780 void __iomem *mmio = hpriv->base; 3781 3782 rc = mv_chip_id(host, board_idx); 3783 if (rc) 3784 goto done; 3785 3786 if (IS_SOC(hpriv)) { 3787 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3788 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 3789 } else { 3790 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3791 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3792 } 3793 3794 /* initialize shadow irq mask with register's value */ 3795 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 3796 3797 /* global interrupt mask: 0 == mask everything */ 3798 mv_set_main_irq_mask(host, ~0, 0); 3799 3800 n_hc = mv_get_hc_count(host->ports[0]->flags); 3801 3802 for (port = 0; port < host->n_ports; port++) 3803 hpriv->ops->read_preamp(hpriv, port, mmio); 3804 3805 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 3806 if (rc) 3807 goto done; 3808 3809 hpriv->ops->reset_flash(hpriv, mmio); 3810 hpriv->ops->reset_bus(host, mmio); 3811 hpriv->ops->enable_leds(hpriv, mmio); 3812 3813 for (port = 0; port < host->n_ports; port++) { 3814 struct ata_port *ap = host->ports[port]; 3815 void __iomem *port_mmio = mv_port_base(mmio, port); 3816 3817 mv_port_init(&ap->ioaddr, port_mmio); 3818 3819 #ifdef CONFIG_PCI 3820 if (!IS_SOC(hpriv)) { 3821 unsigned int offset = port_mmio - mmio; 3822 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3823 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3824 } 3825 #endif 3826 } 3827 3828 for (hc = 0; hc < n_hc; hc++) { 3829 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3830 3831 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 3832 "(before clear)=0x%08x\n", hc, 3833 readl(hc_mmio + HC_CFG), 3834 readl(hc_mmio + HC_IRQ_CAUSE)); 3835 3836 /* Clear any currently outstanding hc interrupt conditions */ 3837 writelfl(0, hc_mmio + HC_IRQ_CAUSE); 3838 } 3839 3840 if (!IS_SOC(hpriv)) { 3841 /* Clear any currently outstanding host interrupt conditions */ 3842 writelfl(0, mmio + hpriv->irq_cause_offset); 3843 3844 /* and unmask interrupt generation for host regs */ 3845 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 3846 } 3847 3848 /* 3849 * enable only global host interrupts for now. 3850 * The per-port interrupts get done later as ports are set up. 3851 */ 3852 mv_set_main_irq_mask(host, 0, PCI_ERR); 3853 mv_set_irq_coalescing(host, irq_coalescing_io_count, 3854 irq_coalescing_usecs); 3855 done: 3856 return rc; 3857 } 3858 3859 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3860 { 3861 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3862 MV_CRQB_Q_SZ, 0); 3863 if (!hpriv->crqb_pool) 3864 return -ENOMEM; 3865 3866 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3867 MV_CRPB_Q_SZ, 0); 3868 if (!hpriv->crpb_pool) 3869 return -ENOMEM; 3870 3871 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3872 MV_SG_TBL_SZ, 0); 3873 if (!hpriv->sg_tbl_pool) 3874 return -ENOMEM; 3875 3876 return 0; 3877 } 3878 3879 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 3880 struct mbus_dram_target_info *dram) 3881 { 3882 int i; 3883 3884 for (i = 0; i < 4; i++) { 3885 writel(0, hpriv->base + WINDOW_CTRL(i)); 3886 writel(0, hpriv->base + WINDOW_BASE(i)); 3887 } 3888 3889 for (i = 0; i < dram->num_cs; i++) { 3890 struct mbus_dram_window *cs = dram->cs + i; 3891 3892 writel(((cs->size - 1) & 0xffff0000) | 3893 (cs->mbus_attr << 8) | 3894 (dram->mbus_dram_target_id << 4) | 1, 3895 hpriv->base + WINDOW_CTRL(i)); 3896 writel(cs->base, hpriv->base + WINDOW_BASE(i)); 3897 } 3898 } 3899 3900 /** 3901 * mv_platform_probe - handle a positive probe of an soc Marvell 3902 * host 3903 * @pdev: platform device found 3904 * 3905 * LOCKING: 3906 * Inherited from caller. 3907 */ 3908 static int mv_platform_probe(struct platform_device *pdev) 3909 { 3910 static int printed_version; 3911 const struct mv_sata_platform_data *mv_platform_data; 3912 const struct ata_port_info *ppi[] = 3913 { &mv_port_info[chip_soc], NULL }; 3914 struct ata_host *host; 3915 struct mv_host_priv *hpriv; 3916 struct resource *res; 3917 int n_ports, rc; 3918 3919 if (!printed_version++) 3920 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3921 3922 /* 3923 * Simple resource validation .. 3924 */ 3925 if (unlikely(pdev->num_resources != 2)) { 3926 dev_err(&pdev->dev, "invalid number of resources\n"); 3927 return -EINVAL; 3928 } 3929 3930 /* 3931 * Get the register base first 3932 */ 3933 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3934 if (res == NULL) 3935 return -EINVAL; 3936 3937 /* allocate host */ 3938 mv_platform_data = pdev->dev.platform_data; 3939 n_ports = mv_platform_data->n_ports; 3940 3941 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3942 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3943 3944 if (!host || !hpriv) 3945 return -ENOMEM; 3946 host->private_data = hpriv; 3947 hpriv->n_ports = n_ports; 3948 3949 host->iomap = NULL; 3950 hpriv->base = devm_ioremap(&pdev->dev, res->start, 3951 res->end - res->start + 1); 3952 hpriv->base -= SATAHC0_REG_BASE; 3953 3954 /* 3955 * (Re-)program MBUS remapping windows if we are asked to. 3956 */ 3957 if (mv_platform_data->dram != NULL) 3958 mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 3959 3960 rc = mv_create_dma_pools(hpriv, &pdev->dev); 3961 if (rc) 3962 return rc; 3963 3964 /* initialize adapter */ 3965 rc = mv_init_host(host, chip_soc); 3966 if (rc) 3967 return rc; 3968 3969 dev_printk(KERN_INFO, &pdev->dev, 3970 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3971 host->n_ports); 3972 3973 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3974 IRQF_SHARED, &mv6_sht); 3975 } 3976 3977 /* 3978 * 3979 * mv_platform_remove - unplug a platform interface 3980 * @pdev: platform device 3981 * 3982 * A platform bus SATA device has been unplugged. Perform the needed 3983 * cleanup. Also called on module unload for any active devices. 3984 */ 3985 static int __devexit mv_platform_remove(struct platform_device *pdev) 3986 { 3987 struct device *dev = &pdev->dev; 3988 struct ata_host *host = dev_get_drvdata(dev); 3989 3990 ata_host_detach(host); 3991 return 0; 3992 } 3993 3994 static struct platform_driver mv_platform_driver = { 3995 .probe = mv_platform_probe, 3996 .remove = __devexit_p(mv_platform_remove), 3997 .driver = { 3998 .name = DRV_NAME, 3999 .owner = THIS_MODULE, 4000 }, 4001 }; 4002 4003 4004 #ifdef CONFIG_PCI 4005 static int mv_pci_init_one(struct pci_dev *pdev, 4006 const struct pci_device_id *ent); 4007 4008 4009 static struct pci_driver mv_pci_driver = { 4010 .name = DRV_NAME, 4011 .id_table = mv_pci_tbl, 4012 .probe = mv_pci_init_one, 4013 .remove = ata_pci_remove_one, 4014 }; 4015 4016 /* move to PCI layer or libata core? */ 4017 static int pci_go_64(struct pci_dev *pdev) 4018 { 4019 int rc; 4020 4021 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 4022 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4023 if (rc) { 4024 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 4025 if (rc) { 4026 dev_printk(KERN_ERR, &pdev->dev, 4027 "64-bit DMA enable failed\n"); 4028 return rc; 4029 } 4030 } 4031 } else { 4032 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4033 if (rc) { 4034 dev_printk(KERN_ERR, &pdev->dev, 4035 "32-bit DMA enable failed\n"); 4036 return rc; 4037 } 4038 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 4039 if (rc) { 4040 dev_printk(KERN_ERR, &pdev->dev, 4041 "32-bit consistent DMA enable failed\n"); 4042 return rc; 4043 } 4044 } 4045 4046 return rc; 4047 } 4048 4049 /** 4050 * mv_print_info - Dump key info to kernel log for perusal. 4051 * @host: ATA host to print info about 4052 * 4053 * FIXME: complete this. 4054 * 4055 * LOCKING: 4056 * Inherited from caller. 4057 */ 4058 static void mv_print_info(struct ata_host *host) 4059 { 4060 struct pci_dev *pdev = to_pci_dev(host->dev); 4061 struct mv_host_priv *hpriv = host->private_data; 4062 u8 scc; 4063 const char *scc_s, *gen; 4064 4065 /* Use this to determine the HW stepping of the chip so we know 4066 * what errata to workaround 4067 */ 4068 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 4069 if (scc == 0) 4070 scc_s = "SCSI"; 4071 else if (scc == 0x01) 4072 scc_s = "RAID"; 4073 else 4074 scc_s = "?"; 4075 4076 if (IS_GEN_I(hpriv)) 4077 gen = "I"; 4078 else if (IS_GEN_II(hpriv)) 4079 gen = "II"; 4080 else if (IS_GEN_IIE(hpriv)) 4081 gen = "IIE"; 4082 else 4083 gen = "?"; 4084 4085 dev_printk(KERN_INFO, &pdev->dev, 4086 "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4087 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 4088 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 4089 } 4090 4091 /** 4092 * mv_pci_init_one - handle a positive probe of a PCI Marvell host 4093 * @pdev: PCI device found 4094 * @ent: PCI device ID entry for the matched host 4095 * 4096 * LOCKING: 4097 * Inherited from caller. 4098 */ 4099 static int mv_pci_init_one(struct pci_dev *pdev, 4100 const struct pci_device_id *ent) 4101 { 4102 static int printed_version; 4103 unsigned int board_idx = (unsigned int)ent->driver_data; 4104 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 4105 struct ata_host *host; 4106 struct mv_host_priv *hpriv; 4107 int n_ports, rc; 4108 4109 if (!printed_version++) 4110 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 4111 4112 /* allocate host */ 4113 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 4114 4115 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4116 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4117 if (!host || !hpriv) 4118 return -ENOMEM; 4119 host->private_data = hpriv; 4120 hpriv->n_ports = n_ports; 4121 4122 /* acquire resources */ 4123 rc = pcim_enable_device(pdev); 4124 if (rc) 4125 return rc; 4126 4127 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 4128 if (rc == -EBUSY) 4129 pcim_pin_device(pdev); 4130 if (rc) 4131 return rc; 4132 host->iomap = pcim_iomap_table(pdev); 4133 hpriv->base = host->iomap[MV_PRIMARY_BAR]; 4134 4135 rc = pci_go_64(pdev); 4136 if (rc) 4137 return rc; 4138 4139 rc = mv_create_dma_pools(hpriv, &pdev->dev); 4140 if (rc) 4141 return rc; 4142 4143 /* initialize adapter */ 4144 rc = mv_init_host(host, board_idx); 4145 if (rc) 4146 return rc; 4147 4148 /* Enable message-switched interrupts, if requested */ 4149 if (msi && pci_enable_msi(pdev) == 0) 4150 hpriv->hp_flags |= MV_HP_FLAG_MSI; 4151 4152 mv_dump_pci_cfg(pdev, 0x68); 4153 mv_print_info(host); 4154 4155 pci_set_master(pdev); 4156 pci_try_set_mwi(pdev); 4157 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4158 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 4159 } 4160 #endif 4161 4162 static int mv_platform_probe(struct platform_device *pdev); 4163 static int __devexit mv_platform_remove(struct platform_device *pdev); 4164 4165 static int __init mv_init(void) 4166 { 4167 int rc = -ENODEV; 4168 #ifdef CONFIG_PCI 4169 rc = pci_register_driver(&mv_pci_driver); 4170 if (rc < 0) 4171 return rc; 4172 #endif 4173 rc = platform_driver_register(&mv_platform_driver); 4174 4175 #ifdef CONFIG_PCI 4176 if (rc < 0) 4177 pci_unregister_driver(&mv_pci_driver); 4178 #endif 4179 return rc; 4180 } 4181 4182 static void __exit mv_exit(void) 4183 { 4184 #ifdef CONFIG_PCI 4185 pci_unregister_driver(&mv_pci_driver); 4186 #endif 4187 platform_driver_unregister(&mv_platform_driver); 4188 } 4189 4190 MODULE_AUTHOR("Brett Russ"); 4191 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 4192 MODULE_LICENSE("GPL"); 4193 MODULE_DEVICE_TABLE(pci, mv_pci_tbl); 4194 MODULE_VERSION(DRV_VERSION); 4195 MODULE_ALIAS("platform:" DRV_NAME); 4196 4197 module_init(mv_init); 4198 module_exit(mv_exit); 4199