1 /* 2 * sata_mv.c - Marvell SATA support 3 * 4 * Copyright 2008: Marvell Corporation, all rights reserved. 5 * Copyright 2005: EMC Corporation, all rights reserved. 6 * Copyright 2005 Red Hat, Inc. All rights reserved. 7 * 8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 25 /* 26 * sata_mv TODO list: 27 * 28 * --> Errata workaround for NCQ device errors. 29 * 30 * --> More errata workarounds for PCI-X. 31 * 32 * --> Complete a full errata audit for all chipsets to identify others. 33 * 34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it). 35 * 36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI). 37 * 38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead. 39 * 40 * --> Develop a low-power-consumption strategy, and implement it. 41 * 42 * --> [Experiment, low priority] Investigate interrupt coalescing. 43 * Quite often, especially with PCI Message Signalled Interrupts (MSI), 44 * the overhead reduced by interrupt mitigation is quite often not 45 * worth the latency cost. 46 * 47 * --> [Experiment, Marvell value added] Is it possible to use target 48 * mode to cross-connect two Linux boxes with Marvell cards? If so, 49 * creating LibATA target mode support would be very interesting. 50 * 51 * Target mode, for those without docs, is the ability to directly 52 * connect two SATA ports. 53 */ 54 55 #include <linux/kernel.h> 56 #include <linux/module.h> 57 #include <linux/pci.h> 58 #include <linux/init.h> 59 #include <linux/blkdev.h> 60 #include <linux/delay.h> 61 #include <linux/interrupt.h> 62 #include <linux/dmapool.h> 63 #include <linux/dma-mapping.h> 64 #include <linux/device.h> 65 #include <linux/platform_device.h> 66 #include <linux/ata_platform.h> 67 #include <linux/mbus.h> 68 #include <linux/bitops.h> 69 #include <scsi/scsi_host.h> 70 #include <scsi/scsi_cmnd.h> 71 #include <scsi/scsi_device.h> 72 #include <linux/libata.h> 73 74 #define DRV_NAME "sata_mv" 75 #define DRV_VERSION "1.24" 76 77 enum { 78 /* BAR's are enumerated in terms of pci_resource_start() terms */ 79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 80 MV_IO_BAR = 2, /* offset 0x18: IO space */ 81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 82 83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 85 86 MV_PCI_REG_BASE = 0, 87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 93 94 MV_SATAHC0_REG_BASE = 0x20000, 95 MV_FLASH_CTL_OFS = 0x1046c, 96 MV_GPIO_PORT_CTL_OFS = 0x104f0, 97 MV_RESET_CFG_OFS = 0x180d8, 98 99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 103 104 MV_MAX_Q_DEPTH = 32, 105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 106 107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB 108 * CRPB needs alignment on a 256B boundary. Size == 256B 109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 110 */ 111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 113 MV_MAX_SG_CT = 256, 114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 115 116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 117 MV_PORT_HC_SHIFT = 2, 118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 121 122 /* Host Flags */ 123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 125 126 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 127 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 128 ATA_FLAG_PIO_POLLING, 129 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 131 132 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 133 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 134 ATA_FLAG_NCQ | ATA_FLAG_AN, 135 136 CRQB_FLAG_READ = (1 << 0), 137 CRQB_TAG_SHIFT = 1, 138 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 139 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 140 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 141 CRQB_CMD_ADDR_SHIFT = 8, 142 CRQB_CMD_CS = (0x2 << 11), 143 CRQB_CMD_LAST = (1 << 15), 144 145 CRPB_FLAG_STATUS_SHIFT = 8, 146 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 147 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 148 149 EPRD_FLAG_END_OF_TBL = (1 << 31), 150 151 /* PCI interface registers */ 152 153 PCI_COMMAND_OFS = 0xc00, 154 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 155 156 PCI_MAIN_CMD_STS_OFS = 0xd30, 157 STOP_PCI_MASTER = (1 << 2), 158 PCI_MASTER_EMPTY = (1 << 3), 159 GLOB_SFT_RST = (1 << 4), 160 161 MV_PCI_MODE_OFS = 0xd00, 162 MV_PCI_MODE_MASK = 0x30, 163 164 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 165 MV_PCI_DISC_TIMER = 0xd04, 166 MV_PCI_MSI_TRIGGER = 0xc38, 167 MV_PCI_SERR_MASK = 0xc28, 168 MV_PCI_XBAR_TMOUT_OFS = 0x1d04, 169 MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 170 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 171 MV_PCI_ERR_ATTRIBUTE = 0x1d48, 172 MV_PCI_ERR_COMMAND = 0x1d50, 173 174 PCI_IRQ_CAUSE_OFS = 0x1d58, 175 PCI_IRQ_MASK_OFS = 0x1d5c, 176 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 177 178 PCIE_IRQ_CAUSE_OFS = 0x1900, 179 PCIE_IRQ_MASK_OFS = 0x1910, 180 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 181 182 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 183 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 184 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, 185 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, 186 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, 187 ERR_IRQ = (1 << 0), /* shift by port # */ 188 DONE_IRQ = (1 << 1), /* shift by port # */ 189 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 190 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 191 PCI_ERR = (1 << 18), 192 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 193 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 194 PORTS_0_3_COAL_DONE = (1 << 8), 195 PORTS_4_7_COAL_DONE = (1 << 17), 196 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 197 GPIO_INT = (1 << 22), 198 SELF_INT = (1 << 23), 199 TWSI_INT = (1 << 24), 200 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 201 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 202 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 203 204 /* SATAHC registers */ 205 HC_CFG_OFS = 0, 206 207 HC_IRQ_CAUSE_OFS = 0x14, 208 DMA_IRQ = (1 << 0), /* shift by port # */ 209 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 210 DEV_IRQ = (1 << 8), /* shift by port # */ 211 212 /* Shadow block registers */ 213 SHD_BLK_OFS = 0x100, 214 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 215 216 /* SATA registers */ 217 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 218 SATA_ACTIVE_OFS = 0x350, 219 SATA_FIS_IRQ_CAUSE_OFS = 0x364, 220 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */ 221 222 LTMODE_OFS = 0x30c, 223 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 224 225 PHY_MODE3 = 0x310, 226 PHY_MODE4 = 0x314, 227 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 228 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 229 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 230 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 231 232 PHY_MODE2 = 0x330, 233 SATA_IFCTL_OFS = 0x344, 234 SATA_TESTCTL_OFS = 0x348, 235 SATA_IFSTAT_OFS = 0x34c, 236 VENDOR_UNIQUE_FIS_OFS = 0x35c, 237 238 FISCFG_OFS = 0x360, 239 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 240 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 241 242 MV5_PHY_MODE = 0x74, 243 MV5_LTMODE_OFS = 0x30, 244 MV5_PHY_CTL_OFS = 0x0C, 245 SATA_INTERFACE_CFG_OFS = 0x050, 246 247 MV_M2_PREAMP_MASK = 0x7e0, 248 249 /* Port registers */ 250 EDMA_CFG_OFS = 0, 251 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 252 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 253 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 254 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 255 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 256 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 257 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 258 259 EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 260 EDMA_ERR_IRQ_MASK_OFS = 0xc, 261 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 262 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 263 EDMA_ERR_DEV = (1 << 2), /* device error */ 264 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 265 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 266 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 267 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 268 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 269 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 270 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 271 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 272 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 273 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 274 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 275 276 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 277 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 278 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 279 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 280 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 281 282 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 283 284 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 285 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 286 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 287 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 288 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 289 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 290 291 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 292 293 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 294 EDMA_ERR_OVERRUN_5 = (1 << 5), 295 EDMA_ERR_UNDERRUN_5 = (1 << 6), 296 297 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 298 EDMA_ERR_LNK_CTRL_RX_1 | 299 EDMA_ERR_LNK_CTRL_RX_3 | 300 EDMA_ERR_LNK_CTRL_TX, 301 302 EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 303 EDMA_ERR_PRD_PAR | 304 EDMA_ERR_DEV_DCON | 305 EDMA_ERR_DEV_CON | 306 EDMA_ERR_SERR | 307 EDMA_ERR_SELF_DIS | 308 EDMA_ERR_CRQB_PAR | 309 EDMA_ERR_CRPB_PAR | 310 EDMA_ERR_INTRL_PAR | 311 EDMA_ERR_IORDY | 312 EDMA_ERR_LNK_CTRL_RX_2 | 313 EDMA_ERR_LNK_DATA_RX | 314 EDMA_ERR_LNK_DATA_TX | 315 EDMA_ERR_TRANS_PROTO, 316 317 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 318 EDMA_ERR_PRD_PAR | 319 EDMA_ERR_DEV_DCON | 320 EDMA_ERR_DEV_CON | 321 EDMA_ERR_OVERRUN_5 | 322 EDMA_ERR_UNDERRUN_5 | 323 EDMA_ERR_SELF_DIS_5 | 324 EDMA_ERR_CRQB_PAR | 325 EDMA_ERR_CRPB_PAR | 326 EDMA_ERR_INTRL_PAR | 327 EDMA_ERR_IORDY, 328 329 EDMA_REQ_Q_BASE_HI_OFS = 0x10, 330 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 331 332 EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 333 EDMA_REQ_Q_PTR_SHIFT = 5, 334 335 EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 336 EDMA_RSP_Q_IN_PTR_OFS = 0x20, 337 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 338 EDMA_RSP_Q_PTR_SHIFT = 3, 339 340 EDMA_CMD_OFS = 0x28, /* EDMA command register */ 341 EDMA_EN = (1 << 0), /* enable EDMA */ 342 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 343 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 344 345 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ 346 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 347 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 348 349 EDMA_IORDY_TMOUT_OFS = 0x34, 350 EDMA_ARB_CFG_OFS = 0x38, 351 352 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 353 354 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 355 356 /* Host private flags (hp_flags) */ 357 MV_HP_FLAG_MSI = (1 << 0), 358 MV_HP_ERRATA_50XXB0 = (1 << 1), 359 MV_HP_ERRATA_50XXB2 = (1 << 2), 360 MV_HP_ERRATA_60X1B2 = (1 << 3), 361 MV_HP_ERRATA_60X1C0 = (1 << 4), 362 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 363 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 364 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 365 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 366 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 367 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 368 369 /* Port private flags (pp_flags) */ 370 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 371 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 372 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 373 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 374 }; 375 376 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 377 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 378 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 379 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 380 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 381 382 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 383 #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 384 385 enum { 386 /* DMA boundary 0xffff is required by the s/g splitting 387 * we need on /length/ in mv_fill-sg(). 388 */ 389 MV_DMA_BOUNDARY = 0xffffU, 390 391 /* mask of register bits containing lower 32 bits 392 * of EDMA request queue DMA address 393 */ 394 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 395 396 /* ditto, for response queue */ 397 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 398 }; 399 400 enum chip_type { 401 chip_504x, 402 chip_508x, 403 chip_5080, 404 chip_604x, 405 chip_608x, 406 chip_6042, 407 chip_7042, 408 chip_soc, 409 }; 410 411 /* Command ReQuest Block: 32B */ 412 struct mv_crqb { 413 __le32 sg_addr; 414 __le32 sg_addr_hi; 415 __le16 ctrl_flags; 416 __le16 ata_cmd[11]; 417 }; 418 419 struct mv_crqb_iie { 420 __le32 addr; 421 __le32 addr_hi; 422 __le32 flags; 423 __le32 len; 424 __le32 ata_cmd[4]; 425 }; 426 427 /* Command ResPonse Block: 8B */ 428 struct mv_crpb { 429 __le16 id; 430 __le16 flags; 431 __le32 tmstmp; 432 }; 433 434 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 435 struct mv_sg { 436 __le32 addr; 437 __le32 flags_size; 438 __le32 addr_hi; 439 __le32 reserved; 440 }; 441 442 struct mv_port_priv { 443 struct mv_crqb *crqb; 444 dma_addr_t crqb_dma; 445 struct mv_crpb *crpb; 446 dma_addr_t crpb_dma; 447 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 448 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 449 450 unsigned int req_idx; 451 unsigned int resp_idx; 452 453 u32 pp_flags; 454 unsigned int delayed_eh_pmp_map; 455 }; 456 457 struct mv_port_signal { 458 u32 amps; 459 u32 pre; 460 }; 461 462 struct mv_host_priv { 463 u32 hp_flags; 464 u32 main_irq_mask; 465 struct mv_port_signal signal[8]; 466 const struct mv_hw_ops *ops; 467 int n_ports; 468 void __iomem *base; 469 void __iomem *main_irq_cause_addr; 470 void __iomem *main_irq_mask_addr; 471 u32 irq_cause_ofs; 472 u32 irq_mask_ofs; 473 u32 unmask_all_irqs; 474 /* 475 * These consistent DMA memory pools give us guaranteed 476 * alignment for hardware-accessed data structures, 477 * and less memory waste in accomplishing the alignment. 478 */ 479 struct dma_pool *crqb_pool; 480 struct dma_pool *crpb_pool; 481 struct dma_pool *sg_tbl_pool; 482 }; 483 484 struct mv_hw_ops { 485 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 486 unsigned int port); 487 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 488 void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 489 void __iomem *mmio); 490 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 491 unsigned int n_hc); 492 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 493 void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 494 }; 495 496 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 497 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 498 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 499 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 500 static int mv_port_start(struct ata_port *ap); 501 static void mv_port_stop(struct ata_port *ap); 502 static int mv_qc_defer(struct ata_queued_cmd *qc); 503 static void mv_qc_prep(struct ata_queued_cmd *qc); 504 static void mv_qc_prep_iie(struct ata_queued_cmd *qc); 505 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 506 static int mv_hardreset(struct ata_link *link, unsigned int *class, 507 unsigned long deadline); 508 static void mv_eh_freeze(struct ata_port *ap); 509 static void mv_eh_thaw(struct ata_port *ap); 510 static void mv6_dev_config(struct ata_device *dev); 511 512 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 513 unsigned int port); 514 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 515 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 516 void __iomem *mmio); 517 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 518 unsigned int n_hc); 519 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 520 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 521 522 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 523 unsigned int port); 524 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 525 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 526 void __iomem *mmio); 527 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 528 unsigned int n_hc); 529 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 530 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 531 void __iomem *mmio); 532 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 533 void __iomem *mmio); 534 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 535 void __iomem *mmio, unsigned int n_hc); 536 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 537 void __iomem *mmio); 538 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 539 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 540 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 541 unsigned int port_no); 542 static int mv_stop_edma(struct ata_port *ap); 543 static int mv_stop_edma_engine(void __iomem *port_mmio); 544 static void mv_edma_cfg(struct ata_port *ap, int want_ncq); 545 546 static void mv_pmp_select(struct ata_port *ap, int pmp); 547 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 548 unsigned long deadline); 549 static int mv_softreset(struct ata_link *link, unsigned int *class, 550 unsigned long deadline); 551 static void mv_pmp_error_handler(struct ata_port *ap); 552 static void mv_process_crpb_entries(struct ata_port *ap, 553 struct mv_port_priv *pp); 554 555 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 556 * because we have to allow room for worst case splitting of 557 * PRDs for 64K boundaries in mv_fill_sg(). 558 */ 559 static struct scsi_host_template mv5_sht = { 560 ATA_BASE_SHT(DRV_NAME), 561 .sg_tablesize = MV_MAX_SG_CT / 2, 562 .dma_boundary = MV_DMA_BOUNDARY, 563 }; 564 565 static struct scsi_host_template mv6_sht = { 566 ATA_NCQ_SHT(DRV_NAME), 567 .can_queue = MV_MAX_Q_DEPTH - 1, 568 .sg_tablesize = MV_MAX_SG_CT / 2, 569 .dma_boundary = MV_DMA_BOUNDARY, 570 }; 571 572 static struct ata_port_operations mv5_ops = { 573 .inherits = &ata_sff_port_ops, 574 575 .qc_defer = mv_qc_defer, 576 .qc_prep = mv_qc_prep, 577 .qc_issue = mv_qc_issue, 578 579 .freeze = mv_eh_freeze, 580 .thaw = mv_eh_thaw, 581 .hardreset = mv_hardreset, 582 .error_handler = ata_std_error_handler, /* avoid SFF EH */ 583 .post_internal_cmd = ATA_OP_NULL, 584 585 .scr_read = mv5_scr_read, 586 .scr_write = mv5_scr_write, 587 588 .port_start = mv_port_start, 589 .port_stop = mv_port_stop, 590 }; 591 592 static struct ata_port_operations mv6_ops = { 593 .inherits = &mv5_ops, 594 .dev_config = mv6_dev_config, 595 .scr_read = mv_scr_read, 596 .scr_write = mv_scr_write, 597 598 .pmp_hardreset = mv_pmp_hardreset, 599 .pmp_softreset = mv_softreset, 600 .softreset = mv_softreset, 601 .error_handler = mv_pmp_error_handler, 602 }; 603 604 static struct ata_port_operations mv_iie_ops = { 605 .inherits = &mv6_ops, 606 .dev_config = ATA_OP_NULL, 607 .qc_prep = mv_qc_prep_iie, 608 }; 609 610 static const struct ata_port_info mv_port_info[] = { 611 { /* chip_504x */ 612 .flags = MV_COMMON_FLAGS, 613 .pio_mask = 0x1f, /* pio0-4 */ 614 .udma_mask = ATA_UDMA6, 615 .port_ops = &mv5_ops, 616 }, 617 { /* chip_508x */ 618 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 619 .pio_mask = 0x1f, /* pio0-4 */ 620 .udma_mask = ATA_UDMA6, 621 .port_ops = &mv5_ops, 622 }, 623 { /* chip_5080 */ 624 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 625 .pio_mask = 0x1f, /* pio0-4 */ 626 .udma_mask = ATA_UDMA6, 627 .port_ops = &mv5_ops, 628 }, 629 { /* chip_604x */ 630 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 631 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 632 ATA_FLAG_NCQ, 633 .pio_mask = 0x1f, /* pio0-4 */ 634 .udma_mask = ATA_UDMA6, 635 .port_ops = &mv6_ops, 636 }, 637 { /* chip_608x */ 638 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 639 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 640 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 641 .pio_mask = 0x1f, /* pio0-4 */ 642 .udma_mask = ATA_UDMA6, 643 .port_ops = &mv6_ops, 644 }, 645 { /* chip_6042 */ 646 .flags = MV_GENIIE_FLAGS, 647 .pio_mask = 0x1f, /* pio0-4 */ 648 .udma_mask = ATA_UDMA6, 649 .port_ops = &mv_iie_ops, 650 }, 651 { /* chip_7042 */ 652 .flags = MV_GENIIE_FLAGS, 653 .pio_mask = 0x1f, /* pio0-4 */ 654 .udma_mask = ATA_UDMA6, 655 .port_ops = &mv_iie_ops, 656 }, 657 { /* chip_soc */ 658 .flags = MV_GENIIE_FLAGS, 659 .pio_mask = 0x1f, /* pio0-4 */ 660 .udma_mask = ATA_UDMA6, 661 .port_ops = &mv_iie_ops, 662 }, 663 }; 664 665 static const struct pci_device_id mv_pci_tbl[] = { 666 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 667 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 668 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 669 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 670 /* RocketRAID 1740/174x have different identifiers */ 671 { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 672 { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 673 674 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 675 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 676 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 677 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 678 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 679 680 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 681 682 /* Adaptec 1430SA */ 683 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 684 685 /* Marvell 7042 support */ 686 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 687 688 /* Highpoint RocketRAID PCIe series */ 689 { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 690 { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 691 692 { } /* terminate list */ 693 }; 694 695 static const struct mv_hw_ops mv5xxx_ops = { 696 .phy_errata = mv5_phy_errata, 697 .enable_leds = mv5_enable_leds, 698 .read_preamp = mv5_read_preamp, 699 .reset_hc = mv5_reset_hc, 700 .reset_flash = mv5_reset_flash, 701 .reset_bus = mv5_reset_bus, 702 }; 703 704 static const struct mv_hw_ops mv6xxx_ops = { 705 .phy_errata = mv6_phy_errata, 706 .enable_leds = mv6_enable_leds, 707 .read_preamp = mv6_read_preamp, 708 .reset_hc = mv6_reset_hc, 709 .reset_flash = mv6_reset_flash, 710 .reset_bus = mv_reset_pci_bus, 711 }; 712 713 static const struct mv_hw_ops mv_soc_ops = { 714 .phy_errata = mv6_phy_errata, 715 .enable_leds = mv_soc_enable_leds, 716 .read_preamp = mv_soc_read_preamp, 717 .reset_hc = mv_soc_reset_hc, 718 .reset_flash = mv_soc_reset_flash, 719 .reset_bus = mv_soc_reset_bus, 720 }; 721 722 /* 723 * Functions 724 */ 725 726 static inline void writelfl(unsigned long data, void __iomem *addr) 727 { 728 writel(data, addr); 729 (void) readl(addr); /* flush to avoid PCI posted write */ 730 } 731 732 static inline unsigned int mv_hc_from_port(unsigned int port) 733 { 734 return port >> MV_PORT_HC_SHIFT; 735 } 736 737 static inline unsigned int mv_hardport_from_port(unsigned int port) 738 { 739 return port & MV_PORT_MASK; 740 } 741 742 /* 743 * Consolidate some rather tricky bit shift calculations. 744 * This is hot-path stuff, so not a function. 745 * Simple code, with two return values, so macro rather than inline. 746 * 747 * port is the sole input, in range 0..7. 748 * shift is one output, for use with main_irq_cause / main_irq_mask registers. 749 * hardport is the other output, in range 0..3. 750 * 751 * Note that port and hardport may be the same variable in some cases. 752 */ 753 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 754 { \ 755 shift = mv_hc_from_port(port) * HC_SHIFT; \ 756 hardport = mv_hardport_from_port(port); \ 757 shift += hardport * 2; \ 758 } 759 760 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 761 { 762 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 763 } 764 765 static inline void __iomem *mv_hc_base_from_port(void __iomem *base, 766 unsigned int port) 767 { 768 return mv_hc_base(base, mv_hc_from_port(port)); 769 } 770 771 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 772 { 773 return mv_hc_base_from_port(base, port) + 774 MV_SATAHC_ARBTR_REG_SZ + 775 (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 776 } 777 778 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 779 { 780 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 781 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 782 783 return hc_mmio + ofs; 784 } 785 786 static inline void __iomem *mv_host_base(struct ata_host *host) 787 { 788 struct mv_host_priv *hpriv = host->private_data; 789 return hpriv->base; 790 } 791 792 static inline void __iomem *mv_ap_base(struct ata_port *ap) 793 { 794 return mv_port_base(mv_host_base(ap->host), ap->port_no); 795 } 796 797 static inline int mv_get_hc_count(unsigned long port_flags) 798 { 799 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 800 } 801 802 static void mv_set_edma_ptrs(void __iomem *port_mmio, 803 struct mv_host_priv *hpriv, 804 struct mv_port_priv *pp) 805 { 806 u32 index; 807 808 /* 809 * initialize request queue 810 */ 811 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 812 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 813 814 WARN_ON(pp->crqb_dma & 0x3ff); 815 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 816 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 817 port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 818 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 819 820 /* 821 * initialize response queue 822 */ 823 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 824 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 825 826 WARN_ON(pp->crpb_dma & 0xff); 827 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 828 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 829 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 830 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 831 } 832 833 static void mv_set_main_irq_mask(struct ata_host *host, 834 u32 disable_bits, u32 enable_bits) 835 { 836 struct mv_host_priv *hpriv = host->private_data; 837 u32 old_mask, new_mask; 838 839 old_mask = hpriv->main_irq_mask; 840 new_mask = (old_mask & ~disable_bits) | enable_bits; 841 if (new_mask != old_mask) { 842 hpriv->main_irq_mask = new_mask; 843 writelfl(new_mask, hpriv->main_irq_mask_addr); 844 } 845 } 846 847 static void mv_enable_port_irqs(struct ata_port *ap, 848 unsigned int port_bits) 849 { 850 unsigned int shift, hardport, port = ap->port_no; 851 u32 disable_bits, enable_bits; 852 853 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 854 855 disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 856 enable_bits = port_bits << shift; 857 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 858 } 859 860 /** 861 * mv_start_dma - Enable eDMA engine 862 * @base: port base address 863 * @pp: port private data 864 * 865 * Verify the local cache of the eDMA state is accurate with a 866 * WARN_ON. 867 * 868 * LOCKING: 869 * Inherited from caller. 870 */ 871 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 872 struct mv_port_priv *pp, u8 protocol) 873 { 874 int want_ncq = (protocol == ATA_PROT_NCQ); 875 876 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 877 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 878 if (want_ncq != using_ncq) 879 mv_stop_edma(ap); 880 } 881 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 882 struct mv_host_priv *hpriv = ap->host->private_data; 883 int hardport = mv_hardport_from_port(ap->port_no); 884 void __iomem *hc_mmio = mv_hc_base_from_port( 885 mv_host_base(ap->host), hardport); 886 u32 hc_irq_cause, ipending; 887 888 /* clear EDMA event indicators, if any */ 889 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 890 891 /* clear EDMA interrupt indicator, if any */ 892 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 893 ipending = (DEV_IRQ | DMA_IRQ) << hardport; 894 if (hc_irq_cause & ipending) { 895 writelfl(hc_irq_cause & ~ipending, 896 hc_mmio + HC_IRQ_CAUSE_OFS); 897 } 898 899 mv_edma_cfg(ap, want_ncq); 900 901 /* clear FIS IRQ Cause */ 902 if (IS_GEN_IIE(hpriv)) 903 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 904 905 mv_set_edma_ptrs(port_mmio, hpriv, pp); 906 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ); 907 908 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 909 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 910 } 911 } 912 913 static void mv_wait_for_edma_empty_idle(struct ata_port *ap) 914 { 915 void __iomem *port_mmio = mv_ap_base(ap); 916 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 917 const int per_loop = 5, timeout = (15 * 1000 / per_loop); 918 int i; 919 920 /* 921 * Wait for the EDMA engine to finish transactions in progress. 922 * No idea what a good "timeout" value might be, but measurements 923 * indicate that it often requires hundreds of microseconds 924 * with two drives in-use. So we use the 15msec value above 925 * as a rough guess at what even more drives might require. 926 */ 927 for (i = 0; i < timeout; ++i) { 928 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); 929 if ((edma_stat & empty_idle) == empty_idle) 930 break; 931 udelay(per_loop); 932 } 933 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 934 } 935 936 /** 937 * mv_stop_edma_engine - Disable eDMA engine 938 * @port_mmio: io base address 939 * 940 * LOCKING: 941 * Inherited from caller. 942 */ 943 static int mv_stop_edma_engine(void __iomem *port_mmio) 944 { 945 int i; 946 947 /* Disable eDMA. The disable bit auto clears. */ 948 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 949 950 /* Wait for the chip to confirm eDMA is off. */ 951 for (i = 10000; i > 0; i--) { 952 u32 reg = readl(port_mmio + EDMA_CMD_OFS); 953 if (!(reg & EDMA_EN)) 954 return 0; 955 udelay(10); 956 } 957 return -EIO; 958 } 959 960 static int mv_stop_edma(struct ata_port *ap) 961 { 962 void __iomem *port_mmio = mv_ap_base(ap); 963 struct mv_port_priv *pp = ap->private_data; 964 965 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 966 return 0; 967 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 968 mv_wait_for_edma_empty_idle(ap); 969 if (mv_stop_edma_engine(port_mmio)) { 970 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 971 return -EIO; 972 } 973 return 0; 974 } 975 976 #ifdef ATA_DEBUG 977 static void mv_dump_mem(void __iomem *start, unsigned bytes) 978 { 979 int b, w; 980 for (b = 0; b < bytes; ) { 981 DPRINTK("%p: ", start + b); 982 for (w = 0; b < bytes && w < 4; w++) { 983 printk("%08x ", readl(start + b)); 984 b += sizeof(u32); 985 } 986 printk("\n"); 987 } 988 } 989 #endif 990 991 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 992 { 993 #ifdef ATA_DEBUG 994 int b, w; 995 u32 dw; 996 for (b = 0; b < bytes; ) { 997 DPRINTK("%02x: ", b); 998 for (w = 0; b < bytes && w < 4; w++) { 999 (void) pci_read_config_dword(pdev, b, &dw); 1000 printk("%08x ", dw); 1001 b += sizeof(u32); 1002 } 1003 printk("\n"); 1004 } 1005 #endif 1006 } 1007 static void mv_dump_all_regs(void __iomem *mmio_base, int port, 1008 struct pci_dev *pdev) 1009 { 1010 #ifdef ATA_DEBUG 1011 void __iomem *hc_base = mv_hc_base(mmio_base, 1012 port >> MV_PORT_HC_SHIFT); 1013 void __iomem *port_base; 1014 int start_port, num_ports, p, start_hc, num_hcs, hc; 1015 1016 if (0 > port) { 1017 start_hc = start_port = 0; 1018 num_ports = 8; /* shld be benign for 4 port devs */ 1019 num_hcs = 2; 1020 } else { 1021 start_hc = port >> MV_PORT_HC_SHIFT; 1022 start_port = port; 1023 num_ports = num_hcs = 1; 1024 } 1025 DPRINTK("All registers for port(s) %u-%u:\n", start_port, 1026 num_ports > 1 ? num_ports - 1 : start_port); 1027 1028 if (NULL != pdev) { 1029 DPRINTK("PCI config space regs:\n"); 1030 mv_dump_pci_cfg(pdev, 0x68); 1031 } 1032 DPRINTK("PCI regs:\n"); 1033 mv_dump_mem(mmio_base+0xc00, 0x3c); 1034 mv_dump_mem(mmio_base+0xd00, 0x34); 1035 mv_dump_mem(mmio_base+0xf00, 0x4); 1036 mv_dump_mem(mmio_base+0x1d00, 0x6c); 1037 for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1038 hc_base = mv_hc_base(mmio_base, hc); 1039 DPRINTK("HC regs (HC %i):\n", hc); 1040 mv_dump_mem(hc_base, 0x1c); 1041 } 1042 for (p = start_port; p < start_port + num_ports; p++) { 1043 port_base = mv_port_base(mmio_base, p); 1044 DPRINTK("EDMA regs (port %i):\n", p); 1045 mv_dump_mem(port_base, 0x54); 1046 DPRINTK("SATA regs (port %i):\n", p); 1047 mv_dump_mem(port_base+0x300, 0x60); 1048 } 1049 #endif 1050 } 1051 1052 static unsigned int mv_scr_offset(unsigned int sc_reg_in) 1053 { 1054 unsigned int ofs; 1055 1056 switch (sc_reg_in) { 1057 case SCR_STATUS: 1058 case SCR_CONTROL: 1059 case SCR_ERROR: 1060 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 1061 break; 1062 case SCR_ACTIVE: 1063 ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 1064 break; 1065 default: 1066 ofs = 0xffffffffU; 1067 break; 1068 } 1069 return ofs; 1070 } 1071 1072 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1073 { 1074 unsigned int ofs = mv_scr_offset(sc_reg_in); 1075 1076 if (ofs != 0xffffffffU) { 1077 *val = readl(mv_ap_base(ap) + ofs); 1078 return 0; 1079 } else 1080 return -EINVAL; 1081 } 1082 1083 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1084 { 1085 unsigned int ofs = mv_scr_offset(sc_reg_in); 1086 1087 if (ofs != 0xffffffffU) { 1088 writelfl(val, mv_ap_base(ap) + ofs); 1089 return 0; 1090 } else 1091 return -EINVAL; 1092 } 1093 1094 static void mv6_dev_config(struct ata_device *adev) 1095 { 1096 /* 1097 * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1098 * 1099 * Gen-II does not support NCQ over a port multiplier 1100 * (no FIS-based switching). 1101 * 1102 * We don't have hob_nsect when doing NCQ commands on Gen-II. 1103 * See mv_qc_prep() for more info. 1104 */ 1105 if (adev->flags & ATA_DFLAG_NCQ) { 1106 if (sata_pmp_attached(adev->link->ap)) { 1107 adev->flags &= ~ATA_DFLAG_NCQ; 1108 ata_dev_printk(adev, KERN_INFO, 1109 "NCQ disabled for command-based switching\n"); 1110 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { 1111 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; 1112 ata_dev_printk(adev, KERN_INFO, 1113 "max_sectors limited to %u for NCQ\n", 1114 adev->max_sectors); 1115 } 1116 } 1117 } 1118 1119 static int mv_qc_defer(struct ata_queued_cmd *qc) 1120 { 1121 struct ata_link *link = qc->dev->link; 1122 struct ata_port *ap = link->ap; 1123 struct mv_port_priv *pp = ap->private_data; 1124 1125 /* 1126 * Don't allow new commands if we're in a delayed EH state 1127 * for NCQ and/or FIS-based switching. 1128 */ 1129 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 1130 return ATA_DEFER_PORT; 1131 /* 1132 * If the port is completely idle, then allow the new qc. 1133 */ 1134 if (ap->nr_active_links == 0) 1135 return 0; 1136 1137 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1138 /* 1139 * The port is operating in host queuing mode (EDMA). 1140 * It can accomodate a new qc if the qc protocol 1141 * is compatible with the current host queue mode. 1142 */ 1143 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 1144 /* 1145 * The host queue (EDMA) is in NCQ mode. 1146 * If the new qc is also an NCQ command, 1147 * then allow the new qc. 1148 */ 1149 if (qc->tf.protocol == ATA_PROT_NCQ) 1150 return 0; 1151 } else { 1152 /* 1153 * The host queue (EDMA) is in non-NCQ, DMA mode. 1154 * If the new qc is also a non-NCQ, DMA command, 1155 * then allow the new qc. 1156 */ 1157 if (qc->tf.protocol == ATA_PROT_DMA) 1158 return 0; 1159 } 1160 } 1161 return ATA_DEFER_PORT; 1162 } 1163 1164 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs) 1165 { 1166 u32 new_fiscfg, old_fiscfg; 1167 u32 new_ltmode, old_ltmode; 1168 u32 new_haltcond, old_haltcond; 1169 1170 old_fiscfg = readl(port_mmio + FISCFG_OFS); 1171 old_ltmode = readl(port_mmio + LTMODE_OFS); 1172 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS); 1173 1174 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1175 new_ltmode = old_ltmode & ~LTMODE_BIT8; 1176 new_haltcond = old_haltcond | EDMA_ERR_DEV; 1177 1178 if (want_fbs) { 1179 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC; 1180 new_ltmode = old_ltmode | LTMODE_BIT8; 1181 if (want_ncq) 1182 new_haltcond &= ~EDMA_ERR_DEV; 1183 else 1184 new_fiscfg |= FISCFG_WAIT_DEV_ERR; 1185 } 1186 1187 if (new_fiscfg != old_fiscfg) 1188 writelfl(new_fiscfg, port_mmio + FISCFG_OFS); 1189 if (new_ltmode != old_ltmode) 1190 writelfl(new_ltmode, port_mmio + LTMODE_OFS); 1191 if (new_haltcond != old_haltcond) 1192 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS); 1193 } 1194 1195 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1196 { 1197 struct mv_host_priv *hpriv = ap->host->private_data; 1198 u32 old, new; 1199 1200 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1201 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS); 1202 if (want_ncq) 1203 new = old | (1 << 22); 1204 else 1205 new = old & ~(1 << 22); 1206 if (new != old) 1207 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS); 1208 } 1209 1210 static void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1211 { 1212 u32 cfg; 1213 struct mv_port_priv *pp = ap->private_data; 1214 struct mv_host_priv *hpriv = ap->host->private_data; 1215 void __iomem *port_mmio = mv_ap_base(ap); 1216 1217 /* set up non-NCQ EDMA configuration */ 1218 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1219 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN; 1220 1221 if (IS_GEN_I(hpriv)) 1222 cfg |= (1 << 8); /* enab config burst size mask */ 1223 1224 else if (IS_GEN_II(hpriv)) { 1225 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1226 mv_60x1_errata_sata25(ap, want_ncq); 1227 1228 } else if (IS_GEN_IIE(hpriv)) { 1229 int want_fbs = sata_pmp_attached(ap); 1230 /* 1231 * Possible future enhancement: 1232 * 1233 * The chip can use FBS with non-NCQ, if we allow it, 1234 * But first we need to have the error handling in place 1235 * for this mode (datasheet section 7.3.15.4.2.3). 1236 * So disallow non-NCQ FBS for now. 1237 */ 1238 want_fbs &= want_ncq; 1239 1240 mv_config_fbs(port_mmio, want_ncq, want_fbs); 1241 1242 if (want_fbs) { 1243 pp->pp_flags |= MV_PP_FLAG_FBS_EN; 1244 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1245 } 1246 1247 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1248 cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1249 if (!IS_SOC(hpriv)) 1250 cfg |= (1 << 18); /* enab early completion */ 1251 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1252 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1253 } 1254 1255 if (want_ncq) { 1256 cfg |= EDMA_CFG_NCQ; 1257 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1258 } else 1259 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1260 1261 writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1262 } 1263 1264 static void mv_port_free_dma_mem(struct ata_port *ap) 1265 { 1266 struct mv_host_priv *hpriv = ap->host->private_data; 1267 struct mv_port_priv *pp = ap->private_data; 1268 int tag; 1269 1270 if (pp->crqb) { 1271 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1272 pp->crqb = NULL; 1273 } 1274 if (pp->crpb) { 1275 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1276 pp->crpb = NULL; 1277 } 1278 /* 1279 * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1280 * For later hardware, we have one unique sg_tbl per NCQ tag. 1281 */ 1282 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1283 if (pp->sg_tbl[tag]) { 1284 if (tag == 0 || !IS_GEN_I(hpriv)) 1285 dma_pool_free(hpriv->sg_tbl_pool, 1286 pp->sg_tbl[tag], 1287 pp->sg_tbl_dma[tag]); 1288 pp->sg_tbl[tag] = NULL; 1289 } 1290 } 1291 } 1292 1293 /** 1294 * mv_port_start - Port specific init/start routine. 1295 * @ap: ATA channel to manipulate 1296 * 1297 * Allocate and point to DMA memory, init port private memory, 1298 * zero indices. 1299 * 1300 * LOCKING: 1301 * Inherited from caller. 1302 */ 1303 static int mv_port_start(struct ata_port *ap) 1304 { 1305 struct device *dev = ap->host->dev; 1306 struct mv_host_priv *hpriv = ap->host->private_data; 1307 struct mv_port_priv *pp; 1308 int tag; 1309 1310 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1311 if (!pp) 1312 return -ENOMEM; 1313 ap->private_data = pp; 1314 1315 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1316 if (!pp->crqb) 1317 return -ENOMEM; 1318 memset(pp->crqb, 0, MV_CRQB_Q_SZ); 1319 1320 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1321 if (!pp->crpb) 1322 goto out_port_free_dma_mem; 1323 memset(pp->crpb, 0, MV_CRPB_Q_SZ); 1324 1325 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 1326 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 1327 ap->flags |= ATA_FLAG_AN; 1328 /* 1329 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1330 * For later hardware, we need one unique sg_tbl per NCQ tag. 1331 */ 1332 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1333 if (tag == 0 || !IS_GEN_I(hpriv)) { 1334 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1335 GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1336 if (!pp->sg_tbl[tag]) 1337 goto out_port_free_dma_mem; 1338 } else { 1339 pp->sg_tbl[tag] = pp->sg_tbl[0]; 1340 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1341 } 1342 } 1343 return 0; 1344 1345 out_port_free_dma_mem: 1346 mv_port_free_dma_mem(ap); 1347 return -ENOMEM; 1348 } 1349 1350 /** 1351 * mv_port_stop - Port specific cleanup/stop routine. 1352 * @ap: ATA channel to manipulate 1353 * 1354 * Stop DMA, cleanup port memory. 1355 * 1356 * LOCKING: 1357 * This routine uses the host lock to protect the DMA stop. 1358 */ 1359 static void mv_port_stop(struct ata_port *ap) 1360 { 1361 mv_stop_edma(ap); 1362 mv_enable_port_irqs(ap, 0); 1363 mv_port_free_dma_mem(ap); 1364 } 1365 1366 /** 1367 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 1368 * @qc: queued command whose SG list to source from 1369 * 1370 * Populate the SG list and mark the last entry. 1371 * 1372 * LOCKING: 1373 * Inherited from caller. 1374 */ 1375 static void mv_fill_sg(struct ata_queued_cmd *qc) 1376 { 1377 struct mv_port_priv *pp = qc->ap->private_data; 1378 struct scatterlist *sg; 1379 struct mv_sg *mv_sg, *last_sg = NULL; 1380 unsigned int si; 1381 1382 mv_sg = pp->sg_tbl[qc->tag]; 1383 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1384 dma_addr_t addr = sg_dma_address(sg); 1385 u32 sg_len = sg_dma_len(sg); 1386 1387 while (sg_len) { 1388 u32 offset = addr & 0xffff; 1389 u32 len = sg_len; 1390 1391 if ((offset + sg_len > 0x10000)) 1392 len = 0x10000 - offset; 1393 1394 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 1395 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 1396 mv_sg->flags_size = cpu_to_le32(len & 0xffff); 1397 1398 sg_len -= len; 1399 addr += len; 1400 1401 last_sg = mv_sg; 1402 mv_sg++; 1403 } 1404 } 1405 1406 if (likely(last_sg)) 1407 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 1408 } 1409 1410 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 1411 { 1412 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 1413 (last ? CRQB_CMD_LAST : 0); 1414 *cmdw = cpu_to_le16(tmp); 1415 } 1416 1417 /** 1418 * mv_qc_prep - Host specific command preparation. 1419 * @qc: queued command to prepare 1420 * 1421 * This routine simply redirects to the general purpose routine 1422 * if command is not DMA. Else, it handles prep of the CRQB 1423 * (command request block), does some sanity checking, and calls 1424 * the SG load routine. 1425 * 1426 * LOCKING: 1427 * Inherited from caller. 1428 */ 1429 static void mv_qc_prep(struct ata_queued_cmd *qc) 1430 { 1431 struct ata_port *ap = qc->ap; 1432 struct mv_port_priv *pp = ap->private_data; 1433 __le16 *cw; 1434 struct ata_taskfile *tf; 1435 u16 flags = 0; 1436 unsigned in_index; 1437 1438 if ((qc->tf.protocol != ATA_PROT_DMA) && 1439 (qc->tf.protocol != ATA_PROT_NCQ)) 1440 return; 1441 1442 /* Fill in command request block 1443 */ 1444 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1445 flags |= CRQB_FLAG_READ; 1446 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1447 flags |= qc->tag << CRQB_TAG_SHIFT; 1448 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1449 1450 /* get current queue index from software */ 1451 in_index = pp->req_idx; 1452 1453 pp->crqb[in_index].sg_addr = 1454 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1455 pp->crqb[in_index].sg_addr_hi = 1456 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1457 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 1458 1459 cw = &pp->crqb[in_index].ata_cmd[0]; 1460 tf = &qc->tf; 1461 1462 /* Sadly, the CRQB cannot accomodate all registers--there are 1463 * only 11 bytes...so we must pick and choose required 1464 * registers based on the command. So, we drop feature and 1465 * hob_feature for [RW] DMA commands, but they are needed for 1466 * NCQ. NCQ will drop hob_nsect. 1467 */ 1468 switch (tf->command) { 1469 case ATA_CMD_READ: 1470 case ATA_CMD_READ_EXT: 1471 case ATA_CMD_WRITE: 1472 case ATA_CMD_WRITE_EXT: 1473 case ATA_CMD_WRITE_FUA_EXT: 1474 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 1475 break; 1476 case ATA_CMD_FPDMA_READ: 1477 case ATA_CMD_FPDMA_WRITE: 1478 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 1479 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 1480 break; 1481 default: 1482 /* The only other commands EDMA supports in non-queued and 1483 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 1484 * of which are defined/used by Linux. If we get here, this 1485 * driver needs work. 1486 * 1487 * FIXME: modify libata to give qc_prep a return value and 1488 * return error here. 1489 */ 1490 BUG_ON(tf->command); 1491 break; 1492 } 1493 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 1494 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 1495 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 1496 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 1497 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 1498 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 1499 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 1500 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 1501 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 1502 1503 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1504 return; 1505 mv_fill_sg(qc); 1506 } 1507 1508 /** 1509 * mv_qc_prep_iie - Host specific command preparation. 1510 * @qc: queued command to prepare 1511 * 1512 * This routine simply redirects to the general purpose routine 1513 * if command is not DMA. Else, it handles prep of the CRQB 1514 * (command request block), does some sanity checking, and calls 1515 * the SG load routine. 1516 * 1517 * LOCKING: 1518 * Inherited from caller. 1519 */ 1520 static void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1521 { 1522 struct ata_port *ap = qc->ap; 1523 struct mv_port_priv *pp = ap->private_data; 1524 struct mv_crqb_iie *crqb; 1525 struct ata_taskfile *tf; 1526 unsigned in_index; 1527 u32 flags = 0; 1528 1529 if ((qc->tf.protocol != ATA_PROT_DMA) && 1530 (qc->tf.protocol != ATA_PROT_NCQ)) 1531 return; 1532 1533 /* Fill in Gen IIE command request block */ 1534 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1535 flags |= CRQB_FLAG_READ; 1536 1537 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1538 flags |= qc->tag << CRQB_TAG_SHIFT; 1539 flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1540 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1541 1542 /* get current queue index from software */ 1543 in_index = pp->req_idx; 1544 1545 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1546 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1547 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1548 crqb->flags = cpu_to_le32(flags); 1549 1550 tf = &qc->tf; 1551 crqb->ata_cmd[0] = cpu_to_le32( 1552 (tf->command << 16) | 1553 (tf->feature << 24) 1554 ); 1555 crqb->ata_cmd[1] = cpu_to_le32( 1556 (tf->lbal << 0) | 1557 (tf->lbam << 8) | 1558 (tf->lbah << 16) | 1559 (tf->device << 24) 1560 ); 1561 crqb->ata_cmd[2] = cpu_to_le32( 1562 (tf->hob_lbal << 0) | 1563 (tf->hob_lbam << 8) | 1564 (tf->hob_lbah << 16) | 1565 (tf->hob_feature << 24) 1566 ); 1567 crqb->ata_cmd[3] = cpu_to_le32( 1568 (tf->nsect << 0) | 1569 (tf->hob_nsect << 8) 1570 ); 1571 1572 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1573 return; 1574 mv_fill_sg(qc); 1575 } 1576 1577 /** 1578 * mv_qc_issue - Initiate a command to the host 1579 * @qc: queued command to start 1580 * 1581 * This routine simply redirects to the general purpose routine 1582 * if command is not DMA. Else, it sanity checks our local 1583 * caches of the request producer/consumer indices then enables 1584 * DMA and bumps the request producer index. 1585 * 1586 * LOCKING: 1587 * Inherited from caller. 1588 */ 1589 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 1590 { 1591 struct ata_port *ap = qc->ap; 1592 void __iomem *port_mmio = mv_ap_base(ap); 1593 struct mv_port_priv *pp = ap->private_data; 1594 u32 in_index; 1595 1596 if ((qc->tf.protocol != ATA_PROT_DMA) && 1597 (qc->tf.protocol != ATA_PROT_NCQ)) { 1598 static int limit_warnings = 10; 1599 /* 1600 * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 1601 * 1602 * Someday, we might implement special polling workarounds 1603 * for these, but it all seems rather unnecessary since we 1604 * normally use only DMA for commands which transfer more 1605 * than a single block of data. 1606 * 1607 * Much of the time, this could just work regardless. 1608 * So for now, just log the incident, and allow the attempt. 1609 */ 1610 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 1611 --limit_warnings; 1612 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 1613 ": attempting PIO w/multiple DRQ: " 1614 "this may fail due to h/w errata\n"); 1615 } 1616 /* 1617 * We're about to send a non-EDMA capable command to the 1618 * port. Turn off EDMA so there won't be problems accessing 1619 * shadow block, etc registers. 1620 */ 1621 mv_stop_edma(ap); 1622 mv_enable_port_irqs(ap, ERR_IRQ); 1623 mv_pmp_select(ap, qc->dev->link->pmp); 1624 return ata_sff_qc_issue(qc); 1625 } 1626 1627 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1628 1629 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1630 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 1631 1632 /* and write the request in pointer to kick the EDMA to life */ 1633 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1634 port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 1635 1636 return 0; 1637 } 1638 1639 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 1640 { 1641 struct mv_port_priv *pp = ap->private_data; 1642 struct ata_queued_cmd *qc; 1643 1644 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1645 return NULL; 1646 qc = ata_qc_from_tag(ap, ap->link.active_tag); 1647 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1648 qc = NULL; 1649 return qc; 1650 } 1651 1652 static void mv_pmp_error_handler(struct ata_port *ap) 1653 { 1654 unsigned int pmp, pmp_map; 1655 struct mv_port_priv *pp = ap->private_data; 1656 1657 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 1658 /* 1659 * Perform NCQ error analysis on failed PMPs 1660 * before we freeze the port entirely. 1661 * 1662 * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 1663 */ 1664 pmp_map = pp->delayed_eh_pmp_map; 1665 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 1666 for (pmp = 0; pmp_map != 0; pmp++) { 1667 unsigned int this_pmp = (1 << pmp); 1668 if (pmp_map & this_pmp) { 1669 struct ata_link *link = &ap->pmp_link[pmp]; 1670 pmp_map &= ~this_pmp; 1671 ata_eh_analyze_ncq_error(link); 1672 } 1673 } 1674 ata_port_freeze(ap); 1675 } 1676 sata_pmp_error_handler(ap); 1677 } 1678 1679 static unsigned int mv_get_err_pmp_map(struct ata_port *ap) 1680 { 1681 void __iomem *port_mmio = mv_ap_base(ap); 1682 1683 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16; 1684 } 1685 1686 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 1687 { 1688 struct ata_eh_info *ehi; 1689 unsigned int pmp; 1690 1691 /* 1692 * Initialize EH info for PMPs which saw device errors 1693 */ 1694 ehi = &ap->link.eh_info; 1695 for (pmp = 0; pmp_map != 0; pmp++) { 1696 unsigned int this_pmp = (1 << pmp); 1697 if (pmp_map & this_pmp) { 1698 struct ata_link *link = &ap->pmp_link[pmp]; 1699 1700 pmp_map &= ~this_pmp; 1701 ehi = &link->eh_info; 1702 ata_ehi_clear_desc(ehi); 1703 ata_ehi_push_desc(ehi, "dev err"); 1704 ehi->err_mask |= AC_ERR_DEV; 1705 ehi->action |= ATA_EH_RESET; 1706 ata_link_abort(link); 1707 } 1708 } 1709 } 1710 1711 static int mv_req_q_empty(struct ata_port *ap) 1712 { 1713 void __iomem *port_mmio = mv_ap_base(ap); 1714 u32 in_ptr, out_ptr; 1715 1716 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS) 1717 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1718 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) 1719 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1720 return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 1721 } 1722 1723 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 1724 { 1725 struct mv_port_priv *pp = ap->private_data; 1726 int failed_links; 1727 unsigned int old_map, new_map; 1728 1729 /* 1730 * Device error during FBS+NCQ operation: 1731 * 1732 * Set a port flag to prevent further I/O being enqueued. 1733 * Leave the EDMA running to drain outstanding commands from this port. 1734 * Perform the post-mortem/EH only when all responses are complete. 1735 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 1736 */ 1737 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 1738 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 1739 pp->delayed_eh_pmp_map = 0; 1740 } 1741 old_map = pp->delayed_eh_pmp_map; 1742 new_map = old_map | mv_get_err_pmp_map(ap); 1743 1744 if (old_map != new_map) { 1745 pp->delayed_eh_pmp_map = new_map; 1746 mv_pmp_eh_prep(ap, new_map & ~old_map); 1747 } 1748 failed_links = hweight16(new_map); 1749 1750 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 1751 "failed_links=%d nr_active_links=%d\n", 1752 __func__, pp->delayed_eh_pmp_map, 1753 ap->qc_active, failed_links, 1754 ap->nr_active_links); 1755 1756 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 1757 mv_process_crpb_entries(ap, pp); 1758 mv_stop_edma(ap); 1759 mv_eh_freeze(ap); 1760 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 1761 return 1; /* handled */ 1762 } 1763 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 1764 return 1; /* handled */ 1765 } 1766 1767 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 1768 { 1769 /* 1770 * Possible future enhancement: 1771 * 1772 * FBS+non-NCQ operation is not yet implemented. 1773 * See related notes in mv_edma_cfg(). 1774 * 1775 * Device error during FBS+non-NCQ operation: 1776 * 1777 * We need to snapshot the shadow registers for each failed command. 1778 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 1779 */ 1780 return 0; /* not handled */ 1781 } 1782 1783 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 1784 { 1785 struct mv_port_priv *pp = ap->private_data; 1786 1787 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1788 return 0; /* EDMA was not active: not handled */ 1789 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 1790 return 0; /* FBS was not active: not handled */ 1791 1792 if (!(edma_err_cause & EDMA_ERR_DEV)) 1793 return 0; /* non DEV error: not handled */ 1794 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 1795 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 1796 return 0; /* other problems: not handled */ 1797 1798 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 1799 /* 1800 * EDMA should NOT have self-disabled for this case. 1801 * If it did, then something is wrong elsewhere, 1802 * and we cannot handle it here. 1803 */ 1804 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1805 ata_port_printk(ap, KERN_WARNING, 1806 "%s: err_cause=0x%x pp_flags=0x%x\n", 1807 __func__, edma_err_cause, pp->pp_flags); 1808 return 0; /* not handled */ 1809 } 1810 return mv_handle_fbs_ncq_dev_err(ap); 1811 } else { 1812 /* 1813 * EDMA should have self-disabled for this case. 1814 * If it did not, then something is wrong elsewhere, 1815 * and we cannot handle it here. 1816 */ 1817 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 1818 ata_port_printk(ap, KERN_WARNING, 1819 "%s: err_cause=0x%x pp_flags=0x%x\n", 1820 __func__, edma_err_cause, pp->pp_flags); 1821 return 0; /* not handled */ 1822 } 1823 return mv_handle_fbs_non_ncq_dev_err(ap); 1824 } 1825 return 0; /* not handled */ 1826 } 1827 1828 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 1829 { 1830 struct ata_eh_info *ehi = &ap->link.eh_info; 1831 char *when = "idle"; 1832 1833 ata_ehi_clear_desc(ehi); 1834 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 1835 when = "disabled"; 1836 } else if (edma_was_enabled) { 1837 when = "EDMA enabled"; 1838 } else { 1839 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 1840 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1841 when = "polling"; 1842 } 1843 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 1844 ehi->err_mask |= AC_ERR_OTHER; 1845 ehi->action |= ATA_EH_RESET; 1846 ata_port_freeze(ap); 1847 } 1848 1849 /** 1850 * mv_err_intr - Handle error interrupts on the port 1851 * @ap: ATA channel to manipulate 1852 * @qc: affected command (non-NCQ), or NULL 1853 * 1854 * Most cases require a full reset of the chip's state machine, 1855 * which also performs a COMRESET. 1856 * Also, if the port disabled DMA, update our cached copy to match. 1857 * 1858 * LOCKING: 1859 * Inherited from caller. 1860 */ 1861 static void mv_err_intr(struct ata_port *ap) 1862 { 1863 void __iomem *port_mmio = mv_ap_base(ap); 1864 u32 edma_err_cause, eh_freeze_mask, serr = 0; 1865 u32 fis_cause = 0; 1866 struct mv_port_priv *pp = ap->private_data; 1867 struct mv_host_priv *hpriv = ap->host->private_data; 1868 unsigned int action = 0, err_mask = 0; 1869 struct ata_eh_info *ehi = &ap->link.eh_info; 1870 struct ata_queued_cmd *qc; 1871 int abort = 0; 1872 1873 /* 1874 * Read and clear the SError and err_cause bits. 1875 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 1876 * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 1877 */ 1878 sata_scr_read(&ap->link, SCR_ERROR, &serr); 1879 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1880 1881 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1882 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 1883 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 1884 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 1885 } 1886 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1887 1888 if (edma_err_cause & EDMA_ERR_DEV) { 1889 /* 1890 * Device errors during FIS-based switching operation 1891 * require special handling. 1892 */ 1893 if (mv_handle_dev_err(ap, edma_err_cause)) 1894 return; 1895 } 1896 1897 qc = mv_get_active_qc(ap); 1898 ata_ehi_clear_desc(ehi); 1899 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 1900 edma_err_cause, pp->pp_flags); 1901 1902 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 1903 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 1904 if (fis_cause & SATA_FIS_IRQ_AN) { 1905 u32 ec = edma_err_cause & 1906 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 1907 sata_async_notification(ap); 1908 if (!ec) 1909 return; /* Just an AN; no need for the nukes */ 1910 ata_ehi_push_desc(ehi, "SDB notify"); 1911 } 1912 } 1913 /* 1914 * All generations share these EDMA error cause bits: 1915 */ 1916 if (edma_err_cause & EDMA_ERR_DEV) { 1917 err_mask |= AC_ERR_DEV; 1918 action |= ATA_EH_RESET; 1919 ata_ehi_push_desc(ehi, "dev error"); 1920 } 1921 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 1922 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1923 EDMA_ERR_INTRL_PAR)) { 1924 err_mask |= AC_ERR_ATA_BUS; 1925 action |= ATA_EH_RESET; 1926 ata_ehi_push_desc(ehi, "parity error"); 1927 } 1928 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1929 ata_ehi_hotplugged(ehi); 1930 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1931 "dev disconnect" : "dev connect"); 1932 action |= ATA_EH_RESET; 1933 } 1934 1935 /* 1936 * Gen-I has a different SELF_DIS bit, 1937 * different FREEZE bits, and no SERR bit: 1938 */ 1939 if (IS_GEN_I(hpriv)) { 1940 eh_freeze_mask = EDMA_EH_FREEZE_5; 1941 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 1942 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1943 ata_ehi_push_desc(ehi, "EDMA self-disable"); 1944 } 1945 } else { 1946 eh_freeze_mask = EDMA_EH_FREEZE; 1947 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1948 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1949 ata_ehi_push_desc(ehi, "EDMA self-disable"); 1950 } 1951 if (edma_err_cause & EDMA_ERR_SERR) { 1952 ata_ehi_push_desc(ehi, "SError=%08x", serr); 1953 err_mask |= AC_ERR_ATA_BUS; 1954 action |= ATA_EH_RESET; 1955 } 1956 } 1957 1958 if (!err_mask) { 1959 err_mask = AC_ERR_OTHER; 1960 action |= ATA_EH_RESET; 1961 } 1962 1963 ehi->serror |= serr; 1964 ehi->action |= action; 1965 1966 if (qc) 1967 qc->err_mask |= err_mask; 1968 else 1969 ehi->err_mask |= err_mask; 1970 1971 if (err_mask == AC_ERR_DEV) { 1972 /* 1973 * Cannot do ata_port_freeze() here, 1974 * because it would kill PIO access, 1975 * which is needed for further diagnosis. 1976 */ 1977 mv_eh_freeze(ap); 1978 abort = 1; 1979 } else if (edma_err_cause & eh_freeze_mask) { 1980 /* 1981 * Note to self: ata_port_freeze() calls ata_port_abort() 1982 */ 1983 ata_port_freeze(ap); 1984 } else { 1985 abort = 1; 1986 } 1987 1988 if (abort) { 1989 if (qc) 1990 ata_link_abort(qc->dev->link); 1991 else 1992 ata_port_abort(ap); 1993 } 1994 } 1995 1996 static void mv_process_crpb_response(struct ata_port *ap, 1997 struct mv_crpb *response, unsigned int tag, int ncq_enabled) 1998 { 1999 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2000 2001 if (qc) { 2002 u8 ata_status; 2003 u16 edma_status = le16_to_cpu(response->flags); 2004 /* 2005 * edma_status from a response queue entry: 2006 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 2007 * MSB is saved ATA status from command completion. 2008 */ 2009 if (!ncq_enabled) { 2010 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2011 if (err_cause) { 2012 /* 2013 * Error will be seen/handled by mv_err_intr(). 2014 * So do nothing at all here. 2015 */ 2016 return; 2017 } 2018 } 2019 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 2020 if (!ac_err_mask(ata_status)) 2021 ata_qc_complete(qc); 2022 /* else: leave it for mv_err_intr() */ 2023 } else { 2024 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2025 __func__, tag); 2026 } 2027 } 2028 2029 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2030 { 2031 void __iomem *port_mmio = mv_ap_base(ap); 2032 struct mv_host_priv *hpriv = ap->host->private_data; 2033 u32 in_index; 2034 bool work_done = false; 2035 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2036 2037 /* Get the hardware queue position index */ 2038 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 2039 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2040 2041 /* Process new responses from since the last time we looked */ 2042 while (in_index != pp->resp_idx) { 2043 unsigned int tag; 2044 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2045 2046 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2047 2048 if (IS_GEN_I(hpriv)) { 2049 /* 50xx: no NCQ, only one command active at a time */ 2050 tag = ap->link.active_tag; 2051 } else { 2052 /* Gen II/IIE: get command tag from CRPB entry */ 2053 tag = le16_to_cpu(response->id) & 0x1f; 2054 } 2055 mv_process_crpb_response(ap, response, tag, ncq_enabled); 2056 work_done = true; 2057 } 2058 2059 /* Update the software queue position index in hardware */ 2060 if (work_done) 2061 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2062 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2063 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 2064 } 2065 2066 static void mv_port_intr(struct ata_port *ap, u32 port_cause) 2067 { 2068 struct mv_port_priv *pp; 2069 int edma_was_enabled; 2070 2071 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2072 mv_unexpected_intr(ap, 0); 2073 return; 2074 } 2075 /* 2076 * Grab a snapshot of the EDMA_EN flag setting, 2077 * so that we have a consistent view for this port, 2078 * even if something we call of our routines changes it. 2079 */ 2080 pp = ap->private_data; 2081 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2082 /* 2083 * Process completed CRPB response(s) before other events. 2084 */ 2085 if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2086 mv_process_crpb_entries(ap, pp); 2087 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 2088 mv_handle_fbs_ncq_dev_err(ap); 2089 } 2090 /* 2091 * Handle chip-reported errors, or continue on to handle PIO. 2092 */ 2093 if (unlikely(port_cause & ERR_IRQ)) { 2094 mv_err_intr(ap); 2095 } else if (!edma_was_enabled) { 2096 struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2097 if (qc) 2098 ata_sff_host_intr(ap, qc); 2099 else 2100 mv_unexpected_intr(ap, edma_was_enabled); 2101 } 2102 } 2103 2104 /** 2105 * mv_host_intr - Handle all interrupts on the given host controller 2106 * @host: host specific structure 2107 * @main_irq_cause: Main interrupt cause register for the chip. 2108 * 2109 * LOCKING: 2110 * Inherited from caller. 2111 */ 2112 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 2113 { 2114 struct mv_host_priv *hpriv = host->private_data; 2115 void __iomem *mmio = hpriv->base, *hc_mmio; 2116 unsigned int handled = 0, port; 2117 2118 for (port = 0; port < hpriv->n_ports; port++) { 2119 struct ata_port *ap = host->ports[port]; 2120 unsigned int p, shift, hardport, port_cause; 2121 2122 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2123 /* 2124 * Each hc within the host has its own hc_irq_cause register, 2125 * where the interrupting ports bits get ack'd. 2126 */ 2127 if (hardport == 0) { /* first port on this hc ? */ 2128 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2129 u32 port_mask, ack_irqs; 2130 /* 2131 * Skip this entire hc if nothing pending for any ports 2132 */ 2133 if (!hc_cause) { 2134 port += MV_PORTS_PER_HC - 1; 2135 continue; 2136 } 2137 /* 2138 * We don't need/want to read the hc_irq_cause register, 2139 * because doing so hurts performance, and 2140 * main_irq_cause already gives us everything we need. 2141 * 2142 * But we do have to *write* to the hc_irq_cause to ack 2143 * the ports that we are handling this time through. 2144 * 2145 * This requires that we create a bitmap for those 2146 * ports which interrupted us, and use that bitmap 2147 * to ack (only) those ports via hc_irq_cause. 2148 */ 2149 ack_irqs = 0; 2150 for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2151 if ((port + p) >= hpriv->n_ports) 2152 break; 2153 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2154 if (hc_cause & port_mask) 2155 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2156 } 2157 hc_mmio = mv_hc_base_from_port(mmio, port); 2158 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS); 2159 handled = 1; 2160 } 2161 /* 2162 * Handle interrupts signalled for this port: 2163 */ 2164 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2165 if (port_cause) 2166 mv_port_intr(ap, port_cause); 2167 } 2168 return handled; 2169 } 2170 2171 static int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2172 { 2173 struct mv_host_priv *hpriv = host->private_data; 2174 struct ata_port *ap; 2175 struct ata_queued_cmd *qc; 2176 struct ata_eh_info *ehi; 2177 unsigned int i, err_mask, printed = 0; 2178 u32 err_cause; 2179 2180 err_cause = readl(mmio + hpriv->irq_cause_ofs); 2181 2182 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2183 err_cause); 2184 2185 DPRINTK("All regs @ PCI error\n"); 2186 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2187 2188 writelfl(0, mmio + hpriv->irq_cause_ofs); 2189 2190 for (i = 0; i < host->n_ports; i++) { 2191 ap = host->ports[i]; 2192 if (!ata_link_offline(&ap->link)) { 2193 ehi = &ap->link.eh_info; 2194 ata_ehi_clear_desc(ehi); 2195 if (!printed++) 2196 ata_ehi_push_desc(ehi, 2197 "PCI err cause 0x%08x", err_cause); 2198 err_mask = AC_ERR_HOST_BUS; 2199 ehi->action = ATA_EH_RESET; 2200 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2201 if (qc) 2202 qc->err_mask |= err_mask; 2203 else 2204 ehi->err_mask |= err_mask; 2205 2206 ata_port_freeze(ap); 2207 } 2208 } 2209 return 1; /* handled */ 2210 } 2211 2212 /** 2213 * mv_interrupt - Main interrupt event handler 2214 * @irq: unused 2215 * @dev_instance: private data; in this case the host structure 2216 * 2217 * Read the read only register to determine if any host 2218 * controllers have pending interrupts. If so, call lower level 2219 * routine to handle. Also check for PCI errors which are only 2220 * reported here. 2221 * 2222 * LOCKING: 2223 * This routine holds the host lock while processing pending 2224 * interrupts. 2225 */ 2226 static irqreturn_t mv_interrupt(int irq, void *dev_instance) 2227 { 2228 struct ata_host *host = dev_instance; 2229 struct mv_host_priv *hpriv = host->private_data; 2230 unsigned int handled = 0; 2231 u32 main_irq_cause, pending_irqs; 2232 2233 spin_lock(&host->lock); 2234 main_irq_cause = readl(hpriv->main_irq_cause_addr); 2235 pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2236 /* 2237 * Deal with cases where we either have nothing pending, or have read 2238 * a bogus register value which can indicate HW removal or PCI fault. 2239 */ 2240 if (pending_irqs && main_irq_cause != 0xffffffffU) { 2241 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2242 handled = mv_pci_error(host, hpriv->base); 2243 else 2244 handled = mv_host_intr(host, pending_irqs); 2245 } 2246 spin_unlock(&host->lock); 2247 return IRQ_RETVAL(handled); 2248 } 2249 2250 static unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2251 { 2252 unsigned int ofs; 2253 2254 switch (sc_reg_in) { 2255 case SCR_STATUS: 2256 case SCR_ERROR: 2257 case SCR_CONTROL: 2258 ofs = sc_reg_in * sizeof(u32); 2259 break; 2260 default: 2261 ofs = 0xffffffffU; 2262 break; 2263 } 2264 return ofs; 2265 } 2266 2267 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 2268 { 2269 struct mv_host_priv *hpriv = ap->host->private_data; 2270 void __iomem *mmio = hpriv->base; 2271 void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 2272 unsigned int ofs = mv5_scr_offset(sc_reg_in); 2273 2274 if (ofs != 0xffffffffU) { 2275 *val = readl(addr + ofs); 2276 return 0; 2277 } else 2278 return -EINVAL; 2279 } 2280 2281 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 2282 { 2283 struct mv_host_priv *hpriv = ap->host->private_data; 2284 void __iomem *mmio = hpriv->base; 2285 void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 2286 unsigned int ofs = mv5_scr_offset(sc_reg_in); 2287 2288 if (ofs != 0xffffffffU) { 2289 writelfl(val, addr + ofs); 2290 return 0; 2291 } else 2292 return -EINVAL; 2293 } 2294 2295 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2296 { 2297 struct pci_dev *pdev = to_pci_dev(host->dev); 2298 int early_5080; 2299 2300 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2301 2302 if (!early_5080) { 2303 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2304 tmp |= (1 << 0); 2305 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2306 } 2307 2308 mv_reset_pci_bus(host, mmio); 2309 } 2310 2311 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2312 { 2313 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); 2314 } 2315 2316 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 2317 void __iomem *mmio) 2318 { 2319 void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 2320 u32 tmp; 2321 2322 tmp = readl(phy_mmio + MV5_PHY_MODE); 2323 2324 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 2325 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 2326 } 2327 2328 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2329 { 2330 u32 tmp; 2331 2332 writel(0, mmio + MV_GPIO_PORT_CTL_OFS); 2333 2334 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 2335 2336 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2337 tmp |= ~(1 << 0); 2338 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2339 } 2340 2341 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 2342 unsigned int port) 2343 { 2344 void __iomem *phy_mmio = mv5_phy_base(mmio, port); 2345 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 2346 u32 tmp; 2347 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 2348 2349 if (fix_apm_sq) { 2350 tmp = readl(phy_mmio + MV5_LTMODE_OFS); 2351 tmp |= (1 << 19); 2352 writel(tmp, phy_mmio + MV5_LTMODE_OFS); 2353 2354 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); 2355 tmp &= ~0x3; 2356 tmp |= 0x1; 2357 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); 2358 } 2359 2360 tmp = readl(phy_mmio + MV5_PHY_MODE); 2361 tmp &= ~mask; 2362 tmp |= hpriv->signal[port].pre; 2363 tmp |= hpriv->signal[port].amps; 2364 writel(tmp, phy_mmio + MV5_PHY_MODE); 2365 } 2366 2367 2368 #undef ZERO 2369 #define ZERO(reg) writel(0, port_mmio + (reg)) 2370 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 2371 unsigned int port) 2372 { 2373 void __iomem *port_mmio = mv_port_base(mmio, port); 2374 2375 mv_reset_channel(hpriv, mmio, port); 2376 2377 ZERO(0x028); /* command */ 2378 writel(0x11f, port_mmio + EDMA_CFG_OFS); 2379 ZERO(0x004); /* timer */ 2380 ZERO(0x008); /* irq err cause */ 2381 ZERO(0x00c); /* irq err mask */ 2382 ZERO(0x010); /* rq bah */ 2383 ZERO(0x014); /* rq inp */ 2384 ZERO(0x018); /* rq outp */ 2385 ZERO(0x01c); /* respq bah */ 2386 ZERO(0x024); /* respq outp */ 2387 ZERO(0x020); /* respq inp */ 2388 ZERO(0x02c); /* test control */ 2389 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2390 } 2391 #undef ZERO 2392 2393 #define ZERO(reg) writel(0, hc_mmio + (reg)) 2394 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2395 unsigned int hc) 2396 { 2397 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2398 u32 tmp; 2399 2400 ZERO(0x00c); 2401 ZERO(0x010); 2402 ZERO(0x014); 2403 ZERO(0x018); 2404 2405 tmp = readl(hc_mmio + 0x20); 2406 tmp &= 0x1c1c1c1c; 2407 tmp |= 0x03030303; 2408 writel(tmp, hc_mmio + 0x20); 2409 } 2410 #undef ZERO 2411 2412 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2413 unsigned int n_hc) 2414 { 2415 unsigned int hc, port; 2416 2417 for (hc = 0; hc < n_hc; hc++) { 2418 for (port = 0; port < MV_PORTS_PER_HC; port++) 2419 mv5_reset_hc_port(hpriv, mmio, 2420 (hc * MV_PORTS_PER_HC) + port); 2421 2422 mv5_reset_one_hc(hpriv, mmio, hc); 2423 } 2424 2425 return 0; 2426 } 2427 2428 #undef ZERO 2429 #define ZERO(reg) writel(0, mmio + (reg)) 2430 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2431 { 2432 struct mv_host_priv *hpriv = host->private_data; 2433 u32 tmp; 2434 2435 tmp = readl(mmio + MV_PCI_MODE_OFS); 2436 tmp &= 0xff00ffff; 2437 writel(tmp, mmio + MV_PCI_MODE_OFS); 2438 2439 ZERO(MV_PCI_DISC_TIMER); 2440 ZERO(MV_PCI_MSI_TRIGGER); 2441 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 2442 ZERO(MV_PCI_SERR_MASK); 2443 ZERO(hpriv->irq_cause_ofs); 2444 ZERO(hpriv->irq_mask_ofs); 2445 ZERO(MV_PCI_ERR_LOW_ADDRESS); 2446 ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2447 ZERO(MV_PCI_ERR_ATTRIBUTE); 2448 ZERO(MV_PCI_ERR_COMMAND); 2449 } 2450 #undef ZERO 2451 2452 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2453 { 2454 u32 tmp; 2455 2456 mv5_reset_flash(hpriv, mmio); 2457 2458 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); 2459 tmp &= 0x3; 2460 tmp |= (1 << 5) | (1 << 6); 2461 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); 2462 } 2463 2464 /** 2465 * mv6_reset_hc - Perform the 6xxx global soft reset 2466 * @mmio: base address of the HBA 2467 * 2468 * This routine only applies to 6xxx parts. 2469 * 2470 * LOCKING: 2471 * Inherited from caller. 2472 */ 2473 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2474 unsigned int n_hc) 2475 { 2476 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2477 int i, rc = 0; 2478 u32 t; 2479 2480 /* Following procedure defined in PCI "main command and status 2481 * register" table. 2482 */ 2483 t = readl(reg); 2484 writel(t | STOP_PCI_MASTER, reg); 2485 2486 for (i = 0; i < 1000; i++) { 2487 udelay(1); 2488 t = readl(reg); 2489 if (PCI_MASTER_EMPTY & t) 2490 break; 2491 } 2492 if (!(PCI_MASTER_EMPTY & t)) { 2493 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2494 rc = 1; 2495 goto done; 2496 } 2497 2498 /* set reset */ 2499 i = 5; 2500 do { 2501 writel(t | GLOB_SFT_RST, reg); 2502 t = readl(reg); 2503 udelay(1); 2504 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2505 2506 if (!(GLOB_SFT_RST & t)) { 2507 printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2508 rc = 1; 2509 goto done; 2510 } 2511 2512 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2513 i = 5; 2514 do { 2515 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2516 t = readl(reg); 2517 udelay(1); 2518 } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2519 2520 if (GLOB_SFT_RST & t) { 2521 printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2522 rc = 1; 2523 } 2524 done: 2525 return rc; 2526 } 2527 2528 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2529 void __iomem *mmio) 2530 { 2531 void __iomem *port_mmio; 2532 u32 tmp; 2533 2534 tmp = readl(mmio + MV_RESET_CFG_OFS); 2535 if ((tmp & (1 << 0)) == 0) { 2536 hpriv->signal[idx].amps = 0x7 << 8; 2537 hpriv->signal[idx].pre = 0x1 << 5; 2538 return; 2539 } 2540 2541 port_mmio = mv_port_base(mmio, idx); 2542 tmp = readl(port_mmio + PHY_MODE2); 2543 2544 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2545 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2546 } 2547 2548 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2549 { 2550 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); 2551 } 2552 2553 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 2554 unsigned int port) 2555 { 2556 void __iomem *port_mmio = mv_port_base(mmio, port); 2557 2558 u32 hp_flags = hpriv->hp_flags; 2559 int fix_phy_mode2 = 2560 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2561 int fix_phy_mode4 = 2562 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2563 u32 m2, m3; 2564 2565 if (fix_phy_mode2) { 2566 m2 = readl(port_mmio + PHY_MODE2); 2567 m2 &= ~(1 << 16); 2568 m2 |= (1 << 31); 2569 writel(m2, port_mmio + PHY_MODE2); 2570 2571 udelay(200); 2572 2573 m2 = readl(port_mmio + PHY_MODE2); 2574 m2 &= ~((1 << 16) | (1 << 31)); 2575 writel(m2, port_mmio + PHY_MODE2); 2576 2577 udelay(200); 2578 } 2579 2580 /* 2581 * Gen-II/IIe PHY_MODE3 errata RM#2: 2582 * Achieves better receiver noise performance than the h/w default: 2583 */ 2584 m3 = readl(port_mmio + PHY_MODE3); 2585 m3 = (m3 & 0x1f) | (0x5555601 << 5); 2586 2587 /* Guideline 88F5182 (GL# SATA-S11) */ 2588 if (IS_SOC(hpriv)) 2589 m3 &= ~0x1c; 2590 2591 if (fix_phy_mode4) { 2592 u32 m4 = readl(port_mmio + PHY_MODE4); 2593 /* 2594 * Enforce reserved-bit restrictions on GenIIe devices only. 2595 * For earlier chipsets, force only the internal config field 2596 * (workaround for errata FEr SATA#10 part 1). 2597 */ 2598 if (IS_GEN_IIE(hpriv)) 2599 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 2600 else 2601 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 2602 writel(m4, port_mmio + PHY_MODE4); 2603 } 2604 /* 2605 * Workaround for 60x1-B2 errata SATA#13: 2606 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 2607 * so we must always rewrite PHY_MODE3 after PHY_MODE4. 2608 */ 2609 writel(m3, port_mmio + PHY_MODE3); 2610 2611 /* Revert values of pre-emphasis and signal amps to the saved ones */ 2612 m2 = readl(port_mmio + PHY_MODE2); 2613 2614 m2 &= ~MV_M2_PREAMP_MASK; 2615 m2 |= hpriv->signal[port].amps; 2616 m2 |= hpriv->signal[port].pre; 2617 m2 &= ~(1 << 16); 2618 2619 /* according to mvSata 3.6.1, some IIE values are fixed */ 2620 if (IS_GEN_IIE(hpriv)) { 2621 m2 &= ~0xC30FF01F; 2622 m2 |= 0x0000900F; 2623 } 2624 2625 writel(m2, port_mmio + PHY_MODE2); 2626 } 2627 2628 /* TODO: use the generic LED interface to configure the SATA Presence */ 2629 /* & Acitivy LEDs on the board */ 2630 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2631 void __iomem *mmio) 2632 { 2633 return; 2634 } 2635 2636 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2637 void __iomem *mmio) 2638 { 2639 void __iomem *port_mmio; 2640 u32 tmp; 2641 2642 port_mmio = mv_port_base(mmio, idx); 2643 tmp = readl(port_mmio + PHY_MODE2); 2644 2645 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2646 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2647 } 2648 2649 #undef ZERO 2650 #define ZERO(reg) writel(0, port_mmio + (reg)) 2651 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2652 void __iomem *mmio, unsigned int port) 2653 { 2654 void __iomem *port_mmio = mv_port_base(mmio, port); 2655 2656 mv_reset_channel(hpriv, mmio, port); 2657 2658 ZERO(0x028); /* command */ 2659 writel(0x101f, port_mmio + EDMA_CFG_OFS); 2660 ZERO(0x004); /* timer */ 2661 ZERO(0x008); /* irq err cause */ 2662 ZERO(0x00c); /* irq err mask */ 2663 ZERO(0x010); /* rq bah */ 2664 ZERO(0x014); /* rq inp */ 2665 ZERO(0x018); /* rq outp */ 2666 ZERO(0x01c); /* respq bah */ 2667 ZERO(0x024); /* respq outp */ 2668 ZERO(0x020); /* respq inp */ 2669 ZERO(0x02c); /* test control */ 2670 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2671 } 2672 2673 #undef ZERO 2674 2675 #define ZERO(reg) writel(0, hc_mmio + (reg)) 2676 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2677 void __iomem *mmio) 2678 { 2679 void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2680 2681 ZERO(0x00c); 2682 ZERO(0x010); 2683 ZERO(0x014); 2684 2685 } 2686 2687 #undef ZERO 2688 2689 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2690 void __iomem *mmio, unsigned int n_hc) 2691 { 2692 unsigned int port; 2693 2694 for (port = 0; port < hpriv->n_ports; port++) 2695 mv_soc_reset_hc_port(hpriv, mmio, port); 2696 2697 mv_soc_reset_one_hc(hpriv, mmio); 2698 2699 return 0; 2700 } 2701 2702 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2703 void __iomem *mmio) 2704 { 2705 return; 2706 } 2707 2708 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2709 { 2710 return; 2711 } 2712 2713 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 2714 { 2715 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); 2716 2717 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 2718 if (want_gen2i) 2719 ifcfg |= (1 << 7); /* enable gen2i speed */ 2720 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); 2721 } 2722 2723 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2724 unsigned int port_no) 2725 { 2726 void __iomem *port_mmio = mv_port_base(mmio, port_no); 2727 2728 /* 2729 * The datasheet warns against setting EDMA_RESET when EDMA is active 2730 * (but doesn't say what the problem might be). So we first try 2731 * to disable the EDMA engine before doing the EDMA_RESET operation. 2732 */ 2733 mv_stop_edma_engine(port_mmio); 2734 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2735 2736 if (!IS_GEN_I(hpriv)) { 2737 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 2738 mv_setup_ifcfg(port_mmio, 1); 2739 } 2740 /* 2741 * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 2742 * link, and physical layers. It resets all SATA interface registers 2743 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2744 */ 2745 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2746 udelay(25); /* allow reset propagation */ 2747 writelfl(0, port_mmio + EDMA_CMD_OFS); 2748 2749 hpriv->ops->phy_errata(hpriv, mmio, port_no); 2750 2751 if (IS_GEN_I(hpriv)) 2752 mdelay(1); 2753 } 2754 2755 static void mv_pmp_select(struct ata_port *ap, int pmp) 2756 { 2757 if (sata_pmp_supported(ap)) { 2758 void __iomem *port_mmio = mv_ap_base(ap); 2759 u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2760 int old = reg & 0xf; 2761 2762 if (old != pmp) { 2763 reg = (reg & ~0xf) | pmp; 2764 writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2765 } 2766 } 2767 } 2768 2769 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2770 unsigned long deadline) 2771 { 2772 mv_pmp_select(link->ap, sata_srst_pmp(link)); 2773 return sata_std_hardreset(link, class, deadline); 2774 } 2775 2776 static int mv_softreset(struct ata_link *link, unsigned int *class, 2777 unsigned long deadline) 2778 { 2779 mv_pmp_select(link->ap, sata_srst_pmp(link)); 2780 return ata_sff_softreset(link, class, deadline); 2781 } 2782 2783 static int mv_hardreset(struct ata_link *link, unsigned int *class, 2784 unsigned long deadline) 2785 { 2786 struct ata_port *ap = link->ap; 2787 struct mv_host_priv *hpriv = ap->host->private_data; 2788 struct mv_port_priv *pp = ap->private_data; 2789 void __iomem *mmio = hpriv->base; 2790 int rc, attempts = 0, extra = 0; 2791 u32 sstatus; 2792 bool online; 2793 2794 mv_reset_channel(hpriv, mmio, ap->port_no); 2795 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2796 2797 /* Workaround for errata FEr SATA#10 (part 2) */ 2798 do { 2799 const unsigned long *timing = 2800 sata_ehc_deb_timing(&link->eh_context); 2801 2802 rc = sata_link_hardreset(link, timing, deadline + extra, 2803 &online, NULL); 2804 rc = online ? -EAGAIN : rc; 2805 if (rc) 2806 return rc; 2807 sata_scr_read(link, SCR_STATUS, &sstatus); 2808 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 2809 /* Force 1.5gb/s link speed and try again */ 2810 mv_setup_ifcfg(mv_ap_base(ap), 0); 2811 if (time_after(jiffies + HZ, deadline)) 2812 extra = HZ; /* only extend it once, max */ 2813 } 2814 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2815 2816 return rc; 2817 } 2818 2819 static void mv_eh_freeze(struct ata_port *ap) 2820 { 2821 mv_stop_edma(ap); 2822 mv_enable_port_irqs(ap, 0); 2823 } 2824 2825 static void mv_eh_thaw(struct ata_port *ap) 2826 { 2827 struct mv_host_priv *hpriv = ap->host->private_data; 2828 unsigned int port = ap->port_no; 2829 unsigned int hardport = mv_hardport_from_port(port); 2830 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 2831 void __iomem *port_mmio = mv_ap_base(ap); 2832 u32 hc_irq_cause; 2833 2834 /* clear EDMA errors on this port */ 2835 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2836 2837 /* clear pending irq events */ 2838 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 2839 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); 2840 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2841 2842 mv_enable_port_irqs(ap, ERR_IRQ); 2843 } 2844 2845 /** 2846 * mv_port_init - Perform some early initialization on a single port. 2847 * @port: libata data structure storing shadow register addresses 2848 * @port_mmio: base address of the port 2849 * 2850 * Initialize shadow register mmio addresses, clear outstanding 2851 * interrupts on the port, and unmask interrupts for the future 2852 * start of the port. 2853 * 2854 * LOCKING: 2855 * Inherited from caller. 2856 */ 2857 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 2858 { 2859 void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 2860 unsigned serr_ofs; 2861 2862 /* PIO related setup 2863 */ 2864 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 2865 port->error_addr = 2866 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 2867 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 2868 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 2869 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 2870 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 2871 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 2872 port->status_addr = 2873 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 2874 /* special case: control/altstatus doesn't have ATA_REG_ address */ 2875 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 2876 2877 /* unused: */ 2878 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 2879 2880 /* Clear any currently outstanding port interrupt conditions */ 2881 serr_ofs = mv_scr_offset(SCR_ERROR); 2882 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 2883 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2884 2885 /* unmask all non-transient EDMA error interrupts */ 2886 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 2887 2888 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 2889 readl(port_mmio + EDMA_CFG_OFS), 2890 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 2891 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 2892 } 2893 2894 static unsigned int mv_in_pcix_mode(struct ata_host *host) 2895 { 2896 struct mv_host_priv *hpriv = host->private_data; 2897 void __iomem *mmio = hpriv->base; 2898 u32 reg; 2899 2900 if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 2901 return 0; /* not PCI-X capable */ 2902 reg = readl(mmio + MV_PCI_MODE_OFS); 2903 if ((reg & MV_PCI_MODE_MASK) == 0) 2904 return 0; /* conventional PCI mode */ 2905 return 1; /* chip is in PCI-X mode */ 2906 } 2907 2908 static int mv_pci_cut_through_okay(struct ata_host *host) 2909 { 2910 struct mv_host_priv *hpriv = host->private_data; 2911 void __iomem *mmio = hpriv->base; 2912 u32 reg; 2913 2914 if (!mv_in_pcix_mode(host)) { 2915 reg = readl(mmio + PCI_COMMAND_OFS); 2916 if (reg & PCI_COMMAND_MRDTRIG) 2917 return 0; /* not okay */ 2918 } 2919 return 1; /* okay */ 2920 } 2921 2922 static int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2923 { 2924 struct pci_dev *pdev = to_pci_dev(host->dev); 2925 struct mv_host_priv *hpriv = host->private_data; 2926 u32 hp_flags = hpriv->hp_flags; 2927 2928 switch (board_idx) { 2929 case chip_5080: 2930 hpriv->ops = &mv5xxx_ops; 2931 hp_flags |= MV_HP_GEN_I; 2932 2933 switch (pdev->revision) { 2934 case 0x1: 2935 hp_flags |= MV_HP_ERRATA_50XXB0; 2936 break; 2937 case 0x3: 2938 hp_flags |= MV_HP_ERRATA_50XXB2; 2939 break; 2940 default: 2941 dev_printk(KERN_WARNING, &pdev->dev, 2942 "Applying 50XXB2 workarounds to unknown rev\n"); 2943 hp_flags |= MV_HP_ERRATA_50XXB2; 2944 break; 2945 } 2946 break; 2947 2948 case chip_504x: 2949 case chip_508x: 2950 hpriv->ops = &mv5xxx_ops; 2951 hp_flags |= MV_HP_GEN_I; 2952 2953 switch (pdev->revision) { 2954 case 0x0: 2955 hp_flags |= MV_HP_ERRATA_50XXB0; 2956 break; 2957 case 0x3: 2958 hp_flags |= MV_HP_ERRATA_50XXB2; 2959 break; 2960 default: 2961 dev_printk(KERN_WARNING, &pdev->dev, 2962 "Applying B2 workarounds to unknown rev\n"); 2963 hp_flags |= MV_HP_ERRATA_50XXB2; 2964 break; 2965 } 2966 break; 2967 2968 case chip_604x: 2969 case chip_608x: 2970 hpriv->ops = &mv6xxx_ops; 2971 hp_flags |= MV_HP_GEN_II; 2972 2973 switch (pdev->revision) { 2974 case 0x7: 2975 hp_flags |= MV_HP_ERRATA_60X1B2; 2976 break; 2977 case 0x9: 2978 hp_flags |= MV_HP_ERRATA_60X1C0; 2979 break; 2980 default: 2981 dev_printk(KERN_WARNING, &pdev->dev, 2982 "Applying B2 workarounds to unknown rev\n"); 2983 hp_flags |= MV_HP_ERRATA_60X1B2; 2984 break; 2985 } 2986 break; 2987 2988 case chip_7042: 2989 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 2990 if (pdev->vendor == PCI_VENDOR_ID_TTI && 2991 (pdev->device == 0x2300 || pdev->device == 0x2310)) 2992 { 2993 /* 2994 * Highpoint RocketRAID PCIe 23xx series cards: 2995 * 2996 * Unconfigured drives are treated as "Legacy" 2997 * by the BIOS, and it overwrites sector 8 with 2998 * a "Lgcy" metadata block prior to Linux boot. 2999 * 3000 * Configured drives (RAID or JBOD) leave sector 8 3001 * alone, but instead overwrite a high numbered 3002 * sector for the RAID metadata. This sector can 3003 * be determined exactly, by truncating the physical 3004 * drive capacity to a nice even GB value. 3005 * 3006 * RAID metadata is at: (dev->n_sectors & ~0xfffff) 3007 * 3008 * Warn the user, lest they think we're just buggy. 3009 */ 3010 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 3011 " BIOS CORRUPTS DATA on all attached drives," 3012 " regardless of if/how they are configured." 3013 " BEWARE!\n"); 3014 printk(KERN_WARNING DRV_NAME ": For data safety, do not" 3015 " use sectors 8-9 on \"Legacy\" drives," 3016 " and avoid the final two gigabytes on" 3017 " all RocketRAID BIOS initialized drives.\n"); 3018 } 3019 /* drop through */ 3020 case chip_6042: 3021 hpriv->ops = &mv6xxx_ops; 3022 hp_flags |= MV_HP_GEN_IIE; 3023 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3024 hp_flags |= MV_HP_CUT_THROUGH; 3025 3026 switch (pdev->revision) { 3027 case 0x2: /* Rev.B0: the first/only public release */ 3028 hp_flags |= MV_HP_ERRATA_60X1C0; 3029 break; 3030 default: 3031 dev_printk(KERN_WARNING, &pdev->dev, 3032 "Applying 60X1C0 workarounds to unknown rev\n"); 3033 hp_flags |= MV_HP_ERRATA_60X1C0; 3034 break; 3035 } 3036 break; 3037 case chip_soc: 3038 hpriv->ops = &mv_soc_ops; 3039 hp_flags |= MV_HP_FLAG_SOC | MV_HP_ERRATA_60X1C0; 3040 break; 3041 3042 default: 3043 dev_printk(KERN_ERR, host->dev, 3044 "BUG: invalid board index %u\n", board_idx); 3045 return 1; 3046 } 3047 3048 hpriv->hp_flags = hp_flags; 3049 if (hp_flags & MV_HP_PCIE) { 3050 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 3051 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 3052 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 3053 } else { 3054 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 3055 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 3056 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 3057 } 3058 3059 return 0; 3060 } 3061 3062 /** 3063 * mv_init_host - Perform some early initialization of the host. 3064 * @host: ATA host to initialize 3065 * @board_idx: controller index 3066 * 3067 * If possible, do an early global reset of the host. Then do 3068 * our port init and clear/unmask all/relevant host interrupts. 3069 * 3070 * LOCKING: 3071 * Inherited from caller. 3072 */ 3073 static int mv_init_host(struct ata_host *host, unsigned int board_idx) 3074 { 3075 int rc = 0, n_hc, port, hc; 3076 struct mv_host_priv *hpriv = host->private_data; 3077 void __iomem *mmio = hpriv->base; 3078 3079 rc = mv_chip_id(host, board_idx); 3080 if (rc) 3081 goto done; 3082 3083 if (IS_SOC(hpriv)) { 3084 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 3085 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 3086 } else { 3087 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; 3088 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 3089 } 3090 3091 /* global interrupt mask: 0 == mask everything */ 3092 mv_set_main_irq_mask(host, ~0, 0); 3093 3094 n_hc = mv_get_hc_count(host->ports[0]->flags); 3095 3096 for (port = 0; port < host->n_ports; port++) 3097 hpriv->ops->read_preamp(hpriv, port, mmio); 3098 3099 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 3100 if (rc) 3101 goto done; 3102 3103 hpriv->ops->reset_flash(hpriv, mmio); 3104 hpriv->ops->reset_bus(host, mmio); 3105 hpriv->ops->enable_leds(hpriv, mmio); 3106 3107 for (port = 0; port < host->n_ports; port++) { 3108 struct ata_port *ap = host->ports[port]; 3109 void __iomem *port_mmio = mv_port_base(mmio, port); 3110 3111 mv_port_init(&ap->ioaddr, port_mmio); 3112 3113 #ifdef CONFIG_PCI 3114 if (!IS_SOC(hpriv)) { 3115 unsigned int offset = port_mmio - mmio; 3116 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3117 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3118 } 3119 #endif 3120 } 3121 3122 for (hc = 0; hc < n_hc; hc++) { 3123 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3124 3125 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 3126 "(before clear)=0x%08x\n", hc, 3127 readl(hc_mmio + HC_CFG_OFS), 3128 readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 3129 3130 /* Clear any currently outstanding hc interrupt conditions */ 3131 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 3132 } 3133 3134 if (!IS_SOC(hpriv)) { 3135 /* Clear any currently outstanding host interrupt conditions */ 3136 writelfl(0, mmio + hpriv->irq_cause_ofs); 3137 3138 /* and unmask interrupt generation for host regs */ 3139 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 3140 3141 /* 3142 * enable only global host interrupts for now. 3143 * The per-port interrupts get done later as ports are set up. 3144 */ 3145 mv_set_main_irq_mask(host, 0, PCI_ERR); 3146 } 3147 done: 3148 return rc; 3149 } 3150 3151 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3152 { 3153 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3154 MV_CRQB_Q_SZ, 0); 3155 if (!hpriv->crqb_pool) 3156 return -ENOMEM; 3157 3158 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3159 MV_CRPB_Q_SZ, 0); 3160 if (!hpriv->crpb_pool) 3161 return -ENOMEM; 3162 3163 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3164 MV_SG_TBL_SZ, 0); 3165 if (!hpriv->sg_tbl_pool) 3166 return -ENOMEM; 3167 3168 return 0; 3169 } 3170 3171 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 3172 struct mbus_dram_target_info *dram) 3173 { 3174 int i; 3175 3176 for (i = 0; i < 4; i++) { 3177 writel(0, hpriv->base + WINDOW_CTRL(i)); 3178 writel(0, hpriv->base + WINDOW_BASE(i)); 3179 } 3180 3181 for (i = 0; i < dram->num_cs; i++) { 3182 struct mbus_dram_window *cs = dram->cs + i; 3183 3184 writel(((cs->size - 1) & 0xffff0000) | 3185 (cs->mbus_attr << 8) | 3186 (dram->mbus_dram_target_id << 4) | 1, 3187 hpriv->base + WINDOW_CTRL(i)); 3188 writel(cs->base, hpriv->base + WINDOW_BASE(i)); 3189 } 3190 } 3191 3192 /** 3193 * mv_platform_probe - handle a positive probe of an soc Marvell 3194 * host 3195 * @pdev: platform device found 3196 * 3197 * LOCKING: 3198 * Inherited from caller. 3199 */ 3200 static int mv_platform_probe(struct platform_device *pdev) 3201 { 3202 static int printed_version; 3203 const struct mv_sata_platform_data *mv_platform_data; 3204 const struct ata_port_info *ppi[] = 3205 { &mv_port_info[chip_soc], NULL }; 3206 struct ata_host *host; 3207 struct mv_host_priv *hpriv; 3208 struct resource *res; 3209 int n_ports, rc; 3210 3211 if (!printed_version++) 3212 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3213 3214 /* 3215 * Simple resource validation .. 3216 */ 3217 if (unlikely(pdev->num_resources != 2)) { 3218 dev_err(&pdev->dev, "invalid number of resources\n"); 3219 return -EINVAL; 3220 } 3221 3222 /* 3223 * Get the register base first 3224 */ 3225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3226 if (res == NULL) 3227 return -EINVAL; 3228 3229 /* allocate host */ 3230 mv_platform_data = pdev->dev.platform_data; 3231 n_ports = mv_platform_data->n_ports; 3232 3233 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3234 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3235 3236 if (!host || !hpriv) 3237 return -ENOMEM; 3238 host->private_data = hpriv; 3239 hpriv->n_ports = n_ports; 3240 3241 host->iomap = NULL; 3242 hpriv->base = devm_ioremap(&pdev->dev, res->start, 3243 res->end - res->start + 1); 3244 hpriv->base -= MV_SATAHC0_REG_BASE; 3245 3246 /* 3247 * (Re-)program MBUS remapping windows if we are asked to. 3248 */ 3249 if (mv_platform_data->dram != NULL) 3250 mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 3251 3252 rc = mv_create_dma_pools(hpriv, &pdev->dev); 3253 if (rc) 3254 return rc; 3255 3256 /* initialize adapter */ 3257 rc = mv_init_host(host, chip_soc); 3258 if (rc) 3259 return rc; 3260 3261 dev_printk(KERN_INFO, &pdev->dev, 3262 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3263 host->n_ports); 3264 3265 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3266 IRQF_SHARED, &mv6_sht); 3267 } 3268 3269 /* 3270 * 3271 * mv_platform_remove - unplug a platform interface 3272 * @pdev: platform device 3273 * 3274 * A platform bus SATA device has been unplugged. Perform the needed 3275 * cleanup. Also called on module unload for any active devices. 3276 */ 3277 static int __devexit mv_platform_remove(struct platform_device *pdev) 3278 { 3279 struct device *dev = &pdev->dev; 3280 struct ata_host *host = dev_get_drvdata(dev); 3281 3282 ata_host_detach(host); 3283 return 0; 3284 } 3285 3286 static struct platform_driver mv_platform_driver = { 3287 .probe = mv_platform_probe, 3288 .remove = __devexit_p(mv_platform_remove), 3289 .driver = { 3290 .name = DRV_NAME, 3291 .owner = THIS_MODULE, 3292 }, 3293 }; 3294 3295 3296 #ifdef CONFIG_PCI 3297 static int mv_pci_init_one(struct pci_dev *pdev, 3298 const struct pci_device_id *ent); 3299 3300 3301 static struct pci_driver mv_pci_driver = { 3302 .name = DRV_NAME, 3303 .id_table = mv_pci_tbl, 3304 .probe = mv_pci_init_one, 3305 .remove = ata_pci_remove_one, 3306 }; 3307 3308 /* 3309 * module options 3310 */ 3311 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 3312 3313 3314 /* move to PCI layer or libata core? */ 3315 static int pci_go_64(struct pci_dev *pdev) 3316 { 3317 int rc; 3318 3319 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 3320 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 3321 if (rc) { 3322 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 3323 if (rc) { 3324 dev_printk(KERN_ERR, &pdev->dev, 3325 "64-bit DMA enable failed\n"); 3326 return rc; 3327 } 3328 } 3329 } else { 3330 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 3331 if (rc) { 3332 dev_printk(KERN_ERR, &pdev->dev, 3333 "32-bit DMA enable failed\n"); 3334 return rc; 3335 } 3336 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 3337 if (rc) { 3338 dev_printk(KERN_ERR, &pdev->dev, 3339 "32-bit consistent DMA enable failed\n"); 3340 return rc; 3341 } 3342 } 3343 3344 return rc; 3345 } 3346 3347 /** 3348 * mv_print_info - Dump key info to kernel log for perusal. 3349 * @host: ATA host to print info about 3350 * 3351 * FIXME: complete this. 3352 * 3353 * LOCKING: 3354 * Inherited from caller. 3355 */ 3356 static void mv_print_info(struct ata_host *host) 3357 { 3358 struct pci_dev *pdev = to_pci_dev(host->dev); 3359 struct mv_host_priv *hpriv = host->private_data; 3360 u8 scc; 3361 const char *scc_s, *gen; 3362 3363 /* Use this to determine the HW stepping of the chip so we know 3364 * what errata to workaround 3365 */ 3366 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 3367 if (scc == 0) 3368 scc_s = "SCSI"; 3369 else if (scc == 0x01) 3370 scc_s = "RAID"; 3371 else 3372 scc_s = "?"; 3373 3374 if (IS_GEN_I(hpriv)) 3375 gen = "I"; 3376 else if (IS_GEN_II(hpriv)) 3377 gen = "II"; 3378 else if (IS_GEN_IIE(hpriv)) 3379 gen = "IIE"; 3380 else 3381 gen = "?"; 3382 3383 dev_printk(KERN_INFO, &pdev->dev, 3384 "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 3385 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 3386 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 3387 } 3388 3389 /** 3390 * mv_pci_init_one - handle a positive probe of a PCI Marvell host 3391 * @pdev: PCI device found 3392 * @ent: PCI device ID entry for the matched host 3393 * 3394 * LOCKING: 3395 * Inherited from caller. 3396 */ 3397 static int mv_pci_init_one(struct pci_dev *pdev, 3398 const struct pci_device_id *ent) 3399 { 3400 static int printed_version; 3401 unsigned int board_idx = (unsigned int)ent->driver_data; 3402 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 3403 struct ata_host *host; 3404 struct mv_host_priv *hpriv; 3405 int n_ports, rc; 3406 3407 if (!printed_version++) 3408 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3409 3410 /* allocate host */ 3411 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 3412 3413 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3414 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3415 if (!host || !hpriv) 3416 return -ENOMEM; 3417 host->private_data = hpriv; 3418 hpriv->n_ports = n_ports; 3419 3420 /* acquire resources */ 3421 rc = pcim_enable_device(pdev); 3422 if (rc) 3423 return rc; 3424 3425 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 3426 if (rc == -EBUSY) 3427 pcim_pin_device(pdev); 3428 if (rc) 3429 return rc; 3430 host->iomap = pcim_iomap_table(pdev); 3431 hpriv->base = host->iomap[MV_PRIMARY_BAR]; 3432 3433 rc = pci_go_64(pdev); 3434 if (rc) 3435 return rc; 3436 3437 rc = mv_create_dma_pools(hpriv, &pdev->dev); 3438 if (rc) 3439 return rc; 3440 3441 /* initialize adapter */ 3442 rc = mv_init_host(host, board_idx); 3443 if (rc) 3444 return rc; 3445 3446 /* Enable interrupts */ 3447 if (msi && pci_enable_msi(pdev)) 3448 pci_intx(pdev, 1); 3449 3450 mv_dump_pci_cfg(pdev, 0x68); 3451 mv_print_info(host); 3452 3453 pci_set_master(pdev); 3454 pci_try_set_mwi(pdev); 3455 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3456 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 3457 } 3458 #endif 3459 3460 static int mv_platform_probe(struct platform_device *pdev); 3461 static int __devexit mv_platform_remove(struct platform_device *pdev); 3462 3463 static int __init mv_init(void) 3464 { 3465 int rc = -ENODEV; 3466 #ifdef CONFIG_PCI 3467 rc = pci_register_driver(&mv_pci_driver); 3468 if (rc < 0) 3469 return rc; 3470 #endif 3471 rc = platform_driver_register(&mv_platform_driver); 3472 3473 #ifdef CONFIG_PCI 3474 if (rc < 0) 3475 pci_unregister_driver(&mv_pci_driver); 3476 #endif 3477 return rc; 3478 } 3479 3480 static void __exit mv_exit(void) 3481 { 3482 #ifdef CONFIG_PCI 3483 pci_unregister_driver(&mv_pci_driver); 3484 #endif 3485 platform_driver_unregister(&mv_platform_driver); 3486 } 3487 3488 MODULE_AUTHOR("Brett Russ"); 3489 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 3490 MODULE_LICENSE("GPL"); 3491 MODULE_DEVICE_TABLE(pci, mv_pci_tbl); 3492 MODULE_VERSION(DRV_VERSION); 3493 MODULE_ALIAS("platform:" DRV_NAME); 3494 3495 #ifdef CONFIG_PCI 3496 module_param(msi, int, 0444); 3497 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 3498 #endif 3499 3500 module_init(mv_init); 3501 module_exit(mv_exit); 3502