1 /* 2 * sata_inic162x.c - Driver for Initio 162x SATA controllers 3 * 4 * Copyright 2006 SUSE Linux Products GmbH 5 * Copyright 2006 Tejun Heo <teheo@novell.com> 6 * 7 * This file is released under GPL v2. 8 * 9 * This controller is eccentric and easily locks up if something isn't 10 * right. Documentation is available at initio's website but it only 11 * documents registers (not programming model). 12 * 13 * This driver has interesting history. The first version was written 14 * from the documentation and a 2.4 IDE driver posted on a Taiwan 15 * company, which didn't use any IDMA features and couldn't handle 16 * LBA48. The resulting driver couldn't handle LBA48 devices either 17 * making it pretty useless. 18 * 19 * After a while, initio picked the driver up, renamed it to 20 * sata_initio162x, updated it to use IDMA for ATA DMA commands and 21 * posted it on their website. It only used ATA_PROT_DMA for IDMA and 22 * attaching both devices and issuing IDMA and !IDMA commands 23 * simultaneously broke it due to PIRQ masking interaction but it did 24 * show how to use the IDMA (ADMA + some initio specific twists) 25 * engine. 26 * 27 * Then, I picked up their changes again and here's the usable driver 28 * which uses IDMA for everything. Everything works now including 29 * LBA48, CD/DVD burning, suspend/resume and hotplug. There are some 30 * issues tho. Result Tf is not resported properly, NCQ isn't 31 * supported yet and CD/DVD writing works with DMA assisted PIO 32 * protocol (which, for native SATA devices, shouldn't cause any 33 * noticeable difference). 34 * 35 * Anyways, so, here's finally a working driver for inic162x. Enjoy! 36 * 37 * initio: If you guys wanna improve the driver regarding result TF 38 * access and other stuff, please feel free to contact me. I'll be 39 * happy to assist. 40 */ 41 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/pci.h> 45 #include <scsi/scsi_host.h> 46 #include <linux/libata.h> 47 #include <linux/blkdev.h> 48 #include <scsi/scsi_device.h> 49 50 #define DRV_NAME "sata_inic162x" 51 #define DRV_VERSION "0.4" 52 53 enum { 54 MMIO_BAR_PCI = 5, 55 MMIO_BAR_CARDBUS = 1, 56 57 NR_PORTS = 2, 58 59 IDMA_CPB_TBL_SIZE = 4 * 32, 60 61 INIC_DMA_BOUNDARY = 0xffffff, 62 63 HOST_ACTRL = 0x08, 64 HOST_CTL = 0x7c, 65 HOST_STAT = 0x7e, 66 HOST_IRQ_STAT = 0xbc, 67 HOST_IRQ_MASK = 0xbe, 68 69 PORT_SIZE = 0x40, 70 71 /* registers for ATA TF operation */ 72 PORT_TF_DATA = 0x00, 73 PORT_TF_FEATURE = 0x01, 74 PORT_TF_NSECT = 0x02, 75 PORT_TF_LBAL = 0x03, 76 PORT_TF_LBAM = 0x04, 77 PORT_TF_LBAH = 0x05, 78 PORT_TF_DEVICE = 0x06, 79 PORT_TF_COMMAND = 0x07, 80 PORT_TF_ALT_STAT = 0x08, 81 PORT_IRQ_STAT = 0x09, 82 PORT_IRQ_MASK = 0x0a, 83 PORT_PRD_CTL = 0x0b, 84 PORT_PRD_ADDR = 0x0c, 85 PORT_PRD_XFERLEN = 0x10, 86 PORT_CPB_CPBLAR = 0x18, 87 PORT_CPB_PTQFIFO = 0x1c, 88 89 /* IDMA register */ 90 PORT_IDMA_CTL = 0x14, 91 PORT_IDMA_STAT = 0x16, 92 93 PORT_RPQ_FIFO = 0x1e, 94 PORT_RPQ_CNT = 0x1f, 95 96 PORT_SCR = 0x20, 97 98 /* HOST_CTL bits */ 99 HCTL_LEDEN = (1 << 3), /* enable LED operation */ 100 HCTL_IRQOFF = (1 << 8), /* global IRQ off */ 101 HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */ 102 HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/ 103 HCTL_PWRDWN = (1 << 12), /* power down PHYs */ 104 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ 105 HCTL_RPGSEL = (1 << 15), /* register page select */ 106 107 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | 108 HCTL_RPGSEL, 109 110 /* HOST_IRQ_(STAT|MASK) bits */ 111 HIRQ_PORT0 = (1 << 0), 112 HIRQ_PORT1 = (1 << 1), 113 HIRQ_SOFT = (1 << 14), 114 HIRQ_GLOBAL = (1 << 15), /* STAT only */ 115 116 /* PORT_IRQ_(STAT|MASK) bits */ 117 PIRQ_OFFLINE = (1 << 0), /* device unplugged */ 118 PIRQ_ONLINE = (1 << 1), /* device plugged */ 119 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ 120 PIRQ_FATAL = (1 << 3), /* fatal error */ 121 PIRQ_ATA = (1 << 4), /* ATA interrupt */ 122 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ 123 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ 124 125 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, 126 PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA, 127 PIRQ_MASK_FREEZE = 0xff, 128 129 /* PORT_PRD_CTL bits */ 130 PRD_CTL_START = (1 << 0), 131 PRD_CTL_WR = (1 << 3), 132 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ 133 134 /* PORT_IDMA_CTL bits */ 135 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ 136 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */ 137 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ 138 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ 139 140 /* PORT_IDMA_STAT bits */ 141 IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */ 142 IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */ 143 IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */ 144 IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */ 145 IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */ 146 IDMA_STAT_PSD = (1 << 6), /* ADMA pause */ 147 IDMA_STAT_DONE = (1 << 7), /* ADMA done */ 148 149 IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR, 150 151 /* CPB Control Flags*/ 152 CPB_CTL_VALID = (1 << 0), /* CPB valid */ 153 CPB_CTL_QUEUED = (1 << 1), /* queued command */ 154 CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */ 155 CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */ 156 CPB_CTL_DEVDIR = (1 << 4), /* device direction control */ 157 158 /* CPB Response Flags */ 159 CPB_RESP_DONE = (1 << 0), /* ATA command complete */ 160 CPB_RESP_REL = (1 << 1), /* ATA release */ 161 CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */ 162 CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */ 163 CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */ 164 CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */ 165 CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */ 166 CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */ 167 168 /* PRD Control Flags */ 169 PRD_DRAIN = (1 << 1), /* ignore data excess */ 170 PRD_CDB = (1 << 2), /* atapi packet command pointer */ 171 PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */ 172 PRD_DMA = (1 << 4), /* data transfer method */ 173 PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */ 174 PRD_IOM = (1 << 6), /* io/memory transfer */ 175 PRD_END = (1 << 7), /* APRD chain end */ 176 }; 177 178 /* Comman Parameter Block */ 179 struct inic_cpb { 180 u8 resp_flags; /* Response Flags */ 181 u8 error; /* ATA Error */ 182 u8 status; /* ATA Status */ 183 u8 ctl_flags; /* Control Flags */ 184 __le32 len; /* Total Transfer Length */ 185 __le32 prd; /* First PRD pointer */ 186 u8 rsvd[4]; 187 /* 16 bytes */ 188 u8 feature; /* ATA Feature */ 189 u8 hob_feature; /* ATA Ex. Feature */ 190 u8 device; /* ATA Device/Head */ 191 u8 mirctl; /* Mirror Control */ 192 u8 nsect; /* ATA Sector Count */ 193 u8 hob_nsect; /* ATA Ex. Sector Count */ 194 u8 lbal; /* ATA Sector Number */ 195 u8 hob_lbal; /* ATA Ex. Sector Number */ 196 u8 lbam; /* ATA Cylinder Low */ 197 u8 hob_lbam; /* ATA Ex. Cylinder Low */ 198 u8 lbah; /* ATA Cylinder High */ 199 u8 hob_lbah; /* ATA Ex. Cylinder High */ 200 u8 command; /* ATA Command */ 201 u8 ctl; /* ATA Control */ 202 u8 slave_error; /* Slave ATA Error */ 203 u8 slave_status; /* Slave ATA Status */ 204 /* 32 bytes */ 205 } __packed; 206 207 /* Physical Region Descriptor */ 208 struct inic_prd { 209 __le32 mad; /* Physical Memory Address */ 210 __le16 len; /* Transfer Length */ 211 u8 rsvd; 212 u8 flags; /* Control Flags */ 213 } __packed; 214 215 struct inic_pkt { 216 struct inic_cpb cpb; 217 struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */ 218 u8 cdb[ATAPI_CDB_LEN]; 219 } __packed; 220 221 struct inic_host_priv { 222 void __iomem *mmio_base; 223 u16 cached_hctl; 224 }; 225 226 struct inic_port_priv { 227 struct inic_pkt *pkt; 228 dma_addr_t pkt_dma; 229 u32 *cpb_tbl; 230 dma_addr_t cpb_tbl_dma; 231 }; 232 233 static struct scsi_host_template inic_sht = { 234 ATA_BASE_SHT(DRV_NAME), 235 .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */ 236 .dma_boundary = INIC_DMA_BOUNDARY, 237 }; 238 239 static const int scr_map[] = { 240 [SCR_STATUS] = 0, 241 [SCR_ERROR] = 1, 242 [SCR_CONTROL] = 2, 243 }; 244 245 static void __iomem *inic_port_base(struct ata_port *ap) 246 { 247 struct inic_host_priv *hpriv = ap->host->private_data; 248 249 return hpriv->mmio_base + ap->port_no * PORT_SIZE; 250 } 251 252 static void inic_reset_port(void __iomem *port_base) 253 { 254 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; 255 256 /* stop IDMA engine */ 257 readw(idma_ctl); /* flush */ 258 msleep(1); 259 260 /* mask IRQ and assert reset */ 261 writew(IDMA_CTL_RST_IDMA, idma_ctl); 262 readw(idma_ctl); /* flush */ 263 msleep(1); 264 265 /* release reset */ 266 writew(0, idma_ctl); 267 268 /* clear irq */ 269 writeb(0xff, port_base + PORT_IRQ_STAT); 270 } 271 272 static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) 273 { 274 void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR; 275 void __iomem *addr; 276 277 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) 278 return -EINVAL; 279 280 addr = scr_addr + scr_map[sc_reg] * 4; 281 *val = readl(scr_addr + scr_map[sc_reg] * 4); 282 283 /* this controller has stuck DIAG.N, ignore it */ 284 if (sc_reg == SCR_ERROR) 285 *val &= ~SERR_PHYRDY_CHG; 286 return 0; 287 } 288 289 static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) 290 { 291 void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR; 292 293 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) 294 return -EINVAL; 295 296 writel(val, scr_addr + scr_map[sc_reg] * 4); 297 return 0; 298 } 299 300 static void inic_stop_idma(struct ata_port *ap) 301 { 302 void __iomem *port_base = inic_port_base(ap); 303 304 readb(port_base + PORT_RPQ_FIFO); 305 readb(port_base + PORT_RPQ_CNT); 306 writew(0, port_base + PORT_IDMA_CTL); 307 } 308 309 static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat) 310 { 311 struct ata_eh_info *ehi = &ap->link.eh_info; 312 struct inic_port_priv *pp = ap->private_data; 313 struct inic_cpb *cpb = &pp->pkt->cpb; 314 bool freeze = false; 315 316 ata_ehi_clear_desc(ehi); 317 ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x", 318 irq_stat, idma_stat); 319 320 inic_stop_idma(ap); 321 322 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { 323 ata_ehi_push_desc(ehi, "hotplug"); 324 ata_ehi_hotplugged(ehi); 325 freeze = true; 326 } 327 328 if (idma_stat & IDMA_STAT_PERR) { 329 ata_ehi_push_desc(ehi, "PCI error"); 330 freeze = true; 331 } 332 333 if (idma_stat & IDMA_STAT_CPBERR) { 334 ata_ehi_push_desc(ehi, "CPB error"); 335 336 if (cpb->resp_flags & CPB_RESP_IGNORED) { 337 __ata_ehi_push_desc(ehi, " ignored"); 338 ehi->err_mask |= AC_ERR_INVALID; 339 freeze = true; 340 } 341 342 if (cpb->resp_flags & CPB_RESP_ATA_ERR) 343 ehi->err_mask |= AC_ERR_DEV; 344 345 if (cpb->resp_flags & CPB_RESP_SPURIOUS) { 346 __ata_ehi_push_desc(ehi, " spurious-intr"); 347 ehi->err_mask |= AC_ERR_HSM; 348 freeze = true; 349 } 350 351 if (cpb->resp_flags & 352 (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) { 353 __ata_ehi_push_desc(ehi, " data-over/underflow"); 354 ehi->err_mask |= AC_ERR_HSM; 355 freeze = true; 356 } 357 } 358 359 if (freeze) 360 ata_port_freeze(ap); 361 else 362 ata_port_abort(ap); 363 } 364 365 static void inic_host_intr(struct ata_port *ap) 366 { 367 void __iomem *port_base = inic_port_base(ap); 368 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 369 u8 irq_stat; 370 u16 idma_stat; 371 372 /* read and clear IRQ status */ 373 irq_stat = readb(port_base + PORT_IRQ_STAT); 374 writeb(irq_stat, port_base + PORT_IRQ_STAT); 375 idma_stat = readw(port_base + PORT_IDMA_STAT); 376 377 if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR))) 378 inic_host_err_intr(ap, irq_stat, idma_stat); 379 380 if (unlikely(!qc)) 381 goto spurious; 382 383 if (likely(idma_stat & IDMA_STAT_DONE)) { 384 inic_stop_idma(ap); 385 386 /* Depending on circumstances, device error 387 * isn't reported by IDMA, check it explicitly. 388 */ 389 if (unlikely(readb(port_base + PORT_TF_COMMAND) & 390 (ATA_DF | ATA_ERR))) 391 qc->err_mask |= AC_ERR_DEV; 392 393 ata_qc_complete(qc); 394 return; 395 } 396 397 spurious: 398 ata_port_printk(ap, KERN_WARNING, "unhandled interrupt: " 399 "cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n", 400 qc ? qc->tf.command : 0xff, irq_stat, idma_stat); 401 } 402 403 static irqreturn_t inic_interrupt(int irq, void *dev_instance) 404 { 405 struct ata_host *host = dev_instance; 406 struct inic_host_priv *hpriv = host->private_data; 407 u16 host_irq_stat; 408 int i, handled = 0;; 409 410 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); 411 412 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) 413 goto out; 414 415 spin_lock(&host->lock); 416 417 for (i = 0; i < NR_PORTS; i++) { 418 struct ata_port *ap = host->ports[i]; 419 420 if (!(host_irq_stat & (HIRQ_PORT0 << i))) 421 continue; 422 423 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) { 424 inic_host_intr(ap); 425 handled++; 426 } else { 427 if (ata_ratelimit()) 428 dev_printk(KERN_ERR, host->dev, "interrupt " 429 "from disabled port %d (0x%x)\n", 430 i, host_irq_stat); 431 } 432 } 433 434 spin_unlock(&host->lock); 435 436 out: 437 return IRQ_RETVAL(handled); 438 } 439 440 static int inic_check_atapi_dma(struct ata_queued_cmd *qc) 441 { 442 /* For some reason ATAPI_PROT_DMA doesn't work for some 443 * commands including writes and other misc ops. Use PIO 444 * protocol instead, which BTW is driven by the DMA engine 445 * anyway, so it shouldn't make much difference for native 446 * SATA devices. 447 */ 448 if (atapi_cmd_type(qc->cdb[0]) == READ) 449 return 0; 450 return 1; 451 } 452 453 static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc) 454 { 455 struct scatterlist *sg; 456 unsigned int si; 457 u8 flags = 0; 458 459 if (qc->tf.flags & ATA_TFLAG_WRITE) 460 flags |= PRD_WRITE; 461 462 if (ata_is_dma(qc->tf.protocol)) 463 flags |= PRD_DMA; 464 465 for_each_sg(qc->sg, sg, qc->n_elem, si) { 466 prd->mad = cpu_to_le32(sg_dma_address(sg)); 467 prd->len = cpu_to_le16(sg_dma_len(sg)); 468 prd->flags = flags; 469 prd++; 470 } 471 472 WARN_ON(!si); 473 prd[-1].flags |= PRD_END; 474 } 475 476 static void inic_qc_prep(struct ata_queued_cmd *qc) 477 { 478 struct inic_port_priv *pp = qc->ap->private_data; 479 struct inic_pkt *pkt = pp->pkt; 480 struct inic_cpb *cpb = &pkt->cpb; 481 struct inic_prd *prd = pkt->prd; 482 bool is_atapi = ata_is_atapi(qc->tf.protocol); 483 bool is_data = ata_is_data(qc->tf.protocol); 484 unsigned int cdb_len = 0; 485 486 VPRINTK("ENTER\n"); 487 488 if (is_atapi) 489 cdb_len = qc->dev->cdb_len; 490 491 /* prepare packet, based on initio driver */ 492 memset(pkt, 0, sizeof(struct inic_pkt)); 493 494 cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN; 495 if (is_atapi || is_data) 496 cpb->ctl_flags |= CPB_CTL_DATA; 497 498 cpb->len = cpu_to_le32(qc->nbytes + cdb_len); 499 cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd)); 500 501 cpb->device = qc->tf.device; 502 cpb->feature = qc->tf.feature; 503 cpb->nsect = qc->tf.nsect; 504 cpb->lbal = qc->tf.lbal; 505 cpb->lbam = qc->tf.lbam; 506 cpb->lbah = qc->tf.lbah; 507 508 if (qc->tf.flags & ATA_TFLAG_LBA48) { 509 cpb->hob_feature = qc->tf.hob_feature; 510 cpb->hob_nsect = qc->tf.hob_nsect; 511 cpb->hob_lbal = qc->tf.hob_lbal; 512 cpb->hob_lbam = qc->tf.hob_lbam; 513 cpb->hob_lbah = qc->tf.hob_lbah; 514 } 515 516 cpb->command = qc->tf.command; 517 /* don't load ctl - dunno why. it's like that in the initio driver */ 518 519 /* setup PRD for CDB */ 520 if (is_atapi) { 521 memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN); 522 prd->mad = cpu_to_le32(pp->pkt_dma + 523 offsetof(struct inic_pkt, cdb)); 524 prd->len = cpu_to_le16(cdb_len); 525 prd->flags = PRD_CDB | PRD_WRITE; 526 if (!is_data) 527 prd->flags |= PRD_END; 528 prd++; 529 } 530 531 /* setup sg table */ 532 if (is_data) 533 inic_fill_sg(prd, qc); 534 535 pp->cpb_tbl[0] = pp->pkt_dma; 536 } 537 538 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) 539 { 540 struct ata_port *ap = qc->ap; 541 void __iomem *port_base = inic_port_base(ap); 542 543 /* fire up the ADMA engine */ 544 writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL); 545 writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL); 546 writeb(0, port_base + PORT_CPB_PTQFIFO); 547 548 return 0; 549 } 550 551 static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 552 { 553 void __iomem *port_base = inic_port_base(ap); 554 555 tf->feature = readb(port_base + PORT_TF_FEATURE); 556 tf->nsect = readb(port_base + PORT_TF_NSECT); 557 tf->lbal = readb(port_base + PORT_TF_LBAL); 558 tf->lbam = readb(port_base + PORT_TF_LBAM); 559 tf->lbah = readb(port_base + PORT_TF_LBAH); 560 tf->device = readb(port_base + PORT_TF_DEVICE); 561 tf->command = readb(port_base + PORT_TF_COMMAND); 562 } 563 564 static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc) 565 { 566 struct ata_taskfile *rtf = &qc->result_tf; 567 struct ata_taskfile tf; 568 569 /* FIXME: Except for status and error, result TF access 570 * doesn't work. I tried reading from BAR0/2, CPB and BAR5. 571 * None works regardless of which command interface is used. 572 * For now return true iff status indicates device error. 573 * This means that we're reporting bogus sector for RW 574 * failures. Eeekk.... 575 */ 576 inic_tf_read(qc->ap, &tf); 577 578 if (!(tf.command & ATA_ERR)) 579 return false; 580 581 rtf->command = tf.command; 582 rtf->feature = tf.feature; 583 return true; 584 } 585 586 static void inic_freeze(struct ata_port *ap) 587 { 588 void __iomem *port_base = inic_port_base(ap); 589 590 writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK); 591 writeb(0xff, port_base + PORT_IRQ_STAT); 592 } 593 594 static void inic_thaw(struct ata_port *ap) 595 { 596 void __iomem *port_base = inic_port_base(ap); 597 598 writeb(0xff, port_base + PORT_IRQ_STAT); 599 writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK); 600 } 601 602 static int inic_check_ready(struct ata_link *link) 603 { 604 void __iomem *port_base = inic_port_base(link->ap); 605 606 return ata_check_ready(readb(port_base + PORT_TF_COMMAND)); 607 } 608 609 /* 610 * SRST and SControl hardreset don't give valid signature on this 611 * controller. Only controller specific hardreset mechanism works. 612 */ 613 static int inic_hardreset(struct ata_link *link, unsigned int *class, 614 unsigned long deadline) 615 { 616 struct ata_port *ap = link->ap; 617 void __iomem *port_base = inic_port_base(ap); 618 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; 619 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 620 int rc; 621 622 /* hammer it into sane state */ 623 inic_reset_port(port_base); 624 625 writew(IDMA_CTL_RST_ATA, idma_ctl); 626 readw(idma_ctl); /* flush */ 627 msleep(1); 628 writew(0, idma_ctl); 629 630 rc = sata_link_resume(link, timing, deadline); 631 if (rc) { 632 ata_link_printk(link, KERN_WARNING, "failed to resume " 633 "link after reset (errno=%d)\n", rc); 634 return rc; 635 } 636 637 *class = ATA_DEV_NONE; 638 if (ata_link_online(link)) { 639 struct ata_taskfile tf; 640 641 /* wait for link to become ready */ 642 rc = ata_wait_after_reset(link, deadline, inic_check_ready); 643 /* link occupied, -ENODEV too is an error */ 644 if (rc) { 645 ata_link_printk(link, KERN_WARNING, "device not ready " 646 "after hardreset (errno=%d)\n", rc); 647 return rc; 648 } 649 650 inic_tf_read(ap, &tf); 651 *class = ata_dev_classify(&tf); 652 } 653 654 return 0; 655 } 656 657 static void inic_error_handler(struct ata_port *ap) 658 { 659 void __iomem *port_base = inic_port_base(ap); 660 661 inic_reset_port(port_base); 662 ata_std_error_handler(ap); 663 } 664 665 static void inic_post_internal_cmd(struct ata_queued_cmd *qc) 666 { 667 /* make DMA engine forget about the failed command */ 668 if (qc->flags & ATA_QCFLAG_FAILED) 669 inic_reset_port(inic_port_base(qc->ap)); 670 } 671 672 static void init_port(struct ata_port *ap) 673 { 674 void __iomem *port_base = inic_port_base(ap); 675 struct inic_port_priv *pp = ap->private_data; 676 677 /* clear packet and CPB table */ 678 memset(pp->pkt, 0, sizeof(struct inic_pkt)); 679 memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE); 680 681 /* setup PRD and CPB lookup table addresses */ 682 writel(ap->prd_dma, port_base + PORT_PRD_ADDR); 683 writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR); 684 } 685 686 static int inic_port_resume(struct ata_port *ap) 687 { 688 init_port(ap); 689 return 0; 690 } 691 692 static int inic_port_start(struct ata_port *ap) 693 { 694 struct device *dev = ap->host->dev; 695 struct inic_port_priv *pp; 696 int rc; 697 698 /* alloc and initialize private data */ 699 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 700 if (!pp) 701 return -ENOMEM; 702 ap->private_data = pp; 703 704 /* Alloc resources */ 705 rc = ata_port_start(ap); 706 if (rc) 707 return rc; 708 709 pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt), 710 &pp->pkt_dma, GFP_KERNEL); 711 if (!pp->pkt) 712 return -ENOMEM; 713 714 pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE, 715 &pp->cpb_tbl_dma, GFP_KERNEL); 716 if (!pp->cpb_tbl) 717 return -ENOMEM; 718 719 init_port(ap); 720 721 return 0; 722 } 723 724 static struct ata_port_operations inic_port_ops = { 725 .inherits = &sata_port_ops, 726 727 .check_atapi_dma = inic_check_atapi_dma, 728 .qc_prep = inic_qc_prep, 729 .qc_issue = inic_qc_issue, 730 .qc_fill_rtf = inic_qc_fill_rtf, 731 732 .freeze = inic_freeze, 733 .thaw = inic_thaw, 734 .hardreset = inic_hardreset, 735 .error_handler = inic_error_handler, 736 .post_internal_cmd = inic_post_internal_cmd, 737 738 .scr_read = inic_scr_read, 739 .scr_write = inic_scr_write, 740 741 .port_resume = inic_port_resume, 742 .port_start = inic_port_start, 743 }; 744 745 static struct ata_port_info inic_port_info = { 746 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 747 .pio_mask = ATA_PIO4, 748 .mwdma_mask = ATA_MWDMA2, 749 .udma_mask = ATA_UDMA6, 750 .port_ops = &inic_port_ops 751 }; 752 753 static int init_controller(void __iomem *mmio_base, u16 hctl) 754 { 755 int i; 756 u16 val; 757 758 hctl &= ~HCTL_KNOWN_BITS; 759 760 /* Soft reset whole controller. Spec says reset duration is 3 761 * PCI clocks, be generous and give it 10ms. 762 */ 763 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); 764 readw(mmio_base + HOST_CTL); /* flush */ 765 766 for (i = 0; i < 10; i++) { 767 msleep(1); 768 val = readw(mmio_base + HOST_CTL); 769 if (!(val & HCTL_SOFTRST)) 770 break; 771 } 772 773 if (val & HCTL_SOFTRST) 774 return -EIO; 775 776 /* mask all interrupts and reset ports */ 777 for (i = 0; i < NR_PORTS; i++) { 778 void __iomem *port_base = mmio_base + i * PORT_SIZE; 779 780 writeb(0xff, port_base + PORT_IRQ_MASK); 781 inic_reset_port(port_base); 782 } 783 784 /* port IRQ is masked now, unmask global IRQ */ 785 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); 786 val = readw(mmio_base + HOST_IRQ_MASK); 787 val &= ~(HIRQ_PORT0 | HIRQ_PORT1); 788 writew(val, mmio_base + HOST_IRQ_MASK); 789 790 return 0; 791 } 792 793 #ifdef CONFIG_PM 794 static int inic_pci_device_resume(struct pci_dev *pdev) 795 { 796 struct ata_host *host = dev_get_drvdata(&pdev->dev); 797 struct inic_host_priv *hpriv = host->private_data; 798 int rc; 799 800 rc = ata_pci_device_do_resume(pdev); 801 if (rc) 802 return rc; 803 804 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 805 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); 806 if (rc) 807 return rc; 808 } 809 810 ata_host_resume(host); 811 812 return 0; 813 } 814 #endif 815 816 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 817 { 818 static int printed_version; 819 const struct ata_port_info *ppi[] = { &inic_port_info, NULL }; 820 struct ata_host *host; 821 struct inic_host_priv *hpriv; 822 void __iomem * const *iomap; 823 int mmio_bar; 824 int i, rc; 825 826 if (!printed_version++) 827 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 828 829 /* alloc host */ 830 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS); 831 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 832 if (!host || !hpriv) 833 return -ENOMEM; 834 835 host->private_data = hpriv; 836 837 /* Acquire resources and fill host. Note that PCI and cardbus 838 * use different BARs. 839 */ 840 rc = pcim_enable_device(pdev); 841 if (rc) 842 return rc; 843 844 if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM) 845 mmio_bar = MMIO_BAR_PCI; 846 else 847 mmio_bar = MMIO_BAR_CARDBUS; 848 849 rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME); 850 if (rc) 851 return rc; 852 host->iomap = iomap = pcim_iomap_table(pdev); 853 hpriv->mmio_base = iomap[mmio_bar]; 854 hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL); 855 856 for (i = 0; i < NR_PORTS; i++) { 857 struct ata_port *ap = host->ports[i]; 858 859 ata_port_pbar_desc(ap, mmio_bar, -1, "mmio"); 860 ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port"); 861 } 862 863 /* Set dma_mask. This devices doesn't support 64bit addressing. */ 864 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 865 if (rc) { 866 dev_printk(KERN_ERR, &pdev->dev, 867 "32-bit DMA enable failed\n"); 868 return rc; 869 } 870 871 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 872 if (rc) { 873 dev_printk(KERN_ERR, &pdev->dev, 874 "32-bit consistent DMA enable failed\n"); 875 return rc; 876 } 877 878 /* 879 * This controller is braindamaged. dma_boundary is 0xffff 880 * like others but it will lock up the whole machine HARD if 881 * 65536 byte PRD entry is fed. Reduce maximum segment size. 882 */ 883 rc = pci_set_dma_max_seg_size(pdev, 65536 - 512); 884 if (rc) { 885 dev_printk(KERN_ERR, &pdev->dev, 886 "failed to set the maximum segment size.\n"); 887 return rc; 888 } 889 890 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); 891 if (rc) { 892 dev_printk(KERN_ERR, &pdev->dev, 893 "failed to initialize controller\n"); 894 return rc; 895 } 896 897 pci_set_master(pdev); 898 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED, 899 &inic_sht); 900 } 901 902 static const struct pci_device_id inic_pci_tbl[] = { 903 { PCI_VDEVICE(INIT, 0x1622), }, 904 { }, 905 }; 906 907 static struct pci_driver inic_pci_driver = { 908 .name = DRV_NAME, 909 .id_table = inic_pci_tbl, 910 #ifdef CONFIG_PM 911 .suspend = ata_pci_device_suspend, 912 .resume = inic_pci_device_resume, 913 #endif 914 .probe = inic_init_one, 915 .remove = ata_pci_remove_one, 916 }; 917 918 static int __init inic_init(void) 919 { 920 return pci_register_driver(&inic_pci_driver); 921 } 922 923 static void __exit inic_exit(void) 924 { 925 pci_unregister_driver(&inic_pci_driver); 926 } 927 928 MODULE_AUTHOR("Tejun Heo"); 929 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA"); 930 MODULE_LICENSE("GPL v2"); 931 MODULE_DEVICE_TABLE(pci, inic_pci_tbl); 932 MODULE_VERSION(DRV_VERSION); 933 934 module_init(inic_init); 935 module_exit(inic_exit); 936