1 /* 2 * Calxeda Highbank AHCI SATA platform driver 3 * Copyright 2012 Calxeda, Inc. 4 * 5 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include <linux/kernel.h> 20 #include <linux/gfp.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/types.h> 24 #include <linux/err.h> 25 #include <linux/io.h> 26 #include <linux/spinlock.h> 27 #include <linux/device.h> 28 #include <linux/of_device.h> 29 #include <linux/of_address.h> 30 #include <linux/platform_device.h> 31 #include <linux/libata.h> 32 #include <linux/ahci_platform.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/export.h> 36 #include <linux/gpio.h> 37 #include <linux/of_gpio.h> 38 39 #include "ahci.h" 40 41 #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f)) 42 #define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2) 43 #define SERDES_CR_CTL 0x80a0 44 #define SERDES_CR_ADDR 0x80a1 45 #define SERDES_CR_DATA 0x80a2 46 #define CR_BUSY 0x0001 47 #define CR_START 0x0001 48 #define CR_WR_RDN 0x0002 49 #define CPHY_RX_INPUT_STS 0x2002 50 #define CPHY_SATA_OVERRIDE 0x4000 51 #define CPHY_OVERRIDE 0x2005 52 #define SPHY_LANE 0x100 53 #define SPHY_HALF_RATE 0x0001 54 #define CPHY_SATA_DPLL_MODE 0x0700 55 #define CPHY_SATA_DPLL_SHIFT 8 56 #define CPHY_SATA_DPLL_RESET (1 << 11) 57 #define CPHY_PHY_COUNT 6 58 #define CPHY_LANE_COUNT 4 59 #define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT) 60 61 static DEFINE_SPINLOCK(cphy_lock); 62 /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based 63 * sata ports to their phys and then to their lanes within the phys 64 */ 65 struct phy_lane_info { 66 void __iomem *phy_base; 67 u8 lane_mapping; 68 u8 phy_devs; 69 }; 70 static struct phy_lane_info port_data[CPHY_PORT_COUNT]; 71 72 static DEFINE_SPINLOCK(sgpio_lock); 73 #define SCLOCK 0 74 #define SLOAD 1 75 #define SDATA 2 76 #define SGPIO_PINS 3 77 #define SGPIO_PORTS 8 78 79 /* can be cast as an ahci_host_priv for compatibility with most functions */ 80 struct ecx_plat_data { 81 u32 n_ports; 82 unsigned sgpio_gpio[SGPIO_PINS]; 83 u32 sgpio_pattern; 84 u32 port_to_sgpio[SGPIO_PORTS]; 85 }; 86 87 #define SGPIO_SIGNALS 3 88 #define ECX_ACTIVITY_BITS 0x300000 89 #define ECX_ACTIVITY_SHIFT 0 90 #define ECX_LOCATE_BITS 0x80000 91 #define ECX_LOCATE_SHIFT 1 92 #define ECX_FAULT_BITS 0x400000 93 #define ECX_FAULT_SHIFT 2 94 static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, 95 u32 shift) 96 { 97 return 1 << (3 * pdata->port_to_sgpio[port] + shift); 98 } 99 100 static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state) 101 { 102 if (state & ECX_ACTIVITY_BITS) 103 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, 104 ECX_ACTIVITY_SHIFT); 105 else 106 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, 107 ECX_ACTIVITY_SHIFT); 108 if (state & ECX_LOCATE_BITS) 109 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, 110 ECX_LOCATE_SHIFT); 111 else 112 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, 113 ECX_LOCATE_SHIFT); 114 if (state & ECX_FAULT_BITS) 115 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, 116 ECX_FAULT_SHIFT); 117 else 118 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, 119 ECX_FAULT_SHIFT); 120 } 121 122 /* 123 * Tell the LED controller that the signal has changed by raising the clock 124 * line for 50 uS and then lowering it for 50 uS. 125 */ 126 static void ecx_led_cycle_clock(struct ecx_plat_data *pdata) 127 { 128 gpio_set_value(pdata->sgpio_gpio[SCLOCK], 1); 129 udelay(50); 130 gpio_set_value(pdata->sgpio_gpio[SCLOCK], 0); 131 udelay(50); 132 } 133 134 static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state, 135 ssize_t size) 136 { 137 struct ahci_host_priv *hpriv = ap->host->private_data; 138 struct ecx_plat_data *pdata = (struct ecx_plat_data *) hpriv->plat_data; 139 struct ahci_port_priv *pp = ap->private_data; 140 unsigned long flags; 141 int pmp, i; 142 struct ahci_em_priv *emp; 143 u32 sgpio_out; 144 145 /* get the slot number from the message */ 146 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 147 if (pmp < EM_MAX_SLOTS) 148 emp = &pp->em_priv[pmp]; 149 else 150 return -EINVAL; 151 152 if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED)) 153 return size; 154 155 spin_lock_irqsave(&sgpio_lock, flags); 156 ecx_parse_sgpio(pdata, ap->port_no, state); 157 sgpio_out = pdata->sgpio_pattern; 158 gpio_set_value(pdata->sgpio_gpio[SLOAD], 1); 159 ecx_led_cycle_clock(pdata); 160 gpio_set_value(pdata->sgpio_gpio[SLOAD], 0); 161 /* 162 * bit-bang out the SGPIO pattern, by consuming a bit and then 163 * clocking it out. 164 */ 165 for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) { 166 gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1); 167 sgpio_out >>= 1; 168 ecx_led_cycle_clock(pdata); 169 } 170 171 /* save off new led state for port/slot */ 172 emp->led_state = state; 173 174 spin_unlock_irqrestore(&sgpio_lock, flags); 175 return size; 176 } 177 178 static void highbank_set_em_messages(struct device *dev, 179 struct ahci_host_priv *hpriv, 180 struct ata_port_info *pi) 181 { 182 struct device_node *np = dev->of_node; 183 struct ecx_plat_data *pdata = hpriv->plat_data; 184 int i; 185 int err; 186 187 for (i = 0; i < SGPIO_PINS; i++) { 188 err = of_get_named_gpio(np, "calxeda,sgpio-gpio", i); 189 if (IS_ERR_VALUE(err)) 190 return; 191 192 pdata->sgpio_gpio[i] = err; 193 err = gpio_request(pdata->sgpio_gpio[i], "CX SGPIO"); 194 if (err) { 195 pr_err("sata_highbank gpio_request %d failed: %d\n", 196 i, err); 197 return; 198 } 199 gpio_direction_output(pdata->sgpio_gpio[i], 1); 200 } 201 of_property_read_u32_array(np, "calxeda,led-order", 202 pdata->port_to_sgpio, 203 pdata->n_ports); 204 205 /* store em_loc */ 206 hpriv->em_loc = 0; 207 hpriv->em_buf_sz = 4; 208 hpriv->em_msg_type = EM_MSG_TYPE_LED; 209 pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY; 210 } 211 212 static u32 __combo_phy_reg_read(u8 sata_port, u32 addr) 213 { 214 u32 data; 215 u8 dev = port_data[sata_port].phy_devs; 216 spin_lock(&cphy_lock); 217 writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); 218 data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr)); 219 spin_unlock(&cphy_lock); 220 return data; 221 } 222 223 static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data) 224 { 225 u8 dev = port_data[sata_port].phy_devs; 226 spin_lock(&cphy_lock); 227 writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); 228 writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr)); 229 spin_unlock(&cphy_lock); 230 } 231 232 static void combo_phy_wait_for_ready(u8 sata_port) 233 { 234 while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY) 235 udelay(5); 236 } 237 238 static u32 combo_phy_read(u8 sata_port, u32 addr) 239 { 240 combo_phy_wait_for_ready(sata_port); 241 __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr); 242 __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START); 243 combo_phy_wait_for_ready(sata_port); 244 return __combo_phy_reg_read(sata_port, SERDES_CR_DATA); 245 } 246 247 static void combo_phy_write(u8 sata_port, u32 addr, u32 data) 248 { 249 combo_phy_wait_for_ready(sata_port); 250 __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr); 251 __combo_phy_reg_write(sata_port, SERDES_CR_DATA, data); 252 __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START); 253 } 254 255 static void highbank_cphy_disable_overrides(u8 sata_port) 256 { 257 u8 lane = port_data[sata_port].lane_mapping; 258 u32 tmp; 259 if (unlikely(port_data[sata_port].phy_base == NULL)) 260 return; 261 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); 262 tmp &= ~CPHY_SATA_OVERRIDE; 263 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); 264 } 265 266 static void cphy_override_rx_mode(u8 sata_port, u32 val) 267 { 268 u8 lane = port_data[sata_port].lane_mapping; 269 u32 tmp; 270 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); 271 tmp &= ~CPHY_SATA_OVERRIDE; 272 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); 273 274 tmp |= CPHY_SATA_OVERRIDE; 275 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); 276 277 tmp &= ~CPHY_SATA_DPLL_MODE; 278 tmp |= val << CPHY_SATA_DPLL_SHIFT; 279 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); 280 281 tmp |= CPHY_SATA_DPLL_RESET; 282 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); 283 284 tmp &= ~CPHY_SATA_DPLL_RESET; 285 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); 286 287 msleep(15); 288 } 289 290 static void highbank_cphy_override_lane(u8 sata_port) 291 { 292 u8 lane = port_data[sata_port].lane_mapping; 293 u32 tmp, k = 0; 294 295 if (unlikely(port_data[sata_port].phy_base == NULL)) 296 return; 297 do { 298 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + 299 lane * SPHY_LANE); 300 } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000)); 301 cphy_override_rx_mode(sata_port, 3); 302 } 303 304 static int highbank_initialize_phys(struct device *dev, void __iomem *addr) 305 { 306 struct device_node *sata_node = dev->of_node; 307 int phy_count = 0, phy, port = 0; 308 void __iomem *cphy_base[CPHY_PHY_COUNT]; 309 struct device_node *phy_nodes[CPHY_PHY_COUNT]; 310 memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT); 311 memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT); 312 313 do { 314 u32 tmp; 315 struct of_phandle_args phy_data; 316 if (of_parse_phandle_with_args(sata_node, 317 "calxeda,port-phys", "#phy-cells", 318 port, &phy_data)) 319 break; 320 for (phy = 0; phy < phy_count; phy++) { 321 if (phy_nodes[phy] == phy_data.np) 322 break; 323 } 324 if (phy_nodes[phy] == NULL) { 325 phy_nodes[phy] = phy_data.np; 326 cphy_base[phy] = of_iomap(phy_nodes[phy], 0); 327 if (cphy_base[phy] == NULL) { 328 return 0; 329 } 330 phy_count += 1; 331 } 332 port_data[port].lane_mapping = phy_data.args[0]; 333 of_property_read_u32(phy_nodes[phy], "phydev", &tmp); 334 port_data[port].phy_devs = tmp; 335 port_data[port].phy_base = cphy_base[phy]; 336 of_node_put(phy_data.np); 337 port += 1; 338 } while (port < CPHY_PORT_COUNT); 339 return 0; 340 } 341 342 /* 343 * The Calxeda SATA phy intermittently fails to bring up a link with Gen3 344 * Retrying the phy hard reset can work around the issue, but the drive 345 * may fail again. In less than 150 out of 15000 test runs, it took more 346 * than 10 tries for the link to be established (but never more than 35). 347 * Triple the maximum observed retry count to provide plenty of margin for 348 * rare events and to guarantee that the link is established. 349 * 350 * Also, the default 2 second time-out on a failed drive is too long in 351 * this situation. The uboot implementation of the same driver function 352 * uses a much shorter time-out period and never experiences a time out 353 * issue. Reducing the time-out to 500ms improves the responsiveness. 354 * The other timing constants were kept the same as the stock AHCI driver. 355 * This change was also tested 15000 times on 24 drives and none of them 356 * experienced a time out. 357 */ 358 static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class, 359 unsigned long deadline) 360 { 361 static const unsigned long timing[] = { 5, 100, 500}; 362 struct ata_port *ap = link->ap; 363 struct ahci_port_priv *pp = ap->private_data; 364 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 365 struct ata_taskfile tf; 366 bool online; 367 u32 sstatus; 368 int rc; 369 int retry = 100; 370 371 ahci_stop_engine(ap); 372 373 /* clear D2H reception area to properly wait for D2H FIS */ 374 ata_tf_init(link->device, &tf); 375 tf.command = ATA_BUSY; 376 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 377 378 do { 379 highbank_cphy_disable_overrides(link->ap->port_no); 380 rc = sata_link_hardreset(link, timing, deadline, &online, NULL); 381 highbank_cphy_override_lane(link->ap->port_no); 382 383 /* If the status is 1, we are connected, but the link did not 384 * come up. So retry resetting the link again. 385 */ 386 if (sata_scr_read(link, SCR_STATUS, &sstatus)) 387 break; 388 if (!(sstatus & 0x3)) 389 break; 390 } while (!online && retry--); 391 392 ahci_start_engine(ap); 393 394 if (online) 395 *class = ahci_dev_classify(ap); 396 397 return rc; 398 } 399 400 static struct ata_port_operations ahci_highbank_ops = { 401 .inherits = &ahci_ops, 402 .hardreset = ahci_highbank_hardreset, 403 .transmit_led_message = ecx_transmit_led_message, 404 }; 405 406 static const struct ata_port_info ahci_highbank_port_info = { 407 .flags = AHCI_FLAG_COMMON, 408 .pio_mask = ATA_PIO4, 409 .udma_mask = ATA_UDMA6, 410 .port_ops = &ahci_highbank_ops, 411 }; 412 413 static struct scsi_host_template ahci_highbank_platform_sht = { 414 AHCI_SHT("sata_highbank"), 415 }; 416 417 static const struct of_device_id ahci_of_match[] = { 418 { .compatible = "calxeda,hb-ahci" }, 419 {}, 420 }; 421 MODULE_DEVICE_TABLE(of, ahci_of_match); 422 423 static int ahci_highbank_probe(struct platform_device *pdev) 424 { 425 struct device *dev = &pdev->dev; 426 struct ahci_host_priv *hpriv; 427 struct ecx_plat_data *pdata; 428 struct ata_host *host; 429 struct resource *mem; 430 int irq; 431 int i; 432 int rc; 433 u32 n_ports; 434 struct ata_port_info pi = ahci_highbank_port_info; 435 const struct ata_port_info *ppi[] = { &pi, NULL }; 436 437 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 438 if (!mem) { 439 dev_err(dev, "no mmio space\n"); 440 return -EINVAL; 441 } 442 443 irq = platform_get_irq(pdev, 0); 444 if (irq <= 0) { 445 dev_err(dev, "no irq\n"); 446 return -EINVAL; 447 } 448 449 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 450 if (!hpriv) { 451 dev_err(dev, "can't alloc ahci_host_priv\n"); 452 return -ENOMEM; 453 } 454 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 455 if (!pdata) { 456 dev_err(dev, "can't alloc ecx_plat_data\n"); 457 return -ENOMEM; 458 } 459 460 hpriv->flags |= (unsigned long)pi.private_data; 461 462 hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); 463 if (!hpriv->mmio) { 464 dev_err(dev, "can't map %pR\n", mem); 465 return -ENOMEM; 466 } 467 468 rc = highbank_initialize_phys(dev, hpriv->mmio); 469 if (rc) 470 return rc; 471 472 473 ahci_save_initial_config(dev, hpriv, 0, 0); 474 475 /* prepare host */ 476 if (hpriv->cap & HOST_CAP_NCQ) 477 pi.flags |= ATA_FLAG_NCQ; 478 479 if (hpriv->cap & HOST_CAP_PMP) 480 pi.flags |= ATA_FLAG_PMP; 481 482 /* CAP.NP sometimes indicate the index of the last enabled 483 * port, at other times, that of the last possible port, so 484 * determining the maximum port number requires looking at 485 * both CAP.NP and port_map. 486 */ 487 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 488 489 pdata->n_ports = n_ports; 490 hpriv->plat_data = pdata; 491 highbank_set_em_messages(dev, hpriv, &pi); 492 493 host = ata_host_alloc_pinfo(dev, ppi, n_ports); 494 if (!host) { 495 rc = -ENOMEM; 496 goto err0; 497 } 498 499 host->private_data = hpriv; 500 501 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 502 host->flags |= ATA_HOST_PARALLEL_SCAN; 503 504 for (i = 0; i < host->n_ports; i++) { 505 struct ata_port *ap = host->ports[i]; 506 507 ata_port_desc(ap, "mmio %pR", mem); 508 ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80); 509 510 /* set enclosure management message type */ 511 if (ap->flags & ATA_FLAG_EM) 512 ap->em_message_type = hpriv->em_msg_type; 513 514 /* disabled/not-implemented port */ 515 if (!(hpriv->port_map & (1 << i))) 516 ap->ops = &ata_dummy_port_ops; 517 } 518 519 rc = ahci_reset_controller(host); 520 if (rc) 521 goto err0; 522 523 ahci_init_controller(host); 524 ahci_print_info(host, "platform"); 525 526 rc = ata_host_activate(host, irq, ahci_interrupt, 0, 527 &ahci_highbank_platform_sht); 528 if (rc) 529 goto err0; 530 531 return 0; 532 err0: 533 return rc; 534 } 535 536 #ifdef CONFIG_PM_SLEEP 537 static int ahci_highbank_suspend(struct device *dev) 538 { 539 struct ata_host *host = dev_get_drvdata(dev); 540 struct ahci_host_priv *hpriv = host->private_data; 541 void __iomem *mmio = hpriv->mmio; 542 u32 ctl; 543 int rc; 544 545 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 546 dev_err(dev, "firmware update required for suspend/resume\n"); 547 return -EIO; 548 } 549 550 /* 551 * AHCI spec rev1.1 section 8.3.3: 552 * Software must disable interrupts prior to requesting a 553 * transition of the HBA to D3 state. 554 */ 555 ctl = readl(mmio + HOST_CTL); 556 ctl &= ~HOST_IRQ_EN; 557 writel(ctl, mmio + HOST_CTL); 558 readl(mmio + HOST_CTL); /* flush */ 559 560 rc = ata_host_suspend(host, PMSG_SUSPEND); 561 if (rc) 562 return rc; 563 564 return 0; 565 } 566 567 static int ahci_highbank_resume(struct device *dev) 568 { 569 struct ata_host *host = dev_get_drvdata(dev); 570 int rc; 571 572 if (dev->power.power_state.event == PM_EVENT_SUSPEND) { 573 rc = ahci_reset_controller(host); 574 if (rc) 575 return rc; 576 577 ahci_init_controller(host); 578 } 579 580 ata_host_resume(host); 581 582 return 0; 583 } 584 #endif 585 586 static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops, 587 ahci_highbank_suspend, ahci_highbank_resume); 588 589 static struct platform_driver ahci_highbank_driver = { 590 .remove = ata_platform_remove_one, 591 .driver = { 592 .name = "highbank-ahci", 593 .owner = THIS_MODULE, 594 .of_match_table = ahci_of_match, 595 .pm = &ahci_highbank_pm_ops, 596 }, 597 .probe = ahci_highbank_probe, 598 }; 599 600 module_platform_driver(ahci_highbank_driver); 601 602 MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver"); 603 MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>"); 604 MODULE_LICENSE("GPL"); 605 MODULE_ALIAS("sata:highbank"); 606