1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 22 #include <scsi/scsi_host.h> 23 #include <scsi/scsi_cmnd.h> 24 #include <linux/libata.h> 25 #include <asm/io.h> 26 #include <linux/of_platform.h> 27 28 /* Controller information */ 29 enum { 30 SATA_FSL_QUEUE_DEPTH = 16, 31 SATA_FSL_MAX_PRD = 63, 32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 34 35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 37 ATA_FLAG_NCQ), 38 SATA_FSL_HOST_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY, 39 40 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 41 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 42 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 43 44 /* 45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 46 * chained indirect PRDEs upto a max count of 63. 47 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will 48 * be setup as an indirect descriptor, pointing to it's next 49 * (contigious) PRDE. Though chained indirect PRDE arrays are 50 * supported,it will be more efficient to use a direct PRDT and 51 * a single chain/link to indirect PRDE array/PRDT. 52 */ 53 54 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 55 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 56 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 57 SATA_FSL_CMD_DESC_RSRVD = 16, 58 59 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 60 SATA_FSL_CMD_DESC_SFIS_SZ + 61 SATA_FSL_CMD_DESC_ACMD_SZ + 62 SATA_FSL_CMD_DESC_RSRVD + 63 SATA_FSL_MAX_PRD * 16), 64 65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 66 (SATA_FSL_CMD_DESC_CFIS_SZ + 67 SATA_FSL_CMD_DESC_SFIS_SZ + 68 SATA_FSL_CMD_DESC_ACMD_SZ + 69 SATA_FSL_CMD_DESC_RSRVD), 70 71 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 72 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 73 SATA_FSL_CMD_DESC_AR_SZ), 74 75 /* 76 * MPC8315 has two SATA controllers, SATA1 & SATA2 77 * (one port per controller) 78 * MPC837x has 2/4 controllers, one port per controller 79 */ 80 81 SATA_FSL_MAX_PORTS = 1, 82 83 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 84 }; 85 86 /* 87 * Host Controller command register set - per port 88 */ 89 enum { 90 CQ = 0, 91 CA = 8, 92 CC = 0x10, 93 CE = 0x18, 94 DE = 0x20, 95 CHBA = 0x24, 96 HSTATUS = 0x28, 97 HCONTROL = 0x2C, 98 CQPMP = 0x30, 99 SIGNATURE = 0x34, 100 ICC = 0x38, 101 102 /* 103 * Host Status Register (HStatus) bitdefs 104 */ 105 ONLINE = (1 << 31), 106 GOING_OFFLINE = (1 << 30), 107 BIST_ERR = (1 << 29), 108 109 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 110 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 111 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 112 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 113 FATAL_ERR_DATA_OVERRUN = (1 << 12), 114 FATAL_ERR_CRC_ERR_TX = (1 << 11), 115 FATAL_ERR_CRC_ERR_RX = (1 << 10), 116 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 117 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 118 119 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 120 FATAL_ERR_PARITY_ERR_TX | 121 FATAL_ERR_PARITY_ERR_RX | 122 FATAL_ERR_DATA_UNDERRUN | 123 FATAL_ERR_DATA_OVERRUN | 124 FATAL_ERR_CRC_ERR_TX | 125 FATAL_ERR_CRC_ERR_RX | 126 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 127 128 INT_ON_FATAL_ERR = (1 << 5), 129 INT_ON_PHYRDY_CHG = (1 << 4), 130 131 INT_ON_SIGNATURE_UPDATE = (1 << 3), 132 INT_ON_SNOTIFY_UPDATE = (1 << 2), 133 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 134 INT_ON_CMD_COMPLETE = 1, 135 136 INT_ON_ERROR = INT_ON_FATAL_ERR | 137 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 138 139 /* 140 * Host Control Register (HControl) bitdefs 141 */ 142 HCONTROL_ONLINE_PHY_RST = (1 << 31), 143 HCONTROL_FORCE_OFFLINE = (1 << 30), 144 HCONTROL_PARITY_PROT_MOD = (1 << 14), 145 HCONTROL_DPATH_PARITY = (1 << 12), 146 HCONTROL_SNOOP_ENABLE = (1 << 10), 147 HCONTROL_PMP_ATTACHED = (1 << 9), 148 HCONTROL_COPYOUT_STATFIS = (1 << 8), 149 IE_ON_FATAL_ERR = (1 << 5), 150 IE_ON_PHYRDY_CHG = (1 << 4), 151 IE_ON_SIGNATURE_UPDATE = (1 << 3), 152 IE_ON_SNOTIFY_UPDATE = (1 << 2), 153 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 154 IE_ON_CMD_COMPLETE = 1, 155 156 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 157 IE_ON_SIGNATURE_UPDATE | 158 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 159 160 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 161 DATA_SNOOP_ENABLE = (1 << 22), 162 }; 163 164 /* 165 * SATA Superset Registers 166 */ 167 enum { 168 SSTATUS = 0, 169 SERROR = 4, 170 SCONTROL = 8, 171 SNOTIFY = 0xC, 172 }; 173 174 /* 175 * Control Status Register Set 176 */ 177 enum { 178 TRANSCFG = 0, 179 TRANSSTATUS = 4, 180 LINKCFG = 8, 181 LINKCFG1 = 0xC, 182 LINKCFG2 = 0x10, 183 LINKSTATUS = 0x14, 184 LINKSTATUS1 = 0x18, 185 PHYCTRLCFG = 0x1C, 186 COMMANDSTAT = 0x20, 187 }; 188 189 /* PHY (link-layer) configuration control */ 190 enum { 191 PHY_BIST_ENABLE = 0x01, 192 }; 193 194 /* 195 * Command Header Table entry, i.e, command slot 196 * 4 Dwords per command slot, command header size == 64 Dwords. 197 */ 198 struct cmdhdr_tbl_entry { 199 u32 cda; 200 u32 prde_fis_len; 201 u32 ttl; 202 u32 desc_info; 203 }; 204 205 /* 206 * Description information bitdefs 207 */ 208 enum { 209 VENDOR_SPECIFIC_BIST = (1 << 10), 210 CMD_DESC_SNOOP_ENABLE = (1 << 9), 211 FPDMA_QUEUED_CMD = (1 << 8), 212 SRST_CMD = (1 << 7), 213 BIST = (1 << 6), 214 ATAPI_CMD = (1 << 5), 215 }; 216 217 /* 218 * Command Descriptor 219 */ 220 struct command_desc { 221 u8 cfis[8 * 4]; 222 u8 sfis[8 * 4]; 223 u8 acmd[4 * 4]; 224 u8 fill[4 * 4]; 225 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 226 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 227 }; 228 229 /* 230 * Physical region table descriptor(PRD) 231 */ 232 233 struct prde { 234 u32 dba; 235 u8 fill[2 * 4]; 236 u32 ddc_and_ext; 237 }; 238 239 /* 240 * ata_port private data 241 * This is our per-port instance data. 242 */ 243 struct sata_fsl_port_priv { 244 struct cmdhdr_tbl_entry *cmdslot; 245 dma_addr_t cmdslot_paddr; 246 struct command_desc *cmdentry; 247 dma_addr_t cmdentry_paddr; 248 249 /* 250 * SATA FSL controller has a Status FIS which should contain the 251 * received D2H FIS & taskfile registers. This SFIS is present in 252 * the command descriptor, and to have a ready reference to it, 253 * we are caching it here, quite similar to what is done in H/W on 254 * AHCI compliant devices by copying taskfile fields to a 32-bit 255 * register. 256 */ 257 258 struct ata_taskfile tf; 259 }; 260 261 /* 262 * ata_port->host_set private data 263 */ 264 struct sata_fsl_host_priv { 265 void __iomem *hcr_base; 266 void __iomem *ssr_base; 267 void __iomem *csr_base; 268 int irq; 269 }; 270 271 static inline unsigned int sata_fsl_tag(unsigned int tag, 272 void __iomem *hcr_base) 273 { 274 /* We let libATA core do actual (queue) tag allocation */ 275 276 /* all non NCQ/queued commands should have tag#0 */ 277 if (ata_tag_internal(tag)) { 278 DPRINTK("mapping internal cmds to tag#0\n"); 279 return 0; 280 } 281 282 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 283 DPRINTK("tag %d invalid : out of range\n", tag); 284 return 0; 285 } 286 287 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 288 DPRINTK("tag %d invalid : in use!!\n", tag); 289 return 0; 290 } 291 292 return tag; 293 } 294 295 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 296 unsigned int tag, u32 desc_info, 297 u32 data_xfer_len, u8 num_prde, 298 u8 fis_len) 299 { 300 dma_addr_t cmd_descriptor_address; 301 302 cmd_descriptor_address = pp->cmdentry_paddr + 303 tag * SATA_FSL_CMD_DESC_SIZE; 304 305 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 306 307 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 308 pp->cmdslot[tag].prde_fis_len = 309 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 310 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 311 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 312 313 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 314 pp->cmdslot[tag].cda, 315 pp->cmdslot[tag].prde_fis_len, 316 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 317 318 } 319 320 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 321 u32 *ttl, dma_addr_t cmd_desc_paddr) 322 { 323 struct scatterlist *sg; 324 unsigned int num_prde = 0; 325 u32 ttl_dwords = 0; 326 327 /* 328 * NOTE : direct & indirect prdt's are contigiously allocated 329 */ 330 struct prde *prd = (struct prde *)&((struct command_desc *) 331 cmd_desc)->prdt; 332 333 struct prde *prd_ptr_to_indirect_ext = NULL; 334 unsigned indirect_ext_segment_sz = 0; 335 dma_addr_t indirect_ext_segment_paddr; 336 unsigned int si; 337 338 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 339 340 indirect_ext_segment_paddr = cmd_desc_paddr + 341 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 342 343 for_each_sg(qc->sg, sg, qc->n_elem, si) { 344 dma_addr_t sg_addr = sg_dma_address(sg); 345 u32 sg_len = sg_dma_len(sg); 346 347 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n", 348 sg_addr, sg_len); 349 350 /* warn if each s/g element is not dword aligned */ 351 if (sg_addr & 0x03) 352 ata_port_printk(qc->ap, KERN_ERR, 353 "s/g addr unaligned : 0x%x\n", sg_addr); 354 if (sg_len & 0x03) 355 ata_port_printk(qc->ap, KERN_ERR, 356 "s/g len unaligned : 0x%x\n", sg_len); 357 358 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 359 sg_next(sg) != NULL) { 360 VPRINTK("setting indirect prde\n"); 361 prd_ptr_to_indirect_ext = prd; 362 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 363 indirect_ext_segment_sz = 0; 364 ++prd; 365 ++num_prde; 366 } 367 368 ttl_dwords += sg_len; 369 prd->dba = cpu_to_le32(sg_addr); 370 prd->ddc_and_ext = 371 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); 372 373 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 374 ttl_dwords, prd->dba, prd->ddc_and_ext); 375 376 ++num_prde; 377 ++prd; 378 if (prd_ptr_to_indirect_ext) 379 indirect_ext_segment_sz += sg_len; 380 } 381 382 if (prd_ptr_to_indirect_ext) { 383 /* set indirect extension flag along with indirect ext. size */ 384 prd_ptr_to_indirect_ext->ddc_and_ext = 385 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 386 DATA_SNOOP_ENABLE | 387 (indirect_ext_segment_sz & ~0x03))); 388 } 389 390 *ttl = ttl_dwords; 391 return num_prde; 392 } 393 394 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 395 { 396 struct ata_port *ap = qc->ap; 397 struct sata_fsl_port_priv *pp = ap->private_data; 398 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 399 void __iomem *hcr_base = host_priv->hcr_base; 400 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 401 struct command_desc *cd; 402 u32 desc_info = CMD_DESC_SNOOP_ENABLE; 403 u32 num_prde = 0; 404 u32 ttl_dwords = 0; 405 dma_addr_t cd_paddr; 406 407 cd = (struct command_desc *)pp->cmdentry + tag; 408 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 409 410 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) &cd->cfis); 411 412 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 413 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 414 415 if (qc->tf.protocol == ATA_PROT_NCQ) { 416 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 417 cd->cfis[3], cd->cfis[11]); 418 } 419 420 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 421 if (ata_is_atapi(qc->tf.protocol)) { 422 desc_info |= ATAPI_CMD; 423 memset((void *)&cd->acmd, 0, 32); 424 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 425 } 426 427 if (qc->flags & ATA_QCFLAG_DMAMAP) 428 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 429 &ttl_dwords, cd_paddr); 430 431 if (qc->tf.protocol == ATA_PROT_NCQ) 432 desc_info |= FPDMA_QUEUED_CMD; 433 434 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 435 num_prde, 5); 436 437 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 438 desc_info, ttl_dwords, num_prde); 439 } 440 441 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 442 { 443 struct ata_port *ap = qc->ap; 444 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 445 void __iomem *hcr_base = host_priv->hcr_base; 446 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 447 448 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 449 ioread32(CQ + hcr_base), 450 ioread32(CA + hcr_base), 451 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 452 453 /* Simply queue command to the controller/device */ 454 iowrite32(1 << tag, CQ + hcr_base); 455 456 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 457 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 458 459 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 460 ioread32(CE + hcr_base), 461 ioread32(DE + hcr_base), 462 ioread32(CC + hcr_base), 463 ioread32(COMMANDSTAT + host_priv->csr_base)); 464 465 return 0; 466 } 467 468 static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in, 469 u32 val) 470 { 471 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 472 void __iomem *ssr_base = host_priv->ssr_base; 473 unsigned int sc_reg; 474 475 switch (sc_reg_in) { 476 case SCR_STATUS: 477 case SCR_ERROR: 478 case SCR_CONTROL: 479 case SCR_ACTIVE: 480 sc_reg = sc_reg_in; 481 break; 482 default: 483 return -EINVAL; 484 } 485 486 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 487 488 iowrite32(val, ssr_base + (sc_reg * 4)); 489 return 0; 490 } 491 492 static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in, 493 u32 *val) 494 { 495 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 496 void __iomem *ssr_base = host_priv->ssr_base; 497 unsigned int sc_reg; 498 499 switch (sc_reg_in) { 500 case SCR_STATUS: 501 case SCR_ERROR: 502 case SCR_CONTROL: 503 case SCR_ACTIVE: 504 sc_reg = sc_reg_in; 505 break; 506 default: 507 return -EINVAL; 508 } 509 510 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 511 512 *val = ioread32(ssr_base + (sc_reg * 4)); 513 return 0; 514 } 515 516 static void sata_fsl_freeze(struct ata_port *ap) 517 { 518 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 519 void __iomem *hcr_base = host_priv->hcr_base; 520 u32 temp; 521 522 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 523 ioread32(CQ + hcr_base), 524 ioread32(CA + hcr_base), 525 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 526 VPRINTK("CmdStat = 0x%x\n", 527 ioread32(host_priv->csr_base + COMMANDSTAT)); 528 529 /* disable interrupts on the controller/port */ 530 temp = ioread32(hcr_base + HCONTROL); 531 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 532 533 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 534 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 535 } 536 537 static void sata_fsl_thaw(struct ata_port *ap) 538 { 539 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 540 void __iomem *hcr_base = host_priv->hcr_base; 541 u32 temp; 542 543 /* ack. any pending IRQs for this controller/port */ 544 temp = ioread32(hcr_base + HSTATUS); 545 546 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 547 548 if (temp & 0x3F) 549 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 550 551 /* enable interrupts on the controller/port */ 552 temp = ioread32(hcr_base + HCONTROL); 553 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 554 555 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 556 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 557 } 558 559 /* 560 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor. 561 */ 562 static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd 563 *qc, 564 struct ata_port *ap) 565 { 566 struct sata_fsl_port_priv *pp = ap->private_data; 567 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 568 void __iomem *hcr_base = host_priv->hcr_base; 569 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 570 struct command_desc *cd; 571 572 cd = pp->cmdentry + tag; 573 574 ata_tf_from_fis(cd->sfis, &pp->tf); 575 } 576 577 static u8 sata_fsl_check_status(struct ata_port *ap) 578 { 579 struct sata_fsl_port_priv *pp = ap->private_data; 580 581 return pp->tf.command; 582 } 583 584 static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 585 { 586 struct sata_fsl_port_priv *pp = ap->private_data; 587 588 *tf = pp->tf; 589 } 590 591 static int sata_fsl_port_start(struct ata_port *ap) 592 { 593 struct device *dev = ap->host->dev; 594 struct sata_fsl_port_priv *pp; 595 int retval; 596 void *mem; 597 dma_addr_t mem_dma; 598 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 599 void __iomem *hcr_base = host_priv->hcr_base; 600 u32 temp; 601 602 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 603 if (!pp) 604 return -ENOMEM; 605 606 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 607 GFP_KERNEL); 608 if (!mem) { 609 kfree(pp); 610 return -ENOMEM; 611 } 612 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 613 614 pp->cmdslot = mem; 615 pp->cmdslot_paddr = mem_dma; 616 617 mem += SATA_FSL_CMD_SLOT_SIZE; 618 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 619 620 pp->cmdentry = mem; 621 pp->cmdentry_paddr = mem_dma; 622 623 ap->private_data = pp; 624 625 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 626 pp->cmdslot_paddr, pp->cmdentry_paddr); 627 628 /* Now, update the CHBA register in host controller cmd register set */ 629 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 630 631 /* 632 * Now, we can bring the controller on-line & also initiate 633 * the COMINIT sequence, we simply return here and the boot-probing 634 * & device discovery process is re-initiated by libATA using a 635 * Softreset EH (dummy) session. Hence, boot probing and device 636 * discovey will be part of sata_fsl_softreset() callback. 637 */ 638 639 temp = ioread32(hcr_base + HCONTROL); 640 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 641 642 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 643 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 644 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 645 646 #ifdef CONFIG_MPC8315_DS 647 /* 648 * Workaround for 8315DS board 3gbps link-up issue, 649 * currently limit SATA port to GEN1 speed 650 */ 651 sata_fsl_scr_read(ap, SCR_CONTROL, &temp); 652 temp &= ~(0xF << 4); 653 temp |= (0x1 << 4); 654 sata_fsl_scr_write(ap, SCR_CONTROL, temp); 655 656 sata_fsl_scr_read(ap, SCR_CONTROL, &temp); 657 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", 658 temp); 659 #endif 660 661 return 0; 662 } 663 664 static void sata_fsl_port_stop(struct ata_port *ap) 665 { 666 struct device *dev = ap->host->dev; 667 struct sata_fsl_port_priv *pp = ap->private_data; 668 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 669 void __iomem *hcr_base = host_priv->hcr_base; 670 u32 temp; 671 672 /* 673 * Force host controller to go off-line, aborting current operations 674 */ 675 temp = ioread32(hcr_base + HCONTROL); 676 temp &= ~HCONTROL_ONLINE_PHY_RST; 677 temp |= HCONTROL_FORCE_OFFLINE; 678 iowrite32(temp, hcr_base + HCONTROL); 679 680 /* Poll for controller to go offline - should happen immediately */ 681 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 682 683 ap->private_data = NULL; 684 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 685 pp->cmdslot, pp->cmdslot_paddr); 686 687 kfree(pp); 688 } 689 690 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 691 { 692 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 693 void __iomem *hcr_base = host_priv->hcr_base; 694 struct ata_taskfile tf; 695 u32 temp; 696 697 temp = ioread32(hcr_base + SIGNATURE); 698 699 VPRINTK("raw sig = 0x%x\n", temp); 700 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 701 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 702 703 tf.lbah = (temp >> 24) & 0xff; 704 tf.lbam = (temp >> 16) & 0xff; 705 tf.lbal = (temp >> 8) & 0xff; 706 tf.nsect = temp & 0xff; 707 708 return ata_dev_classify(&tf); 709 } 710 711 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 712 unsigned long deadline) 713 { 714 struct ata_port *ap = link->ap; 715 struct sata_fsl_port_priv *pp = ap->private_data; 716 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 717 void __iomem *hcr_base = host_priv->hcr_base; 718 u32 temp; 719 struct ata_taskfile tf; 720 u8 *cfis; 721 u32 Serror; 722 int i = 0; 723 unsigned long start_jiffies; 724 725 DPRINTK("in xx_softreset\n"); 726 727 try_offline_again: 728 /* 729 * Force host controller to go off-line, aborting current operations 730 */ 731 temp = ioread32(hcr_base + HCONTROL); 732 temp &= ~HCONTROL_ONLINE_PHY_RST; 733 iowrite32(temp, hcr_base + HCONTROL); 734 735 /* Poll for controller to go offline */ 736 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); 737 738 if (temp & ONLINE) { 739 ata_port_printk(ap, KERN_ERR, 740 "Softreset failed, not off-lined %d\n", i); 741 742 /* 743 * Try to offline controller atleast twice 744 */ 745 i++; 746 if (i == 2) 747 goto err; 748 else 749 goto try_offline_again; 750 } 751 752 DPRINTK("softreset, controller off-lined\n"); 753 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 754 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 755 756 /* 757 * PHY reset should remain asserted for atleast 1ms 758 */ 759 msleep(1); 760 761 /* 762 * Now, bring the host controller online again, this can take time 763 * as PHY reset and communication establishment, 1st D2H FIS and 764 * device signature update is done, on safe side assume 500ms 765 * NOTE : Host online status may be indicated immediately!! 766 */ 767 768 temp = ioread32(hcr_base + HCONTROL); 769 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 770 iowrite32(temp, hcr_base + HCONTROL); 771 772 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); 773 774 if (!(temp & ONLINE)) { 775 ata_port_printk(ap, KERN_ERR, 776 "Softreset failed, not on-lined\n"); 777 goto err; 778 } 779 780 DPRINTK("softreset, controller off-lined & on-lined\n"); 781 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 782 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 783 784 /* 785 * First, wait for the PHYRDY change to occur before waiting for 786 * the signature, and also verify if SStatus indicates device 787 * presence 788 */ 789 790 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); 791 if ((!(temp & 0x10)) || ata_link_offline(link)) { 792 ata_port_printk(ap, KERN_WARNING, 793 "No Device OR PHYRDY change,Hstatus = 0x%x\n", 794 ioread32(hcr_base + HSTATUS)); 795 goto err; 796 } 797 798 /* 799 * Wait for the first D2H from device,i.e,signature update notification 800 */ 801 start_jiffies = jiffies; 802 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, 803 500, jiffies_to_msecs(deadline - start_jiffies)); 804 805 if ((temp & 0xFF) != 0x18) { 806 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); 807 goto err; 808 } else { 809 ata_port_printk(ap, KERN_INFO, 810 "Signature Update detected @ %d msecs\n", 811 jiffies_to_msecs(jiffies - start_jiffies)); 812 } 813 814 /* 815 * Send a device reset (SRST) explicitly on command slot #0 816 * Check : will the command queue (reg) be cleared during offlining ?? 817 * Also we will be online only if Phy commn. has been established 818 * and device presence has been detected, therefore if we have 819 * reached here, we can send a command to the target device 820 */ 821 822 DPRINTK("Sending SRST/device reset\n"); 823 824 ata_tf_init(link->device, &tf); 825 cfis = (u8 *) &pp->cmdentry->cfis; 826 827 /* device reset/SRST is a control register update FIS, uses tag0 */ 828 sata_fsl_setup_cmd_hdr_entry(pp, 0, 829 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 830 831 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 832 ata_tf_to_fis(&tf, 0, 0, cfis); 833 834 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 835 cfis[0], cfis[1], cfis[2], cfis[3]); 836 837 /* 838 * Queue SRST command to the controller/device, ensure that no 839 * other commands are active on the controller/device 840 */ 841 842 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 843 ioread32(CQ + hcr_base), 844 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 845 846 iowrite32(0xFFFF, CC + hcr_base); 847 iowrite32(1, CQ + hcr_base); 848 849 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); 850 if (temp & 0x1) { 851 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); 852 853 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 854 ioread32(CQ + hcr_base), 855 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 856 857 sata_fsl_scr_read(ap, SCR_ERROR, &Serror); 858 859 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 860 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 861 DPRINTK("Serror = 0x%x\n", Serror); 862 goto err; 863 } 864 865 msleep(1); 866 867 /* 868 * SATA device enters reset state after receving a Control register 869 * FIS with SRST bit asserted and it awaits another H2D Control reg. 870 * FIS with SRST bit cleared, then the device does internal diags & 871 * initialization, followed by indicating it's initialization status 872 * using ATA signature D2H register FIS to the host controller. 873 */ 874 875 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 876 877 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 878 ata_tf_to_fis(&tf, 0, 0, cfis); 879 880 iowrite32(1, CQ + hcr_base); 881 msleep(150); /* ?? */ 882 883 /* 884 * The above command would have signalled an interrupt on command 885 * complete, which needs special handling, by clearing the Nth 886 * command bit of the CCreg 887 */ 888 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 889 890 DPRINTK("SATA FSL : Now checking device signature\n"); 891 892 *class = ATA_DEV_NONE; 893 894 /* Verify if SStatus indicates device presence */ 895 if (ata_link_online(link)) { 896 /* 897 * if we are here, device presence has been detected, 898 * 1st D2H FIS would have been received, but sfis in 899 * command desc. is not updated, but signature register 900 * would have been updated 901 */ 902 903 *class = sata_fsl_dev_classify(ap); 904 905 DPRINTK("class = %d\n", *class); 906 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 907 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 908 } 909 910 return 0; 911 912 err: 913 return -EIO; 914 } 915 916 static void sata_fsl_error_handler(struct ata_port *ap) 917 { 918 919 DPRINTK("in xx_error_handler\n"); 920 921 /* perform recovery */ 922 ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_std_hardreset, 923 ata_std_postreset); 924 } 925 926 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 927 { 928 if (qc->flags & ATA_QCFLAG_FAILED) 929 qc->err_mask |= AC_ERR_OTHER; 930 931 if (qc->err_mask) { 932 /* make DMA engine forget about the failed command */ 933 934 } 935 } 936 937 static void sata_fsl_irq_clear(struct ata_port *ap) 938 { 939 /* unused */ 940 } 941 942 static void sata_fsl_error_intr(struct ata_port *ap) 943 { 944 struct ata_link *link = &ap->link; 945 struct ata_eh_info *ehi = &link->eh_info; 946 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 947 void __iomem *hcr_base = host_priv->hcr_base; 948 u32 hstatus, dereg, cereg = 0, SError = 0; 949 unsigned int err_mask = 0, action = 0; 950 struct ata_queued_cmd *qc; 951 int freeze = 0; 952 953 hstatus = ioread32(hcr_base + HSTATUS); 954 cereg = ioread32(hcr_base + CE); 955 956 ata_ehi_clear_desc(ehi); 957 958 /* 959 * Handle & Clear SError 960 */ 961 962 sata_fsl_scr_read(ap, SCR_ERROR, &SError); 963 if (unlikely(SError & 0xFFFF0000)) { 964 sata_fsl_scr_write(ap, SCR_ERROR, SError); 965 err_mask |= AC_ERR_ATA_BUS; 966 } 967 968 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 969 hstatus, cereg, ioread32(hcr_base + DE), SError); 970 971 /* handle single device errors */ 972 if (cereg) { 973 /* 974 * clear the command error, also clears queue to the device 975 * in error, and we can (re)issue commands to this device. 976 * When a device is in error all commands queued into the 977 * host controller and at the device are considered aborted 978 * and the queue for that device is stopped. Now, after 979 * clearing the device error, we can issue commands to the 980 * device to interrogate it to find the source of the error. 981 */ 982 dereg = ioread32(hcr_base + DE); 983 iowrite32(dereg, hcr_base + DE); 984 iowrite32(cereg, hcr_base + CE); 985 986 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 987 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 988 /* 989 * We should consider this as non fatal error, and TF must 990 * be updated as done below. 991 */ 992 993 err_mask |= AC_ERR_DEV; 994 } 995 996 /* handle fatal errors */ 997 if (hstatus & FATAL_ERROR_DECODE) { 998 err_mask |= AC_ERR_ATA_BUS; 999 action |= ATA_EH_SOFTRESET; 1000 /* how will fatal error interrupts be completed ?? */ 1001 freeze = 1; 1002 } 1003 1004 /* Handle PHYRDY change notification */ 1005 if (hstatus & INT_ON_PHYRDY_CHG) { 1006 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1007 1008 /* Setup a soft-reset EH action */ 1009 ata_ehi_hotplugged(ehi); 1010 freeze = 1; 1011 } 1012 1013 /* record error info */ 1014 qc = ata_qc_from_tag(ap, link->active_tag); 1015 1016 if (qc) { 1017 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap); 1018 qc->err_mask |= err_mask; 1019 } else 1020 ehi->err_mask |= err_mask; 1021 1022 ehi->action |= action; 1023 ehi->serror |= SError; 1024 1025 /* freeze or abort */ 1026 if (freeze) 1027 ata_port_freeze(ap); 1028 else 1029 ata_port_abort(ap); 1030 } 1031 1032 static void sata_fsl_qc_complete(struct ata_queued_cmd *qc) 1033 { 1034 if (qc->flags & ATA_QCFLAG_RESULT_TF) { 1035 DPRINTK("xx_qc_complete called\n"); 1036 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap); 1037 } 1038 } 1039 1040 static void sata_fsl_host_intr(struct ata_port *ap) 1041 { 1042 struct ata_link *link = &ap->link; 1043 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1044 void __iomem *hcr_base = host_priv->hcr_base; 1045 u32 hstatus, qc_active = 0; 1046 struct ata_queued_cmd *qc; 1047 u32 SError; 1048 1049 hstatus = ioread32(hcr_base + HSTATUS); 1050 1051 sata_fsl_scr_read(ap, SCR_ERROR, &SError); 1052 1053 if (unlikely(SError & 0xFFFF0000)) { 1054 DPRINTK("serror @host_intr : 0x%x\n", SError); 1055 sata_fsl_error_intr(ap); 1056 1057 } 1058 1059 if (unlikely(hstatus & INT_ON_ERROR)) { 1060 DPRINTK("error interrupt!!\n"); 1061 sata_fsl_error_intr(ap); 1062 return; 1063 } 1064 1065 if (link->sactive) { /* only true for NCQ commands */ 1066 int i; 1067 /* Read command completed register */ 1068 qc_active = ioread32(hcr_base + CC); 1069 /* clear CC bit, this will also complete the interrupt */ 1070 iowrite32(qc_active, hcr_base + CC); 1071 1072 DPRINTK("Status of all queues :\n"); 1073 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1074 qc_active, ioread32(hcr_base + CA), 1075 ioread32(hcr_base + CE)); 1076 1077 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1078 if (qc_active & (1 << i)) { 1079 qc = ata_qc_from_tag(ap, i); 1080 if (qc) { 1081 sata_fsl_qc_complete(qc); 1082 ata_qc_complete(qc); 1083 } 1084 DPRINTK 1085 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1086 i, ioread32(hcr_base + CC), 1087 ioread32(hcr_base + CA)); 1088 } 1089 } 1090 return; 1091 1092 } else if (ap->qc_active) { 1093 iowrite32(1, hcr_base + CC); 1094 qc = ata_qc_from_tag(ap, link->active_tag); 1095 1096 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n", 1097 link->active_tag, ioread32(hcr_base + CC)); 1098 1099 if (qc) { 1100 sata_fsl_qc_complete(qc); 1101 ata_qc_complete(qc); 1102 } 1103 } else { 1104 /* Spurious Interrupt!! */ 1105 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1106 ioread32(hcr_base + CC)); 1107 return; 1108 } 1109 } 1110 1111 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1112 { 1113 struct ata_host *host = dev_instance; 1114 struct sata_fsl_host_priv *host_priv = host->private_data; 1115 void __iomem *hcr_base = host_priv->hcr_base; 1116 u32 interrupt_enables; 1117 unsigned handled = 0; 1118 struct ata_port *ap; 1119 1120 /* ack. any pending IRQs for this controller/port */ 1121 interrupt_enables = ioread32(hcr_base + HSTATUS); 1122 interrupt_enables &= 0x3F; 1123 1124 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1125 1126 if (!interrupt_enables) 1127 return IRQ_NONE; 1128 1129 spin_lock(&host->lock); 1130 1131 /* Assuming one port per host controller */ 1132 1133 ap = host->ports[0]; 1134 if (ap) { 1135 sata_fsl_host_intr(ap); 1136 } else { 1137 dev_printk(KERN_WARNING, host->dev, 1138 "interrupt on disabled port 0\n"); 1139 } 1140 1141 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1142 handled = 1; 1143 1144 spin_unlock(&host->lock); 1145 1146 return IRQ_RETVAL(handled); 1147 } 1148 1149 /* 1150 * Multiple ports are represented by multiple SATA controllers with 1151 * one port per controller 1152 */ 1153 static int sata_fsl_init_controller(struct ata_host *host) 1154 { 1155 struct sata_fsl_host_priv *host_priv = host->private_data; 1156 void __iomem *hcr_base = host_priv->hcr_base; 1157 u32 temp; 1158 1159 /* 1160 * NOTE : We cannot bring the controller online before setting 1161 * the CHBA, hence main controller initialization is done as 1162 * part of the port_start() callback 1163 */ 1164 1165 /* ack. any pending IRQs for this controller/port */ 1166 temp = ioread32(hcr_base + HSTATUS); 1167 if (temp & 0x3F) 1168 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1169 1170 /* Keep interrupts disabled on the controller */ 1171 temp = ioread32(hcr_base + HCONTROL); 1172 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1173 1174 /* Disable interrupt coalescing control(icc), for the moment */ 1175 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1176 iowrite32(0x01000000, hcr_base + ICC); 1177 1178 /* clear error registers, SError is cleared by libATA */ 1179 iowrite32(0x00000FFFF, hcr_base + CE); 1180 iowrite32(0x00000FFFF, hcr_base + DE); 1181 1182 /* initially assuming no Port multiplier, set CQPMP to 0 */ 1183 iowrite32(0x0, hcr_base + CQPMP); 1184 1185 /* 1186 * host controller will be brought on-line, during xx_port_start() 1187 * callback, that should also initiate the OOB, COMINIT sequence 1188 */ 1189 1190 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1191 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1192 1193 return 0; 1194 } 1195 1196 /* 1197 * scsi mid-layer and libata interface structures 1198 */ 1199 static struct scsi_host_template sata_fsl_sht = { 1200 .module = THIS_MODULE, 1201 .name = "sata_fsl", 1202 .ioctl = ata_scsi_ioctl, 1203 .queuecommand = ata_scsi_queuecmd, 1204 .change_queue_depth = ata_scsi_change_queue_depth, 1205 .can_queue = SATA_FSL_QUEUE_DEPTH, 1206 .this_id = ATA_SHT_THIS_ID, 1207 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1208 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 1209 .emulated = ATA_SHT_EMULATED, 1210 .use_clustering = ATA_SHT_USE_CLUSTERING, 1211 .proc_name = "sata_fsl", 1212 .dma_boundary = ATA_DMA_BOUNDARY, 1213 .slave_configure = ata_scsi_slave_config, 1214 .slave_destroy = ata_scsi_slave_destroy, 1215 .bios_param = ata_std_bios_param, 1216 }; 1217 1218 static const struct ata_port_operations sata_fsl_ops = { 1219 .check_status = sata_fsl_check_status, 1220 .check_altstatus = sata_fsl_check_status, 1221 .dev_select = ata_noop_dev_select, 1222 1223 .tf_read = sata_fsl_tf_read, 1224 1225 .qc_prep = sata_fsl_qc_prep, 1226 .qc_issue = sata_fsl_qc_issue, 1227 .irq_clear = sata_fsl_irq_clear, 1228 1229 .scr_read = sata_fsl_scr_read, 1230 .scr_write = sata_fsl_scr_write, 1231 1232 .freeze = sata_fsl_freeze, 1233 .thaw = sata_fsl_thaw, 1234 .error_handler = sata_fsl_error_handler, 1235 .post_internal_cmd = sata_fsl_post_internal_cmd, 1236 1237 .port_start = sata_fsl_port_start, 1238 .port_stop = sata_fsl_port_stop, 1239 }; 1240 1241 static const struct ata_port_info sata_fsl_port_info[] = { 1242 { 1243 .flags = SATA_FSL_HOST_FLAGS, 1244 .link_flags = SATA_FSL_HOST_LFLAGS, 1245 .pio_mask = 0x1f, /* pio 0-4 */ 1246 .udma_mask = 0x7f, /* udma 0-6 */ 1247 .port_ops = &sata_fsl_ops, 1248 }, 1249 }; 1250 1251 static int sata_fsl_probe(struct of_device *ofdev, 1252 const struct of_device_id *match) 1253 { 1254 int retval = 0; 1255 void __iomem *hcr_base = NULL; 1256 void __iomem *ssr_base = NULL; 1257 void __iomem *csr_base = NULL; 1258 struct sata_fsl_host_priv *host_priv = NULL; 1259 int irq; 1260 struct ata_host *host; 1261 1262 struct ata_port_info pi = sata_fsl_port_info[0]; 1263 const struct ata_port_info *ppi[] = { &pi, NULL }; 1264 1265 dev_printk(KERN_INFO, &ofdev->dev, 1266 "Sata FSL Platform/CSB Driver init\n"); 1267 1268 hcr_base = of_iomap(ofdev->node, 0); 1269 if (!hcr_base) 1270 goto error_exit_with_cleanup; 1271 1272 ssr_base = hcr_base + 0x100; 1273 csr_base = hcr_base + 0x140; 1274 1275 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1276 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1277 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1278 1279 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1280 if (!host_priv) 1281 goto error_exit_with_cleanup; 1282 1283 host_priv->hcr_base = hcr_base; 1284 host_priv->ssr_base = ssr_base; 1285 host_priv->csr_base = csr_base; 1286 1287 irq = irq_of_parse_and_map(ofdev->node, 0); 1288 if (irq < 0) { 1289 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); 1290 goto error_exit_with_cleanup; 1291 } 1292 host_priv->irq = irq; 1293 1294 /* allocate host structure */ 1295 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1296 1297 /* host->iomap is not used currently */ 1298 host->private_data = host_priv; 1299 1300 /* setup port(s) */ 1301 1302 host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base; 1303 host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base; 1304 1305 /* initialize host controller */ 1306 sata_fsl_init_controller(host); 1307 1308 /* 1309 * Now, register with libATA core, this will also initiate the 1310 * device discovery process, invoking our port_start() handler & 1311 * error_handler() to execute a dummy Softreset EH session 1312 */ 1313 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1314 &sata_fsl_sht); 1315 1316 dev_set_drvdata(&ofdev->dev, host); 1317 1318 return 0; 1319 1320 error_exit_with_cleanup: 1321 1322 if (hcr_base) 1323 iounmap(hcr_base); 1324 if (host_priv) 1325 kfree(host_priv); 1326 1327 return retval; 1328 } 1329 1330 static int sata_fsl_remove(struct of_device *ofdev) 1331 { 1332 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1333 struct sata_fsl_host_priv *host_priv = host->private_data; 1334 1335 ata_host_detach(host); 1336 1337 dev_set_drvdata(&ofdev->dev, NULL); 1338 1339 irq_dispose_mapping(host_priv->irq); 1340 iounmap(host_priv->hcr_base); 1341 kfree(host_priv); 1342 1343 return 0; 1344 } 1345 1346 static struct of_device_id fsl_sata_match[] = { 1347 { 1348 .compatible = "fsl,pq-sata", 1349 }, 1350 {}, 1351 }; 1352 1353 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1354 1355 static struct of_platform_driver fsl_sata_driver = { 1356 .name = "fsl-sata", 1357 .match_table = fsl_sata_match, 1358 .probe = sata_fsl_probe, 1359 .remove = sata_fsl_remove, 1360 }; 1361 1362 static int __init sata_fsl_init(void) 1363 { 1364 of_register_platform_driver(&fsl_sata_driver); 1365 return 0; 1366 } 1367 1368 static void __exit sata_fsl_exit(void) 1369 { 1370 of_unregister_platform_driver(&fsl_sata_driver); 1371 } 1372 1373 MODULE_LICENSE("GPL"); 1374 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1375 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1376 MODULE_VERSION("1.10"); 1377 1378 module_init(sata_fsl_init); 1379 module_exit(sata_fsl_exit); 1380