1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 22 #include <scsi/scsi_host.h> 23 #include <scsi/scsi_cmnd.h> 24 #include <linux/libata.h> 25 #include <asm/io.h> 26 #include <linux/of_platform.h> 27 28 /* Controller information */ 29 enum { 30 SATA_FSL_QUEUE_DEPTH = 16, 31 SATA_FSL_MAX_PRD = 63, 32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 34 35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 37 ATA_FLAG_PMP | ATA_FLAG_NCQ), 38 39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 42 43 /* 44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 45 * chained indirect PRDEs upto a max count of 63. 46 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will 47 * be setup as an indirect descriptor, pointing to it's next 48 * (contigious) PRDE. Though chained indirect PRDE arrays are 49 * supported,it will be more efficient to use a direct PRDT and 50 * a single chain/link to indirect PRDE array/PRDT. 51 */ 52 53 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 54 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 55 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 56 SATA_FSL_CMD_DESC_RSRVD = 16, 57 58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 59 SATA_FSL_CMD_DESC_SFIS_SZ + 60 SATA_FSL_CMD_DESC_ACMD_SZ + 61 SATA_FSL_CMD_DESC_RSRVD + 62 SATA_FSL_MAX_PRD * 16), 63 64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 65 (SATA_FSL_CMD_DESC_CFIS_SZ + 66 SATA_FSL_CMD_DESC_SFIS_SZ + 67 SATA_FSL_CMD_DESC_ACMD_SZ + 68 SATA_FSL_CMD_DESC_RSRVD), 69 70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 72 SATA_FSL_CMD_DESC_AR_SZ), 73 74 /* 75 * MPC8315 has two SATA controllers, SATA1 & SATA2 76 * (one port per controller) 77 * MPC837x has 2/4 controllers, one port per controller 78 */ 79 80 SATA_FSL_MAX_PORTS = 1, 81 82 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 83 }; 84 85 /* 86 * Host Controller command register set - per port 87 */ 88 enum { 89 CQ = 0, 90 CA = 8, 91 CC = 0x10, 92 CE = 0x18, 93 DE = 0x20, 94 CHBA = 0x24, 95 HSTATUS = 0x28, 96 HCONTROL = 0x2C, 97 CQPMP = 0x30, 98 SIGNATURE = 0x34, 99 ICC = 0x38, 100 101 /* 102 * Host Status Register (HStatus) bitdefs 103 */ 104 ONLINE = (1 << 31), 105 GOING_OFFLINE = (1 << 30), 106 BIST_ERR = (1 << 29), 107 108 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 109 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 110 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 111 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 112 FATAL_ERR_DATA_OVERRUN = (1 << 12), 113 FATAL_ERR_CRC_ERR_TX = (1 << 11), 114 FATAL_ERR_CRC_ERR_RX = (1 << 10), 115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 117 118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 119 FATAL_ERR_PARITY_ERR_TX | 120 FATAL_ERR_PARITY_ERR_RX | 121 FATAL_ERR_DATA_UNDERRUN | 122 FATAL_ERR_DATA_OVERRUN | 123 FATAL_ERR_CRC_ERR_TX | 124 FATAL_ERR_CRC_ERR_RX | 125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 126 127 INT_ON_FATAL_ERR = (1 << 5), 128 INT_ON_PHYRDY_CHG = (1 << 4), 129 130 INT_ON_SIGNATURE_UPDATE = (1 << 3), 131 INT_ON_SNOTIFY_UPDATE = (1 << 2), 132 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 133 INT_ON_CMD_COMPLETE = 1, 134 135 INT_ON_ERROR = INT_ON_FATAL_ERR | 136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 137 138 /* 139 * Host Control Register (HControl) bitdefs 140 */ 141 HCONTROL_ONLINE_PHY_RST = (1 << 31), 142 HCONTROL_FORCE_OFFLINE = (1 << 30), 143 HCONTROL_PARITY_PROT_MOD = (1 << 14), 144 HCONTROL_DPATH_PARITY = (1 << 12), 145 HCONTROL_SNOOP_ENABLE = (1 << 10), 146 HCONTROL_PMP_ATTACHED = (1 << 9), 147 HCONTROL_COPYOUT_STATFIS = (1 << 8), 148 IE_ON_FATAL_ERR = (1 << 5), 149 IE_ON_PHYRDY_CHG = (1 << 4), 150 IE_ON_SIGNATURE_UPDATE = (1 << 3), 151 IE_ON_SNOTIFY_UPDATE = (1 << 2), 152 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 153 IE_ON_CMD_COMPLETE = 1, 154 155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 156 IE_ON_SIGNATURE_UPDATE | 157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 158 159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 160 DATA_SNOOP_ENABLE = (1 << 22), 161 }; 162 163 /* 164 * SATA Superset Registers 165 */ 166 enum { 167 SSTATUS = 0, 168 SERROR = 4, 169 SCONTROL = 8, 170 SNOTIFY = 0xC, 171 }; 172 173 /* 174 * Control Status Register Set 175 */ 176 enum { 177 TRANSCFG = 0, 178 TRANSSTATUS = 4, 179 LINKCFG = 8, 180 LINKCFG1 = 0xC, 181 LINKCFG2 = 0x10, 182 LINKSTATUS = 0x14, 183 LINKSTATUS1 = 0x18, 184 PHYCTRLCFG = 0x1C, 185 COMMANDSTAT = 0x20, 186 }; 187 188 /* PHY (link-layer) configuration control */ 189 enum { 190 PHY_BIST_ENABLE = 0x01, 191 }; 192 193 /* 194 * Command Header Table entry, i.e, command slot 195 * 4 Dwords per command slot, command header size == 64 Dwords. 196 */ 197 struct cmdhdr_tbl_entry { 198 u32 cda; 199 u32 prde_fis_len; 200 u32 ttl; 201 u32 desc_info; 202 }; 203 204 /* 205 * Description information bitdefs 206 */ 207 enum { 208 VENDOR_SPECIFIC_BIST = (1 << 10), 209 CMD_DESC_SNOOP_ENABLE = (1 << 9), 210 FPDMA_QUEUED_CMD = (1 << 8), 211 SRST_CMD = (1 << 7), 212 BIST = (1 << 6), 213 ATAPI_CMD = (1 << 5), 214 }; 215 216 /* 217 * Command Descriptor 218 */ 219 struct command_desc { 220 u8 cfis[8 * 4]; 221 u8 sfis[8 * 4]; 222 u8 acmd[4 * 4]; 223 u8 fill[4 * 4]; 224 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 225 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 226 }; 227 228 /* 229 * Physical region table descriptor(PRD) 230 */ 231 232 struct prde { 233 u32 dba; 234 u8 fill[2 * 4]; 235 u32 ddc_and_ext; 236 }; 237 238 /* 239 * ata_port private data 240 * This is our per-port instance data. 241 */ 242 struct sata_fsl_port_priv { 243 struct cmdhdr_tbl_entry *cmdslot; 244 dma_addr_t cmdslot_paddr; 245 struct command_desc *cmdentry; 246 dma_addr_t cmdentry_paddr; 247 }; 248 249 /* 250 * ata_port->host_set private data 251 */ 252 struct sata_fsl_host_priv { 253 void __iomem *hcr_base; 254 void __iomem *ssr_base; 255 void __iomem *csr_base; 256 int irq; 257 }; 258 259 static inline unsigned int sata_fsl_tag(unsigned int tag, 260 void __iomem *hcr_base) 261 { 262 /* We let libATA core do actual (queue) tag allocation */ 263 264 /* all non NCQ/queued commands should have tag#0 */ 265 if (ata_tag_internal(tag)) { 266 DPRINTK("mapping internal cmds to tag#0\n"); 267 return 0; 268 } 269 270 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 271 DPRINTK("tag %d invalid : out of range\n", tag); 272 return 0; 273 } 274 275 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 276 DPRINTK("tag %d invalid : in use!!\n", tag); 277 return 0; 278 } 279 280 return tag; 281 } 282 283 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 284 unsigned int tag, u32 desc_info, 285 u32 data_xfer_len, u8 num_prde, 286 u8 fis_len) 287 { 288 dma_addr_t cmd_descriptor_address; 289 290 cmd_descriptor_address = pp->cmdentry_paddr + 291 tag * SATA_FSL_CMD_DESC_SIZE; 292 293 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 294 295 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 296 pp->cmdslot[tag].prde_fis_len = 297 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 298 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 299 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 300 301 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 302 pp->cmdslot[tag].cda, 303 pp->cmdslot[tag].prde_fis_len, 304 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 305 306 } 307 308 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 309 u32 *ttl, dma_addr_t cmd_desc_paddr) 310 { 311 struct scatterlist *sg; 312 unsigned int num_prde = 0; 313 u32 ttl_dwords = 0; 314 315 /* 316 * NOTE : direct & indirect prdt's are contigiously allocated 317 */ 318 struct prde *prd = (struct prde *)&((struct command_desc *) 319 cmd_desc)->prdt; 320 321 struct prde *prd_ptr_to_indirect_ext = NULL; 322 unsigned indirect_ext_segment_sz = 0; 323 dma_addr_t indirect_ext_segment_paddr; 324 unsigned int si; 325 326 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 327 328 indirect_ext_segment_paddr = cmd_desc_paddr + 329 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 330 331 for_each_sg(qc->sg, sg, qc->n_elem, si) { 332 dma_addr_t sg_addr = sg_dma_address(sg); 333 u32 sg_len = sg_dma_len(sg); 334 335 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n", 336 sg_addr, sg_len); 337 338 /* warn if each s/g element is not dword aligned */ 339 if (sg_addr & 0x03) 340 ata_port_printk(qc->ap, KERN_ERR, 341 "s/g addr unaligned : 0x%x\n", sg_addr); 342 if (sg_len & 0x03) 343 ata_port_printk(qc->ap, KERN_ERR, 344 "s/g len unaligned : 0x%x\n", sg_len); 345 346 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 347 sg_next(sg) != NULL) { 348 VPRINTK("setting indirect prde\n"); 349 prd_ptr_to_indirect_ext = prd; 350 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 351 indirect_ext_segment_sz = 0; 352 ++prd; 353 ++num_prde; 354 } 355 356 ttl_dwords += sg_len; 357 prd->dba = cpu_to_le32(sg_addr); 358 prd->ddc_and_ext = 359 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); 360 361 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 362 ttl_dwords, prd->dba, prd->ddc_and_ext); 363 364 ++num_prde; 365 ++prd; 366 if (prd_ptr_to_indirect_ext) 367 indirect_ext_segment_sz += sg_len; 368 } 369 370 if (prd_ptr_to_indirect_ext) { 371 /* set indirect extension flag along with indirect ext. size */ 372 prd_ptr_to_indirect_ext->ddc_and_ext = 373 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 374 DATA_SNOOP_ENABLE | 375 (indirect_ext_segment_sz & ~0x03))); 376 } 377 378 *ttl = ttl_dwords; 379 return num_prde; 380 } 381 382 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 383 { 384 struct ata_port *ap = qc->ap; 385 struct sata_fsl_port_priv *pp = ap->private_data; 386 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 387 void __iomem *hcr_base = host_priv->hcr_base; 388 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 389 struct command_desc *cd; 390 u32 desc_info = CMD_DESC_SNOOP_ENABLE; 391 u32 num_prde = 0; 392 u32 ttl_dwords = 0; 393 dma_addr_t cd_paddr; 394 395 cd = (struct command_desc *)pp->cmdentry + tag; 396 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 397 398 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 399 400 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 401 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 402 403 if (qc->tf.protocol == ATA_PROT_NCQ) { 404 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 405 cd->cfis[3], cd->cfis[11]); 406 } 407 408 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 409 if (ata_is_atapi(qc->tf.protocol)) { 410 desc_info |= ATAPI_CMD; 411 memset((void *)&cd->acmd, 0, 32); 412 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 413 } 414 415 if (qc->flags & ATA_QCFLAG_DMAMAP) 416 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 417 &ttl_dwords, cd_paddr); 418 419 if (qc->tf.protocol == ATA_PROT_NCQ) 420 desc_info |= FPDMA_QUEUED_CMD; 421 422 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 423 num_prde, 5); 424 425 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 426 desc_info, ttl_dwords, num_prde); 427 } 428 429 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 430 { 431 struct ata_port *ap = qc->ap; 432 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 433 void __iomem *hcr_base = host_priv->hcr_base; 434 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 435 436 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 437 ioread32(CQ + hcr_base), 438 ioread32(CA + hcr_base), 439 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 440 441 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 442 443 /* Simply queue command to the controller/device */ 444 iowrite32(1 << tag, CQ + hcr_base); 445 446 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 447 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 448 449 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 450 ioread32(CE + hcr_base), 451 ioread32(DE + hcr_base), 452 ioread32(CC + hcr_base), 453 ioread32(COMMANDSTAT + host_priv->csr_base)); 454 455 return 0; 456 } 457 458 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 459 { 460 struct sata_fsl_port_priv *pp = qc->ap->private_data; 461 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 462 void __iomem *hcr_base = host_priv->hcr_base; 463 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 464 struct command_desc *cd; 465 466 cd = pp->cmdentry + tag; 467 468 ata_tf_from_fis(cd->sfis, &qc->result_tf); 469 return true; 470 } 471 472 static int sata_fsl_scr_write(struct ata_link *link, 473 unsigned int sc_reg_in, u32 val) 474 { 475 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 476 void __iomem *ssr_base = host_priv->ssr_base; 477 unsigned int sc_reg; 478 479 switch (sc_reg_in) { 480 case SCR_STATUS: 481 case SCR_ERROR: 482 case SCR_CONTROL: 483 case SCR_ACTIVE: 484 sc_reg = sc_reg_in; 485 break; 486 default: 487 return -EINVAL; 488 } 489 490 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 491 492 iowrite32(val, ssr_base + (sc_reg * 4)); 493 return 0; 494 } 495 496 static int sata_fsl_scr_read(struct ata_link *link, 497 unsigned int sc_reg_in, u32 *val) 498 { 499 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 500 void __iomem *ssr_base = host_priv->ssr_base; 501 unsigned int sc_reg; 502 503 switch (sc_reg_in) { 504 case SCR_STATUS: 505 case SCR_ERROR: 506 case SCR_CONTROL: 507 case SCR_ACTIVE: 508 sc_reg = sc_reg_in; 509 break; 510 default: 511 return -EINVAL; 512 } 513 514 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 515 516 *val = ioread32(ssr_base + (sc_reg * 4)); 517 return 0; 518 } 519 520 static void sata_fsl_freeze(struct ata_port *ap) 521 { 522 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 523 void __iomem *hcr_base = host_priv->hcr_base; 524 u32 temp; 525 526 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 527 ioread32(CQ + hcr_base), 528 ioread32(CA + hcr_base), 529 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 530 VPRINTK("CmdStat = 0x%x\n", 531 ioread32(host_priv->csr_base + COMMANDSTAT)); 532 533 /* disable interrupts on the controller/port */ 534 temp = ioread32(hcr_base + HCONTROL); 535 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 536 537 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 538 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 539 } 540 541 static void sata_fsl_thaw(struct ata_port *ap) 542 { 543 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 544 void __iomem *hcr_base = host_priv->hcr_base; 545 u32 temp; 546 547 /* ack. any pending IRQs for this controller/port */ 548 temp = ioread32(hcr_base + HSTATUS); 549 550 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 551 552 if (temp & 0x3F) 553 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 554 555 /* enable interrupts on the controller/port */ 556 temp = ioread32(hcr_base + HCONTROL); 557 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 558 559 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 560 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 561 } 562 563 static void sata_fsl_pmp_attach(struct ata_port *ap) 564 { 565 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 566 void __iomem *hcr_base = host_priv->hcr_base; 567 u32 temp; 568 569 temp = ioread32(hcr_base + HCONTROL); 570 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 571 } 572 573 static void sata_fsl_pmp_detach(struct ata_port *ap) 574 { 575 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 576 void __iomem *hcr_base = host_priv->hcr_base; 577 u32 temp; 578 579 temp = ioread32(hcr_base + HCONTROL); 580 temp &= ~HCONTROL_PMP_ATTACHED; 581 iowrite32(temp, hcr_base + HCONTROL); 582 583 /* enable interrupts on the controller/port */ 584 temp = ioread32(hcr_base + HCONTROL); 585 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 586 587 } 588 589 static int sata_fsl_port_start(struct ata_port *ap) 590 { 591 struct device *dev = ap->host->dev; 592 struct sata_fsl_port_priv *pp; 593 void *mem; 594 dma_addr_t mem_dma; 595 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 596 void __iomem *hcr_base = host_priv->hcr_base; 597 u32 temp; 598 599 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 600 if (!pp) 601 return -ENOMEM; 602 603 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 604 GFP_KERNEL); 605 if (!mem) { 606 kfree(pp); 607 return -ENOMEM; 608 } 609 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 610 611 pp->cmdslot = mem; 612 pp->cmdslot_paddr = mem_dma; 613 614 mem += SATA_FSL_CMD_SLOT_SIZE; 615 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 616 617 pp->cmdentry = mem; 618 pp->cmdentry_paddr = mem_dma; 619 620 ap->private_data = pp; 621 622 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 623 pp->cmdslot_paddr, pp->cmdentry_paddr); 624 625 /* Now, update the CHBA register in host controller cmd register set */ 626 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 627 628 /* 629 * Now, we can bring the controller on-line & also initiate 630 * the COMINIT sequence, we simply return here and the boot-probing 631 * & device discovery process is re-initiated by libATA using a 632 * Softreset EH (dummy) session. Hence, boot probing and device 633 * discovey will be part of sata_fsl_softreset() callback. 634 */ 635 636 temp = ioread32(hcr_base + HCONTROL); 637 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 638 639 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 640 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 641 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 642 643 #ifdef CONFIG_MPC8315_DS 644 /* 645 * Workaround for 8315DS board 3gbps link-up issue, 646 * currently limit SATA port to GEN1 speed 647 */ 648 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 649 temp &= ~(0xF << 4); 650 temp |= (0x1 << 4); 651 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp); 652 653 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 654 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", 655 temp); 656 #endif 657 658 return 0; 659 } 660 661 static void sata_fsl_port_stop(struct ata_port *ap) 662 { 663 struct device *dev = ap->host->dev; 664 struct sata_fsl_port_priv *pp = ap->private_data; 665 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 666 void __iomem *hcr_base = host_priv->hcr_base; 667 u32 temp; 668 669 /* 670 * Force host controller to go off-line, aborting current operations 671 */ 672 temp = ioread32(hcr_base + HCONTROL); 673 temp &= ~HCONTROL_ONLINE_PHY_RST; 674 temp |= HCONTROL_FORCE_OFFLINE; 675 iowrite32(temp, hcr_base + HCONTROL); 676 677 /* Poll for controller to go offline - should happen immediately */ 678 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 679 680 ap->private_data = NULL; 681 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 682 pp->cmdslot, pp->cmdslot_paddr); 683 684 kfree(pp); 685 } 686 687 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 688 { 689 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 690 void __iomem *hcr_base = host_priv->hcr_base; 691 struct ata_taskfile tf; 692 u32 temp; 693 694 temp = ioread32(hcr_base + SIGNATURE); 695 696 VPRINTK("raw sig = 0x%x\n", temp); 697 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 698 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 699 700 tf.lbah = (temp >> 24) & 0xff; 701 tf.lbam = (temp >> 16) & 0xff; 702 tf.lbal = (temp >> 8) & 0xff; 703 tf.nsect = temp & 0xff; 704 705 return ata_dev_classify(&tf); 706 } 707 708 static int sata_fsl_prereset(struct ata_link *link, unsigned long deadline) 709 { 710 /* FIXME: Never skip softreset, sata_fsl_softreset() is 711 * combination of soft and hard resets. sata_fsl_softreset() 712 * needs to be splitted into soft and hard resets. 713 */ 714 return 0; 715 } 716 717 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 718 unsigned long deadline) 719 { 720 struct ata_port *ap = link->ap; 721 struct sata_fsl_port_priv *pp = ap->private_data; 722 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 723 void __iomem *hcr_base = host_priv->hcr_base; 724 int pmp = sata_srst_pmp(link); 725 u32 temp; 726 struct ata_taskfile tf; 727 u8 *cfis; 728 u32 Serror; 729 int i = 0; 730 unsigned long start_jiffies; 731 732 DPRINTK("in xx_softreset\n"); 733 734 if (pmp != SATA_PMP_CTRL_PORT) 735 goto issue_srst; 736 737 try_offline_again: 738 /* 739 * Force host controller to go off-line, aborting current operations 740 */ 741 temp = ioread32(hcr_base + HCONTROL); 742 temp &= ~HCONTROL_ONLINE_PHY_RST; 743 iowrite32(temp, hcr_base + HCONTROL); 744 745 /* Poll for controller to go offline */ 746 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); 747 748 if (temp & ONLINE) { 749 ata_port_printk(ap, KERN_ERR, 750 "Softreset failed, not off-lined %d\n", i); 751 752 /* 753 * Try to offline controller atleast twice 754 */ 755 i++; 756 if (i == 2) 757 goto err; 758 else 759 goto try_offline_again; 760 } 761 762 DPRINTK("softreset, controller off-lined\n"); 763 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 764 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 765 766 /* 767 * PHY reset should remain asserted for atleast 1ms 768 */ 769 msleep(1); 770 771 /* 772 * Now, bring the host controller online again, this can take time 773 * as PHY reset and communication establishment, 1st D2H FIS and 774 * device signature update is done, on safe side assume 500ms 775 * NOTE : Host online status may be indicated immediately!! 776 */ 777 778 temp = ioread32(hcr_base + HCONTROL); 779 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 780 temp |= HCONTROL_PMP_ATTACHED; 781 iowrite32(temp, hcr_base + HCONTROL); 782 783 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); 784 785 if (!(temp & ONLINE)) { 786 ata_port_printk(ap, KERN_ERR, 787 "Softreset failed, not on-lined\n"); 788 goto err; 789 } 790 791 DPRINTK("softreset, controller off-lined & on-lined\n"); 792 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 793 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 794 795 /* 796 * First, wait for the PHYRDY change to occur before waiting for 797 * the signature, and also verify if SStatus indicates device 798 * presence 799 */ 800 801 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); 802 if ((!(temp & 0x10)) || ata_link_offline(link)) { 803 ata_port_printk(ap, KERN_WARNING, 804 "No Device OR PHYRDY change,Hstatus = 0x%x\n", 805 ioread32(hcr_base + HSTATUS)); 806 *class = ATA_DEV_NONE; 807 goto out; 808 } 809 810 /* 811 * Wait for the first D2H from device,i.e,signature update notification 812 */ 813 start_jiffies = jiffies; 814 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, 815 500, jiffies_to_msecs(deadline - start_jiffies)); 816 817 if ((temp & 0xFF) != 0x18) { 818 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); 819 *class = ATA_DEV_NONE; 820 goto out; 821 } else { 822 ata_port_printk(ap, KERN_INFO, 823 "Signature Update detected @ %d msecs\n", 824 jiffies_to_msecs(jiffies - start_jiffies)); 825 } 826 827 /* 828 * Send a device reset (SRST) explicitly on command slot #0 829 * Check : will the command queue (reg) be cleared during offlining ?? 830 * Also we will be online only if Phy commn. has been established 831 * and device presence has been detected, therefore if we have 832 * reached here, we can send a command to the target device 833 */ 834 835 issue_srst: 836 DPRINTK("Sending SRST/device reset\n"); 837 838 ata_tf_init(link->device, &tf); 839 cfis = (u8 *) &pp->cmdentry->cfis; 840 841 /* device reset/SRST is a control register update FIS, uses tag0 */ 842 sata_fsl_setup_cmd_hdr_entry(pp, 0, 843 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 844 845 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 846 ata_tf_to_fis(&tf, pmp, 0, cfis); 847 848 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 849 cfis[0], cfis[1], cfis[2], cfis[3]); 850 851 /* 852 * Queue SRST command to the controller/device, ensure that no 853 * other commands are active on the controller/device 854 */ 855 856 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 857 ioread32(CQ + hcr_base), 858 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 859 860 iowrite32(0xFFFF, CC + hcr_base); 861 iowrite32(1, CQ + hcr_base); 862 863 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); 864 if (temp & 0x1) { 865 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); 866 867 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 868 ioread32(CQ + hcr_base), 869 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 870 871 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 872 873 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 874 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 875 DPRINTK("Serror = 0x%x\n", Serror); 876 goto err; 877 } 878 879 msleep(1); 880 881 /* 882 * SATA device enters reset state after receving a Control register 883 * FIS with SRST bit asserted and it awaits another H2D Control reg. 884 * FIS with SRST bit cleared, then the device does internal diags & 885 * initialization, followed by indicating it's initialization status 886 * using ATA signature D2H register FIS to the host controller. 887 */ 888 889 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 890 891 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 892 ata_tf_to_fis(&tf, pmp, 0, cfis); 893 894 if (pmp != SATA_PMP_CTRL_PORT) 895 iowrite32(pmp, CQPMP + hcr_base); 896 iowrite32(1, CQ + hcr_base); 897 msleep(150); /* ?? */ 898 899 /* 900 * The above command would have signalled an interrupt on command 901 * complete, which needs special handling, by clearing the Nth 902 * command bit of the CCreg 903 */ 904 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 905 906 DPRINTK("SATA FSL : Now checking device signature\n"); 907 908 *class = ATA_DEV_NONE; 909 910 /* Verify if SStatus indicates device presence */ 911 if (ata_link_online(link)) { 912 /* 913 * if we are here, device presence has been detected, 914 * 1st D2H FIS would have been received, but sfis in 915 * command desc. is not updated, but signature register 916 * would have been updated 917 */ 918 919 *class = sata_fsl_dev_classify(ap); 920 921 DPRINTK("class = %d\n", *class); 922 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 923 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 924 } 925 926 out: 927 return 0; 928 929 err: 930 return -EIO; 931 } 932 933 static void sata_fsl_error_handler(struct ata_port *ap) 934 { 935 936 DPRINTK("in xx_error_handler\n"); 937 sata_pmp_error_handler(ap); 938 939 } 940 941 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 942 { 943 if (qc->flags & ATA_QCFLAG_FAILED) 944 qc->err_mask |= AC_ERR_OTHER; 945 946 if (qc->err_mask) { 947 /* make DMA engine forget about the failed command */ 948 949 } 950 } 951 952 static void sata_fsl_error_intr(struct ata_port *ap) 953 { 954 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 955 void __iomem *hcr_base = host_priv->hcr_base; 956 u32 hstatus, dereg=0, cereg = 0, SError = 0; 957 unsigned int err_mask = 0, action = 0; 958 int freeze = 0, abort=0; 959 struct ata_link *link = NULL; 960 struct ata_queued_cmd *qc = NULL; 961 struct ata_eh_info *ehi; 962 963 hstatus = ioread32(hcr_base + HSTATUS); 964 cereg = ioread32(hcr_base + CE); 965 966 /* first, analyze and record host port events */ 967 link = &ap->link; 968 ehi = &link->eh_info; 969 ata_ehi_clear_desc(ehi); 970 971 /* 972 * Handle & Clear SError 973 */ 974 975 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 976 if (unlikely(SError & 0xFFFF0000)) { 977 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 978 } 979 980 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 981 hstatus, cereg, ioread32(hcr_base + DE), SError); 982 983 /* handle fatal errors */ 984 if (hstatus & FATAL_ERROR_DECODE) { 985 ehi->err_mask |= AC_ERR_ATA_BUS; 986 ehi->action |= ATA_EH_SOFTRESET; 987 988 /* 989 * Ignore serror in case of fatal errors as we always want 990 * to do a soft-reset of the FSL SATA controller. Analyzing 991 * serror may cause libata to schedule a hard-reset action, 992 * and hard-reset currently does not do controller 993 * offline/online, causing command timeouts and leads to an 994 * un-recoverable state, hence make libATA ignore 995 * autopsy in case of fatal errors. 996 */ 997 998 ehi->flags |= ATA_EHI_NO_AUTOPSY; 999 1000 freeze = 1; 1001 } 1002 1003 /* Handle PHYRDY change notification */ 1004 if (hstatus & INT_ON_PHYRDY_CHG) { 1005 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1006 1007 /* Setup a soft-reset EH action */ 1008 ata_ehi_hotplugged(ehi); 1009 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1010 freeze = 1; 1011 } 1012 1013 /* handle single device errors */ 1014 if (cereg) { 1015 /* 1016 * clear the command error, also clears queue to the device 1017 * in error, and we can (re)issue commands to this device. 1018 * When a device is in error all commands queued into the 1019 * host controller and at the device are considered aborted 1020 * and the queue for that device is stopped. Now, after 1021 * clearing the device error, we can issue commands to the 1022 * device to interrogate it to find the source of the error. 1023 */ 1024 abort = 1; 1025 1026 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 1027 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1028 1029 /* find out the offending link and qc */ 1030 if (ap->nr_pmp_links) { 1031 dereg = ioread32(hcr_base + DE); 1032 iowrite32(dereg, hcr_base + DE); 1033 iowrite32(cereg, hcr_base + CE); 1034 1035 if (dereg < ap->nr_pmp_links) { 1036 link = &ap->pmp_link[dereg]; 1037 ehi = &link->eh_info; 1038 qc = ata_qc_from_tag(ap, link->active_tag); 1039 /* 1040 * We should consider this as non fatal error, 1041 * and TF must be updated as done below. 1042 */ 1043 1044 err_mask |= AC_ERR_DEV; 1045 1046 } else { 1047 err_mask |= AC_ERR_HSM; 1048 action |= ATA_EH_HARDRESET; 1049 freeze = 1; 1050 } 1051 } else { 1052 dereg = ioread32(hcr_base + DE); 1053 iowrite32(dereg, hcr_base + DE); 1054 iowrite32(cereg, hcr_base + CE); 1055 1056 qc = ata_qc_from_tag(ap, link->active_tag); 1057 /* 1058 * We should consider this as non fatal error, 1059 * and TF must be updated as done below. 1060 */ 1061 err_mask |= AC_ERR_DEV; 1062 } 1063 } 1064 1065 /* record error info */ 1066 if (qc) { 1067 qc->err_mask |= err_mask; 1068 } else 1069 ehi->err_mask |= err_mask; 1070 1071 ehi->action |= action; 1072 1073 /* freeze or abort */ 1074 if (freeze) 1075 ata_port_freeze(ap); 1076 else if (abort) { 1077 if (qc) 1078 ata_link_abort(qc->dev->link); 1079 else 1080 ata_port_abort(ap); 1081 } 1082 } 1083 1084 static void sata_fsl_host_intr(struct ata_port *ap) 1085 { 1086 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1087 void __iomem *hcr_base = host_priv->hcr_base; 1088 u32 hstatus, qc_active = 0; 1089 struct ata_queued_cmd *qc; 1090 u32 SError; 1091 1092 hstatus = ioread32(hcr_base + HSTATUS); 1093 1094 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1095 1096 if (unlikely(SError & 0xFFFF0000)) { 1097 DPRINTK("serror @host_intr : 0x%x\n", SError); 1098 sata_fsl_error_intr(ap); 1099 1100 } 1101 1102 if (unlikely(hstatus & INT_ON_ERROR)) { 1103 DPRINTK("error interrupt!!\n"); 1104 sata_fsl_error_intr(ap); 1105 return; 1106 } 1107 1108 /* Read command completed register */ 1109 qc_active = ioread32(hcr_base + CC); 1110 1111 VPRINTK("Status of all queues :\n"); 1112 VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", 1113 qc_active, 1114 ioread32(hcr_base + CA), 1115 ioread32(hcr_base + CE), 1116 ioread32(hcr_base + CQ), 1117 ap->qc_active); 1118 1119 if (qc_active & ap->qc_active) { 1120 int i; 1121 /* clear CC bit, this will also complete the interrupt */ 1122 iowrite32(qc_active, hcr_base + CC); 1123 1124 DPRINTK("Status of all queues :\n"); 1125 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1126 qc_active, ioread32(hcr_base + CA), 1127 ioread32(hcr_base + CE)); 1128 1129 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1130 if (qc_active & (1 << i)) { 1131 qc = ata_qc_from_tag(ap, i); 1132 if (qc) { 1133 ata_qc_complete(qc); 1134 } 1135 DPRINTK 1136 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1137 i, ioread32(hcr_base + CC), 1138 ioread32(hcr_base + CA)); 1139 } 1140 } 1141 return; 1142 1143 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { 1144 iowrite32(1, hcr_base + CC); 1145 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1146 1147 DPRINTK("completing non-ncq cmd, CC=0x%x\n", 1148 ioread32(hcr_base + CC)); 1149 1150 if (qc) { 1151 ata_qc_complete(qc); 1152 } 1153 } else { 1154 /* Spurious Interrupt!! */ 1155 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1156 ioread32(hcr_base + CC)); 1157 iowrite32(qc_active, hcr_base + CC); 1158 return; 1159 } 1160 } 1161 1162 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1163 { 1164 struct ata_host *host = dev_instance; 1165 struct sata_fsl_host_priv *host_priv = host->private_data; 1166 void __iomem *hcr_base = host_priv->hcr_base; 1167 u32 interrupt_enables; 1168 unsigned handled = 0; 1169 struct ata_port *ap; 1170 1171 /* ack. any pending IRQs for this controller/port */ 1172 interrupt_enables = ioread32(hcr_base + HSTATUS); 1173 interrupt_enables &= 0x3F; 1174 1175 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1176 1177 if (!interrupt_enables) 1178 return IRQ_NONE; 1179 1180 spin_lock(&host->lock); 1181 1182 /* Assuming one port per host controller */ 1183 1184 ap = host->ports[0]; 1185 if (ap) { 1186 sata_fsl_host_intr(ap); 1187 } else { 1188 dev_printk(KERN_WARNING, host->dev, 1189 "interrupt on disabled port 0\n"); 1190 } 1191 1192 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1193 handled = 1; 1194 1195 spin_unlock(&host->lock); 1196 1197 return IRQ_RETVAL(handled); 1198 } 1199 1200 /* 1201 * Multiple ports are represented by multiple SATA controllers with 1202 * one port per controller 1203 */ 1204 static int sata_fsl_init_controller(struct ata_host *host) 1205 { 1206 struct sata_fsl_host_priv *host_priv = host->private_data; 1207 void __iomem *hcr_base = host_priv->hcr_base; 1208 u32 temp; 1209 1210 /* 1211 * NOTE : We cannot bring the controller online before setting 1212 * the CHBA, hence main controller initialization is done as 1213 * part of the port_start() callback 1214 */ 1215 1216 /* ack. any pending IRQs for this controller/port */ 1217 temp = ioread32(hcr_base + HSTATUS); 1218 if (temp & 0x3F) 1219 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1220 1221 /* Keep interrupts disabled on the controller */ 1222 temp = ioread32(hcr_base + HCONTROL); 1223 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1224 1225 /* Disable interrupt coalescing control(icc), for the moment */ 1226 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1227 iowrite32(0x01000000, hcr_base + ICC); 1228 1229 /* clear error registers, SError is cleared by libATA */ 1230 iowrite32(0x00000FFFF, hcr_base + CE); 1231 iowrite32(0x00000FFFF, hcr_base + DE); 1232 1233 /* 1234 * host controller will be brought on-line, during xx_port_start() 1235 * callback, that should also initiate the OOB, COMINIT sequence 1236 */ 1237 1238 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1239 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1240 1241 return 0; 1242 } 1243 1244 /* 1245 * scsi mid-layer and libata interface structures 1246 */ 1247 static struct scsi_host_template sata_fsl_sht = { 1248 ATA_NCQ_SHT("sata_fsl"), 1249 .can_queue = SATA_FSL_QUEUE_DEPTH, 1250 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1251 .dma_boundary = ATA_DMA_BOUNDARY, 1252 }; 1253 1254 static struct ata_port_operations sata_fsl_ops = { 1255 .inherits = &sata_pmp_port_ops, 1256 1257 .qc_prep = sata_fsl_qc_prep, 1258 .qc_issue = sata_fsl_qc_issue, 1259 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1260 1261 .scr_read = sata_fsl_scr_read, 1262 .scr_write = sata_fsl_scr_write, 1263 1264 .freeze = sata_fsl_freeze, 1265 .thaw = sata_fsl_thaw, 1266 .prereset = sata_fsl_prereset, 1267 .softreset = sata_fsl_softreset, 1268 .pmp_softreset = sata_fsl_softreset, 1269 .error_handler = sata_fsl_error_handler, 1270 .post_internal_cmd = sata_fsl_post_internal_cmd, 1271 1272 .port_start = sata_fsl_port_start, 1273 .port_stop = sata_fsl_port_stop, 1274 1275 .pmp_attach = sata_fsl_pmp_attach, 1276 .pmp_detach = sata_fsl_pmp_detach, 1277 }; 1278 1279 static const struct ata_port_info sata_fsl_port_info[] = { 1280 { 1281 .flags = SATA_FSL_HOST_FLAGS, 1282 .pio_mask = 0x1f, /* pio 0-4 */ 1283 .udma_mask = 0x7f, /* udma 0-6 */ 1284 .port_ops = &sata_fsl_ops, 1285 }, 1286 }; 1287 1288 static int sata_fsl_probe(struct of_device *ofdev, 1289 const struct of_device_id *match) 1290 { 1291 int retval = 0; 1292 void __iomem *hcr_base = NULL; 1293 void __iomem *ssr_base = NULL; 1294 void __iomem *csr_base = NULL; 1295 struct sata_fsl_host_priv *host_priv = NULL; 1296 int irq; 1297 struct ata_host *host; 1298 1299 struct ata_port_info pi = sata_fsl_port_info[0]; 1300 const struct ata_port_info *ppi[] = { &pi, NULL }; 1301 1302 dev_printk(KERN_INFO, &ofdev->dev, 1303 "Sata FSL Platform/CSB Driver init\n"); 1304 1305 hcr_base = of_iomap(ofdev->node, 0); 1306 if (!hcr_base) 1307 goto error_exit_with_cleanup; 1308 1309 ssr_base = hcr_base + 0x100; 1310 csr_base = hcr_base + 0x140; 1311 1312 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1313 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1314 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1315 1316 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1317 if (!host_priv) 1318 goto error_exit_with_cleanup; 1319 1320 host_priv->hcr_base = hcr_base; 1321 host_priv->ssr_base = ssr_base; 1322 host_priv->csr_base = csr_base; 1323 1324 irq = irq_of_parse_and_map(ofdev->node, 0); 1325 if (irq < 0) { 1326 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); 1327 goto error_exit_with_cleanup; 1328 } 1329 host_priv->irq = irq; 1330 1331 /* allocate host structure */ 1332 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1333 1334 /* host->iomap is not used currently */ 1335 host->private_data = host_priv; 1336 1337 /* initialize host controller */ 1338 sata_fsl_init_controller(host); 1339 1340 /* 1341 * Now, register with libATA core, this will also initiate the 1342 * device discovery process, invoking our port_start() handler & 1343 * error_handler() to execute a dummy Softreset EH session 1344 */ 1345 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1346 &sata_fsl_sht); 1347 1348 dev_set_drvdata(&ofdev->dev, host); 1349 1350 return 0; 1351 1352 error_exit_with_cleanup: 1353 1354 if (hcr_base) 1355 iounmap(hcr_base); 1356 if (host_priv) 1357 kfree(host_priv); 1358 1359 return retval; 1360 } 1361 1362 static int sata_fsl_remove(struct of_device *ofdev) 1363 { 1364 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1365 struct sata_fsl_host_priv *host_priv = host->private_data; 1366 1367 ata_host_detach(host); 1368 1369 dev_set_drvdata(&ofdev->dev, NULL); 1370 1371 irq_dispose_mapping(host_priv->irq); 1372 iounmap(host_priv->hcr_base); 1373 kfree(host_priv); 1374 1375 return 0; 1376 } 1377 1378 static struct of_device_id fsl_sata_match[] = { 1379 { 1380 .compatible = "fsl,pq-sata", 1381 }, 1382 {}, 1383 }; 1384 1385 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1386 1387 static struct of_platform_driver fsl_sata_driver = { 1388 .name = "fsl-sata", 1389 .match_table = fsl_sata_match, 1390 .probe = sata_fsl_probe, 1391 .remove = sata_fsl_remove, 1392 }; 1393 1394 static int __init sata_fsl_init(void) 1395 { 1396 of_register_platform_driver(&fsl_sata_driver); 1397 return 0; 1398 } 1399 1400 static void __exit sata_fsl_exit(void) 1401 { 1402 of_unregister_platform_driver(&fsl_sata_driver); 1403 } 1404 1405 MODULE_LICENSE("GPL"); 1406 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1407 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1408 MODULE_VERSION("1.10"); 1409 1410 module_init(sata_fsl_init); 1411 module_exit(sata_fsl_exit); 1412