1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007, 2011 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 23 #include <scsi/scsi_host.h> 24 #include <scsi/scsi_cmnd.h> 25 #include <linux/libata.h> 26 #include <asm/io.h> 27 #include <linux/of_platform.h> 28 29 /* Controller information */ 30 enum { 31 SATA_FSL_QUEUE_DEPTH = 16, 32 SATA_FSL_MAX_PRD = 63, 33 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 34 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 35 36 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 37 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN), 38 39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 42 43 /* 44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 45 * chained indirect PRDEs up to a max count of 63. 46 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will 47 * be setup as an indirect descriptor, pointing to it's next 48 * (contiguous) PRDE. Though chained indirect PRDE arrays are 49 * supported,it will be more efficient to use a direct PRDT and 50 * a single chain/link to indirect PRDE array/PRDT. 51 */ 52 53 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 54 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 55 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 56 SATA_FSL_CMD_DESC_RSRVD = 16, 57 58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 59 SATA_FSL_CMD_DESC_SFIS_SZ + 60 SATA_FSL_CMD_DESC_ACMD_SZ + 61 SATA_FSL_CMD_DESC_RSRVD + 62 SATA_FSL_MAX_PRD * 16), 63 64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 65 (SATA_FSL_CMD_DESC_CFIS_SZ + 66 SATA_FSL_CMD_DESC_SFIS_SZ + 67 SATA_FSL_CMD_DESC_ACMD_SZ + 68 SATA_FSL_CMD_DESC_RSRVD), 69 70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 72 SATA_FSL_CMD_DESC_AR_SZ), 73 74 /* 75 * MPC8315 has two SATA controllers, SATA1 & SATA2 76 * (one port per controller) 77 * MPC837x has 2/4 controllers, one port per controller 78 */ 79 80 SATA_FSL_MAX_PORTS = 1, 81 82 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 83 }; 84 85 /* 86 * Host Controller command register set - per port 87 */ 88 enum { 89 CQ = 0, 90 CA = 8, 91 CC = 0x10, 92 CE = 0x18, 93 DE = 0x20, 94 CHBA = 0x24, 95 HSTATUS = 0x28, 96 HCONTROL = 0x2C, 97 CQPMP = 0x30, 98 SIGNATURE = 0x34, 99 ICC = 0x38, 100 101 /* 102 * Host Status Register (HStatus) bitdefs 103 */ 104 ONLINE = (1 << 31), 105 GOING_OFFLINE = (1 << 30), 106 BIST_ERR = (1 << 29), 107 108 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 109 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 110 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 111 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 112 FATAL_ERR_DATA_OVERRUN = (1 << 12), 113 FATAL_ERR_CRC_ERR_TX = (1 << 11), 114 FATAL_ERR_CRC_ERR_RX = (1 << 10), 115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 117 118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 119 FATAL_ERR_PARITY_ERR_TX | 120 FATAL_ERR_PARITY_ERR_RX | 121 FATAL_ERR_DATA_UNDERRUN | 122 FATAL_ERR_DATA_OVERRUN | 123 FATAL_ERR_CRC_ERR_TX | 124 FATAL_ERR_CRC_ERR_RX | 125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 126 127 INT_ON_FATAL_ERR = (1 << 5), 128 INT_ON_PHYRDY_CHG = (1 << 4), 129 130 INT_ON_SIGNATURE_UPDATE = (1 << 3), 131 INT_ON_SNOTIFY_UPDATE = (1 << 2), 132 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 133 INT_ON_CMD_COMPLETE = 1, 134 135 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | 136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 137 138 /* 139 * Host Control Register (HControl) bitdefs 140 */ 141 HCONTROL_ONLINE_PHY_RST = (1 << 31), 142 HCONTROL_FORCE_OFFLINE = (1 << 30), 143 HCONTROL_PARITY_PROT_MOD = (1 << 14), 144 HCONTROL_DPATH_PARITY = (1 << 12), 145 HCONTROL_SNOOP_ENABLE = (1 << 10), 146 HCONTROL_PMP_ATTACHED = (1 << 9), 147 HCONTROL_COPYOUT_STATFIS = (1 << 8), 148 IE_ON_FATAL_ERR = (1 << 5), 149 IE_ON_PHYRDY_CHG = (1 << 4), 150 IE_ON_SIGNATURE_UPDATE = (1 << 3), 151 IE_ON_SNOTIFY_UPDATE = (1 << 2), 152 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 153 IE_ON_CMD_COMPLETE = 1, 154 155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 156 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | 157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 158 159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 160 DATA_SNOOP_ENABLE_V1 = (1 << 22), 161 DATA_SNOOP_ENABLE_V2 = (1 << 28), 162 }; 163 164 /* 165 * SATA Superset Registers 166 */ 167 enum { 168 SSTATUS = 0, 169 SERROR = 4, 170 SCONTROL = 8, 171 SNOTIFY = 0xC, 172 }; 173 174 /* 175 * Control Status Register Set 176 */ 177 enum { 178 TRANSCFG = 0, 179 TRANSSTATUS = 4, 180 LINKCFG = 8, 181 LINKCFG1 = 0xC, 182 LINKCFG2 = 0x10, 183 LINKSTATUS = 0x14, 184 LINKSTATUS1 = 0x18, 185 PHYCTRLCFG = 0x1C, 186 COMMANDSTAT = 0x20, 187 }; 188 189 /* TRANSCFG (transport-layer) configuration control */ 190 enum { 191 TRANSCFG_RX_WATER_MARK = (1 << 4), 192 }; 193 194 /* PHY (link-layer) configuration control */ 195 enum { 196 PHY_BIST_ENABLE = 0x01, 197 }; 198 199 /* 200 * Command Header Table entry, i.e, command slot 201 * 4 Dwords per command slot, command header size == 64 Dwords. 202 */ 203 struct cmdhdr_tbl_entry { 204 u32 cda; 205 u32 prde_fis_len; 206 u32 ttl; 207 u32 desc_info; 208 }; 209 210 /* 211 * Description information bitdefs 212 */ 213 enum { 214 CMD_DESC_RES = (1 << 11), 215 VENDOR_SPECIFIC_BIST = (1 << 10), 216 CMD_DESC_SNOOP_ENABLE = (1 << 9), 217 FPDMA_QUEUED_CMD = (1 << 8), 218 SRST_CMD = (1 << 7), 219 BIST = (1 << 6), 220 ATAPI_CMD = (1 << 5), 221 }; 222 223 /* 224 * Command Descriptor 225 */ 226 struct command_desc { 227 u8 cfis[8 * 4]; 228 u8 sfis[8 * 4]; 229 u8 acmd[4 * 4]; 230 u8 fill[4 * 4]; 231 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 232 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 233 }; 234 235 /* 236 * Physical region table descriptor(PRD) 237 */ 238 239 struct prde { 240 u32 dba; 241 u8 fill[2 * 4]; 242 u32 ddc_and_ext; 243 }; 244 245 /* 246 * ata_port private data 247 * This is our per-port instance data. 248 */ 249 struct sata_fsl_port_priv { 250 struct cmdhdr_tbl_entry *cmdslot; 251 dma_addr_t cmdslot_paddr; 252 struct command_desc *cmdentry; 253 dma_addr_t cmdentry_paddr; 254 }; 255 256 /* 257 * ata_port->host_set private data 258 */ 259 struct sata_fsl_host_priv { 260 void __iomem *hcr_base; 261 void __iomem *ssr_base; 262 void __iomem *csr_base; 263 int irq; 264 int data_snoop; 265 }; 266 267 static inline unsigned int sata_fsl_tag(unsigned int tag, 268 void __iomem *hcr_base) 269 { 270 /* We let libATA core do actual (queue) tag allocation */ 271 272 /* all non NCQ/queued commands should have tag#0 */ 273 if (ata_tag_internal(tag)) { 274 DPRINTK("mapping internal cmds to tag#0\n"); 275 return 0; 276 } 277 278 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 279 DPRINTK("tag %d invalid : out of range\n", tag); 280 return 0; 281 } 282 283 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 284 DPRINTK("tag %d invalid : in use!!\n", tag); 285 return 0; 286 } 287 288 return tag; 289 } 290 291 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 292 unsigned int tag, u32 desc_info, 293 u32 data_xfer_len, u8 num_prde, 294 u8 fis_len) 295 { 296 dma_addr_t cmd_descriptor_address; 297 298 cmd_descriptor_address = pp->cmdentry_paddr + 299 tag * SATA_FSL_CMD_DESC_SIZE; 300 301 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 302 303 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 304 pp->cmdslot[tag].prde_fis_len = 305 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 306 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 307 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 308 309 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 310 pp->cmdslot[tag].cda, 311 pp->cmdslot[tag].prde_fis_len, 312 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 313 314 } 315 316 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 317 u32 *ttl, dma_addr_t cmd_desc_paddr, 318 int data_snoop) 319 { 320 struct scatterlist *sg; 321 unsigned int num_prde = 0; 322 u32 ttl_dwords = 0; 323 324 /* 325 * NOTE : direct & indirect prdt's are contiguously allocated 326 */ 327 struct prde *prd = (struct prde *)&((struct command_desc *) 328 cmd_desc)->prdt; 329 330 struct prde *prd_ptr_to_indirect_ext = NULL; 331 unsigned indirect_ext_segment_sz = 0; 332 dma_addr_t indirect_ext_segment_paddr; 333 unsigned int si; 334 335 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 336 337 indirect_ext_segment_paddr = cmd_desc_paddr + 338 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 339 340 for_each_sg(qc->sg, sg, qc->n_elem, si) { 341 dma_addr_t sg_addr = sg_dma_address(sg); 342 u32 sg_len = sg_dma_len(sg); 343 344 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", 345 (unsigned long long)sg_addr, sg_len); 346 347 /* warn if each s/g element is not dword aligned */ 348 if (sg_addr & 0x03) 349 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n", 350 (unsigned long long)sg_addr); 351 if (sg_len & 0x03) 352 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n", 353 sg_len); 354 355 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 356 sg_next(sg) != NULL) { 357 VPRINTK("setting indirect prde\n"); 358 prd_ptr_to_indirect_ext = prd; 359 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 360 indirect_ext_segment_sz = 0; 361 ++prd; 362 ++num_prde; 363 } 364 365 ttl_dwords += sg_len; 366 prd->dba = cpu_to_le32(sg_addr); 367 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); 368 369 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 370 ttl_dwords, prd->dba, prd->ddc_and_ext); 371 372 ++num_prde; 373 ++prd; 374 if (prd_ptr_to_indirect_ext) 375 indirect_ext_segment_sz += sg_len; 376 } 377 378 if (prd_ptr_to_indirect_ext) { 379 /* set indirect extension flag along with indirect ext. size */ 380 prd_ptr_to_indirect_ext->ddc_and_ext = 381 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 382 data_snoop | 383 (indirect_ext_segment_sz & ~0x03))); 384 } 385 386 *ttl = ttl_dwords; 387 return num_prde; 388 } 389 390 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 391 { 392 struct ata_port *ap = qc->ap; 393 struct sata_fsl_port_priv *pp = ap->private_data; 394 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 395 void __iomem *hcr_base = host_priv->hcr_base; 396 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 397 struct command_desc *cd; 398 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 399 u32 num_prde = 0; 400 u32 ttl_dwords = 0; 401 dma_addr_t cd_paddr; 402 403 cd = (struct command_desc *)pp->cmdentry + tag; 404 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 405 406 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 407 408 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 409 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 410 411 if (qc->tf.protocol == ATA_PROT_NCQ) { 412 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 413 cd->cfis[3], cd->cfis[11]); 414 } 415 416 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 417 if (ata_is_atapi(qc->tf.protocol)) { 418 desc_info |= ATAPI_CMD; 419 memset((void *)&cd->acmd, 0, 32); 420 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 421 } 422 423 if (qc->flags & ATA_QCFLAG_DMAMAP) 424 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 425 &ttl_dwords, cd_paddr, 426 host_priv->data_snoop); 427 428 if (qc->tf.protocol == ATA_PROT_NCQ) 429 desc_info |= FPDMA_QUEUED_CMD; 430 431 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 432 num_prde, 5); 433 434 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 435 desc_info, ttl_dwords, num_prde); 436 } 437 438 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 439 { 440 struct ata_port *ap = qc->ap; 441 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 442 void __iomem *hcr_base = host_priv->hcr_base; 443 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 444 445 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 446 ioread32(CQ + hcr_base), 447 ioread32(CA + hcr_base), 448 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 449 450 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 451 452 /* Simply queue command to the controller/device */ 453 iowrite32(1 << tag, CQ + hcr_base); 454 455 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 456 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 457 458 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 459 ioread32(CE + hcr_base), 460 ioread32(DE + hcr_base), 461 ioread32(CC + hcr_base), 462 ioread32(COMMANDSTAT + host_priv->csr_base)); 463 464 return 0; 465 } 466 467 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 468 { 469 struct sata_fsl_port_priv *pp = qc->ap->private_data; 470 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 471 void __iomem *hcr_base = host_priv->hcr_base; 472 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 473 struct command_desc *cd; 474 475 cd = pp->cmdentry + tag; 476 477 ata_tf_from_fis(cd->sfis, &qc->result_tf); 478 return true; 479 } 480 481 static int sata_fsl_scr_write(struct ata_link *link, 482 unsigned int sc_reg_in, u32 val) 483 { 484 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 485 void __iomem *ssr_base = host_priv->ssr_base; 486 unsigned int sc_reg; 487 488 switch (sc_reg_in) { 489 case SCR_STATUS: 490 case SCR_ERROR: 491 case SCR_CONTROL: 492 case SCR_ACTIVE: 493 sc_reg = sc_reg_in; 494 break; 495 default: 496 return -EINVAL; 497 } 498 499 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 500 501 iowrite32(val, ssr_base + (sc_reg * 4)); 502 return 0; 503 } 504 505 static int sata_fsl_scr_read(struct ata_link *link, 506 unsigned int sc_reg_in, u32 *val) 507 { 508 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 509 void __iomem *ssr_base = host_priv->ssr_base; 510 unsigned int sc_reg; 511 512 switch (sc_reg_in) { 513 case SCR_STATUS: 514 case SCR_ERROR: 515 case SCR_CONTROL: 516 case SCR_ACTIVE: 517 sc_reg = sc_reg_in; 518 break; 519 default: 520 return -EINVAL; 521 } 522 523 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 524 525 *val = ioread32(ssr_base + (sc_reg * 4)); 526 return 0; 527 } 528 529 static void sata_fsl_freeze(struct ata_port *ap) 530 { 531 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 532 void __iomem *hcr_base = host_priv->hcr_base; 533 u32 temp; 534 535 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 536 ioread32(CQ + hcr_base), 537 ioread32(CA + hcr_base), 538 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 539 VPRINTK("CmdStat = 0x%x\n", 540 ioread32(host_priv->csr_base + COMMANDSTAT)); 541 542 /* disable interrupts on the controller/port */ 543 temp = ioread32(hcr_base + HCONTROL); 544 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 545 546 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 547 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 548 } 549 550 static void sata_fsl_thaw(struct ata_port *ap) 551 { 552 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 553 void __iomem *hcr_base = host_priv->hcr_base; 554 u32 temp; 555 556 /* ack. any pending IRQs for this controller/port */ 557 temp = ioread32(hcr_base + HSTATUS); 558 559 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 560 561 if (temp & 0x3F) 562 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 563 564 /* enable interrupts on the controller/port */ 565 temp = ioread32(hcr_base + HCONTROL); 566 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 567 568 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 569 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 570 } 571 572 static void sata_fsl_pmp_attach(struct ata_port *ap) 573 { 574 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 575 void __iomem *hcr_base = host_priv->hcr_base; 576 u32 temp; 577 578 temp = ioread32(hcr_base + HCONTROL); 579 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 580 } 581 582 static void sata_fsl_pmp_detach(struct ata_port *ap) 583 { 584 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 585 void __iomem *hcr_base = host_priv->hcr_base; 586 u32 temp; 587 588 temp = ioread32(hcr_base + HCONTROL); 589 temp &= ~HCONTROL_PMP_ATTACHED; 590 iowrite32(temp, hcr_base + HCONTROL); 591 592 /* enable interrupts on the controller/port */ 593 temp = ioread32(hcr_base + HCONTROL); 594 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 595 596 } 597 598 static int sata_fsl_port_start(struct ata_port *ap) 599 { 600 struct device *dev = ap->host->dev; 601 struct sata_fsl_port_priv *pp; 602 void *mem; 603 dma_addr_t mem_dma; 604 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 605 void __iomem *hcr_base = host_priv->hcr_base; 606 u32 temp; 607 608 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 609 if (!pp) 610 return -ENOMEM; 611 612 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 613 GFP_KERNEL); 614 if (!mem) { 615 kfree(pp); 616 return -ENOMEM; 617 } 618 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 619 620 pp->cmdslot = mem; 621 pp->cmdslot_paddr = mem_dma; 622 623 mem += SATA_FSL_CMD_SLOT_SIZE; 624 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 625 626 pp->cmdentry = mem; 627 pp->cmdentry_paddr = mem_dma; 628 629 ap->private_data = pp; 630 631 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 632 pp->cmdslot_paddr, pp->cmdentry_paddr); 633 634 /* Now, update the CHBA register in host controller cmd register set */ 635 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 636 637 /* 638 * Now, we can bring the controller on-line & also initiate 639 * the COMINIT sequence, we simply return here and the boot-probing 640 * & device discovery process is re-initiated by libATA using a 641 * Softreset EH (dummy) session. Hence, boot probing and device 642 * discovey will be part of sata_fsl_softreset() callback. 643 */ 644 645 temp = ioread32(hcr_base + HCONTROL); 646 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 647 648 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 649 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 650 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 651 652 #ifdef CONFIG_MPC8315_DS 653 /* 654 * Workaround for 8315DS board 3gbps link-up issue, 655 * currently limit SATA port to GEN1 speed 656 */ 657 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 658 temp &= ~(0xF << 4); 659 temp |= (0x1 << 4); 660 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp); 661 662 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 663 dev_warn(dev, "scr_control, speed limited to %x\n", temp); 664 #endif 665 666 return 0; 667 } 668 669 static void sata_fsl_port_stop(struct ata_port *ap) 670 { 671 struct device *dev = ap->host->dev; 672 struct sata_fsl_port_priv *pp = ap->private_data; 673 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 674 void __iomem *hcr_base = host_priv->hcr_base; 675 u32 temp; 676 677 /* 678 * Force host controller to go off-line, aborting current operations 679 */ 680 temp = ioread32(hcr_base + HCONTROL); 681 temp &= ~HCONTROL_ONLINE_PHY_RST; 682 temp |= HCONTROL_FORCE_OFFLINE; 683 iowrite32(temp, hcr_base + HCONTROL); 684 685 /* Poll for controller to go offline - should happen immediately */ 686 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 687 688 ap->private_data = NULL; 689 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 690 pp->cmdslot, pp->cmdslot_paddr); 691 692 kfree(pp); 693 } 694 695 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 696 { 697 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 698 void __iomem *hcr_base = host_priv->hcr_base; 699 struct ata_taskfile tf; 700 u32 temp; 701 702 temp = ioread32(hcr_base + SIGNATURE); 703 704 VPRINTK("raw sig = 0x%x\n", temp); 705 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 706 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 707 708 tf.lbah = (temp >> 24) & 0xff; 709 tf.lbam = (temp >> 16) & 0xff; 710 tf.lbal = (temp >> 8) & 0xff; 711 tf.nsect = temp & 0xff; 712 713 return ata_dev_classify(&tf); 714 } 715 716 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, 717 unsigned long deadline) 718 { 719 struct ata_port *ap = link->ap; 720 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 721 void __iomem *hcr_base = host_priv->hcr_base; 722 u32 temp; 723 int i = 0; 724 unsigned long start_jiffies; 725 726 DPRINTK("in xx_hardreset\n"); 727 728 try_offline_again: 729 /* 730 * Force host controller to go off-line, aborting current operations 731 */ 732 temp = ioread32(hcr_base + HCONTROL); 733 temp &= ~HCONTROL_ONLINE_PHY_RST; 734 iowrite32(temp, hcr_base + HCONTROL); 735 736 /* Poll for controller to go offline */ 737 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 738 1, 500); 739 740 if (temp & ONLINE) { 741 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i); 742 743 /* 744 * Try to offline controller atleast twice 745 */ 746 i++; 747 if (i == 2) 748 goto err; 749 else 750 goto try_offline_again; 751 } 752 753 DPRINTK("hardreset, controller off-lined\n"); 754 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 755 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 756 757 /* 758 * PHY reset should remain asserted for atleast 1ms 759 */ 760 ata_msleep(ap, 1); 761 762 /* 763 * Now, bring the host controller online again, this can take time 764 * as PHY reset and communication establishment, 1st D2H FIS and 765 * device signature update is done, on safe side assume 500ms 766 * NOTE : Host online status may be indicated immediately!! 767 */ 768 769 temp = ioread32(hcr_base + HCONTROL); 770 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 771 temp |= HCONTROL_PMP_ATTACHED; 772 iowrite32(temp, hcr_base + HCONTROL); 773 774 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); 775 776 if (!(temp & ONLINE)) { 777 ata_port_err(ap, "Hardreset failed, not on-lined\n"); 778 goto err; 779 } 780 781 DPRINTK("hardreset, controller off-lined & on-lined\n"); 782 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 783 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 784 785 /* 786 * First, wait for the PHYRDY change to occur before waiting for 787 * the signature, and also verify if SStatus indicates device 788 * presence 789 */ 790 791 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); 792 if ((!(temp & 0x10)) || ata_link_offline(link)) { 793 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n", 794 ioread32(hcr_base + HSTATUS)); 795 *class = ATA_DEV_NONE; 796 return 0; 797 } 798 799 /* 800 * Wait for the first D2H from device,i.e,signature update notification 801 */ 802 start_jiffies = jiffies; 803 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, 804 500, jiffies_to_msecs(deadline - start_jiffies)); 805 806 if ((temp & 0xFF) != 0x18) { 807 ata_port_warn(ap, "No Signature Update\n"); 808 *class = ATA_DEV_NONE; 809 goto do_followup_srst; 810 } else { 811 ata_port_info(ap, "Signature Update detected @ %d msecs\n", 812 jiffies_to_msecs(jiffies - start_jiffies)); 813 *class = sata_fsl_dev_classify(ap); 814 return 0; 815 } 816 817 do_followup_srst: 818 /* 819 * request libATA to perform follow-up softreset 820 */ 821 return -EAGAIN; 822 823 err: 824 return -EIO; 825 } 826 827 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 828 unsigned long deadline) 829 { 830 struct ata_port *ap = link->ap; 831 struct sata_fsl_port_priv *pp = ap->private_data; 832 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 833 void __iomem *hcr_base = host_priv->hcr_base; 834 int pmp = sata_srst_pmp(link); 835 u32 temp; 836 struct ata_taskfile tf; 837 u8 *cfis; 838 u32 Serror; 839 840 DPRINTK("in xx_softreset\n"); 841 842 if (ata_link_offline(link)) { 843 DPRINTK("PHY reports no device\n"); 844 *class = ATA_DEV_NONE; 845 return 0; 846 } 847 848 /* 849 * Send a device reset (SRST) explicitly on command slot #0 850 * Check : will the command queue (reg) be cleared during offlining ?? 851 * Also we will be online only if Phy commn. has been established 852 * and device presence has been detected, therefore if we have 853 * reached here, we can send a command to the target device 854 */ 855 856 DPRINTK("Sending SRST/device reset\n"); 857 858 ata_tf_init(link->device, &tf); 859 cfis = (u8 *) &pp->cmdentry->cfis; 860 861 /* device reset/SRST is a control register update FIS, uses tag0 */ 862 sata_fsl_setup_cmd_hdr_entry(pp, 0, 863 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 864 865 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 866 ata_tf_to_fis(&tf, pmp, 0, cfis); 867 868 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 869 cfis[0], cfis[1], cfis[2], cfis[3]); 870 871 /* 872 * Queue SRST command to the controller/device, ensure that no 873 * other commands are active on the controller/device 874 */ 875 876 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 877 ioread32(CQ + hcr_base), 878 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 879 880 iowrite32(0xFFFF, CC + hcr_base); 881 if (pmp != SATA_PMP_CTRL_PORT) 882 iowrite32(pmp, CQPMP + hcr_base); 883 iowrite32(1, CQ + hcr_base); 884 885 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); 886 if (temp & 0x1) { 887 ata_port_warn(ap, "ATA_SRST issue failed\n"); 888 889 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 890 ioread32(CQ + hcr_base), 891 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 892 893 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 894 895 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 896 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 897 DPRINTK("Serror = 0x%x\n", Serror); 898 goto err; 899 } 900 901 ata_msleep(ap, 1); 902 903 /* 904 * SATA device enters reset state after receiving a Control register 905 * FIS with SRST bit asserted and it awaits another H2D Control reg. 906 * FIS with SRST bit cleared, then the device does internal diags & 907 * initialization, followed by indicating it's initialization status 908 * using ATA signature D2H register FIS to the host controller. 909 */ 910 911 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 912 0, 0, 5); 913 914 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 915 ata_tf_to_fis(&tf, pmp, 0, cfis); 916 917 if (pmp != SATA_PMP_CTRL_PORT) 918 iowrite32(pmp, CQPMP + hcr_base); 919 iowrite32(1, CQ + hcr_base); 920 ata_msleep(ap, 150); /* ?? */ 921 922 /* 923 * The above command would have signalled an interrupt on command 924 * complete, which needs special handling, by clearing the Nth 925 * command bit of the CCreg 926 */ 927 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 928 929 DPRINTK("SATA FSL : Now checking device signature\n"); 930 931 *class = ATA_DEV_NONE; 932 933 /* Verify if SStatus indicates device presence */ 934 if (ata_link_online(link)) { 935 /* 936 * if we are here, device presence has been detected, 937 * 1st D2H FIS would have been received, but sfis in 938 * command desc. is not updated, but signature register 939 * would have been updated 940 */ 941 942 *class = sata_fsl_dev_classify(ap); 943 944 DPRINTK("class = %d\n", *class); 945 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 946 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 947 } 948 949 return 0; 950 951 err: 952 return -EIO; 953 } 954 955 static void sata_fsl_error_handler(struct ata_port *ap) 956 { 957 958 DPRINTK("in xx_error_handler\n"); 959 sata_pmp_error_handler(ap); 960 961 } 962 963 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 964 { 965 if (qc->flags & ATA_QCFLAG_FAILED) 966 qc->err_mask |= AC_ERR_OTHER; 967 968 if (qc->err_mask) { 969 /* make DMA engine forget about the failed command */ 970 971 } 972 } 973 974 static void sata_fsl_error_intr(struct ata_port *ap) 975 { 976 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 977 void __iomem *hcr_base = host_priv->hcr_base; 978 u32 hstatus, dereg=0, cereg = 0, SError = 0; 979 unsigned int err_mask = 0, action = 0; 980 int freeze = 0, abort=0; 981 struct ata_link *link = NULL; 982 struct ata_queued_cmd *qc = NULL; 983 struct ata_eh_info *ehi; 984 985 hstatus = ioread32(hcr_base + HSTATUS); 986 cereg = ioread32(hcr_base + CE); 987 988 /* first, analyze and record host port events */ 989 link = &ap->link; 990 ehi = &link->eh_info; 991 ata_ehi_clear_desc(ehi); 992 993 /* 994 * Handle & Clear SError 995 */ 996 997 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 998 if (unlikely(SError & 0xFFFF0000)) 999 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 1000 1001 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 1002 hstatus, cereg, ioread32(hcr_base + DE), SError); 1003 1004 /* handle fatal errors */ 1005 if (hstatus & FATAL_ERROR_DECODE) { 1006 ehi->err_mask |= AC_ERR_ATA_BUS; 1007 ehi->action |= ATA_EH_SOFTRESET; 1008 1009 freeze = 1; 1010 } 1011 1012 /* Handle SDB FIS receive & notify update */ 1013 if (hstatus & INT_ON_SNOTIFY_UPDATE) 1014 sata_async_notification(ap); 1015 1016 /* Handle PHYRDY change notification */ 1017 if (hstatus & INT_ON_PHYRDY_CHG) { 1018 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1019 1020 /* Setup a soft-reset EH action */ 1021 ata_ehi_hotplugged(ehi); 1022 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1023 freeze = 1; 1024 } 1025 1026 /* handle single device errors */ 1027 if (cereg) { 1028 /* 1029 * clear the command error, also clears queue to the device 1030 * in error, and we can (re)issue commands to this device. 1031 * When a device is in error all commands queued into the 1032 * host controller and at the device are considered aborted 1033 * and the queue for that device is stopped. Now, after 1034 * clearing the device error, we can issue commands to the 1035 * device to interrogate it to find the source of the error. 1036 */ 1037 abort = 1; 1038 1039 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 1040 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1041 1042 /* find out the offending link and qc */ 1043 if (ap->nr_pmp_links) { 1044 unsigned int dev_num; 1045 1046 dereg = ioread32(hcr_base + DE); 1047 iowrite32(dereg, hcr_base + DE); 1048 iowrite32(cereg, hcr_base + CE); 1049 1050 dev_num = ffs(dereg) - 1; 1051 if (dev_num < ap->nr_pmp_links && dereg != 0) { 1052 link = &ap->pmp_link[dev_num]; 1053 ehi = &link->eh_info; 1054 qc = ata_qc_from_tag(ap, link->active_tag); 1055 /* 1056 * We should consider this as non fatal error, 1057 * and TF must be updated as done below. 1058 */ 1059 1060 err_mask |= AC_ERR_DEV; 1061 1062 } else { 1063 err_mask |= AC_ERR_HSM; 1064 action |= ATA_EH_HARDRESET; 1065 freeze = 1; 1066 } 1067 } else { 1068 dereg = ioread32(hcr_base + DE); 1069 iowrite32(dereg, hcr_base + DE); 1070 iowrite32(cereg, hcr_base + CE); 1071 1072 qc = ata_qc_from_tag(ap, link->active_tag); 1073 /* 1074 * We should consider this as non fatal error, 1075 * and TF must be updated as done below. 1076 */ 1077 err_mask |= AC_ERR_DEV; 1078 } 1079 } 1080 1081 /* record error info */ 1082 if (qc) 1083 qc->err_mask |= err_mask; 1084 else 1085 ehi->err_mask |= err_mask; 1086 1087 ehi->action |= action; 1088 1089 /* freeze or abort */ 1090 if (freeze) 1091 ata_port_freeze(ap); 1092 else if (abort) { 1093 if (qc) 1094 ata_link_abort(qc->dev->link); 1095 else 1096 ata_port_abort(ap); 1097 } 1098 } 1099 1100 static void sata_fsl_host_intr(struct ata_port *ap) 1101 { 1102 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1103 void __iomem *hcr_base = host_priv->hcr_base; 1104 u32 hstatus, done_mask = 0; 1105 struct ata_queued_cmd *qc; 1106 u32 SError; 1107 1108 hstatus = ioread32(hcr_base + HSTATUS); 1109 1110 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1111 1112 if (unlikely(SError & 0xFFFF0000)) { 1113 DPRINTK("serror @host_intr : 0x%x\n", SError); 1114 sata_fsl_error_intr(ap); 1115 } 1116 1117 if (unlikely(hstatus & INT_ON_ERROR)) { 1118 DPRINTK("error interrupt!!\n"); 1119 sata_fsl_error_intr(ap); 1120 return; 1121 } 1122 1123 /* Read command completed register */ 1124 done_mask = ioread32(hcr_base + CC); 1125 1126 VPRINTK("Status of all queues :\n"); 1127 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", 1128 done_mask, 1129 ioread32(hcr_base + CA), 1130 ioread32(hcr_base + CE), 1131 ioread32(hcr_base + CQ), 1132 ap->qc_active); 1133 1134 if (done_mask & ap->qc_active) { 1135 int i; 1136 /* clear CC bit, this will also complete the interrupt */ 1137 iowrite32(done_mask, hcr_base + CC); 1138 1139 DPRINTK("Status of all queues :\n"); 1140 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1141 done_mask, ioread32(hcr_base + CA), 1142 ioread32(hcr_base + CE)); 1143 1144 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1145 if (done_mask & (1 << i)) 1146 DPRINTK 1147 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1148 i, ioread32(hcr_base + CC), 1149 ioread32(hcr_base + CA)); 1150 } 1151 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); 1152 return; 1153 1154 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { 1155 iowrite32(1, hcr_base + CC); 1156 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1157 1158 DPRINTK("completing non-ncq cmd, CC=0x%x\n", 1159 ioread32(hcr_base + CC)); 1160 1161 if (qc) { 1162 ata_qc_complete(qc); 1163 } 1164 } else { 1165 /* Spurious Interrupt!! */ 1166 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1167 ioread32(hcr_base + CC)); 1168 iowrite32(done_mask, hcr_base + CC); 1169 return; 1170 } 1171 } 1172 1173 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1174 { 1175 struct ata_host *host = dev_instance; 1176 struct sata_fsl_host_priv *host_priv = host->private_data; 1177 void __iomem *hcr_base = host_priv->hcr_base; 1178 u32 interrupt_enables; 1179 unsigned handled = 0; 1180 struct ata_port *ap; 1181 1182 /* ack. any pending IRQs for this controller/port */ 1183 interrupt_enables = ioread32(hcr_base + HSTATUS); 1184 interrupt_enables &= 0x3F; 1185 1186 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1187 1188 if (!interrupt_enables) 1189 return IRQ_NONE; 1190 1191 spin_lock(&host->lock); 1192 1193 /* Assuming one port per host controller */ 1194 1195 ap = host->ports[0]; 1196 if (ap) { 1197 sata_fsl_host_intr(ap); 1198 } else { 1199 dev_warn(host->dev, "interrupt on disabled port 0\n"); 1200 } 1201 1202 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1203 handled = 1; 1204 1205 spin_unlock(&host->lock); 1206 1207 return IRQ_RETVAL(handled); 1208 } 1209 1210 /* 1211 * Multiple ports are represented by multiple SATA controllers with 1212 * one port per controller 1213 */ 1214 static int sata_fsl_init_controller(struct ata_host *host) 1215 { 1216 struct sata_fsl_host_priv *host_priv = host->private_data; 1217 void __iomem *hcr_base = host_priv->hcr_base; 1218 u32 temp; 1219 1220 /* 1221 * NOTE : We cannot bring the controller online before setting 1222 * the CHBA, hence main controller initialization is done as 1223 * part of the port_start() callback 1224 */ 1225 1226 /* ack. any pending IRQs for this controller/port */ 1227 temp = ioread32(hcr_base + HSTATUS); 1228 if (temp & 0x3F) 1229 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1230 1231 /* Keep interrupts disabled on the controller */ 1232 temp = ioread32(hcr_base + HCONTROL); 1233 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1234 1235 /* Disable interrupt coalescing control(icc), for the moment */ 1236 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1237 iowrite32(0x01000000, hcr_base + ICC); 1238 1239 /* clear error registers, SError is cleared by libATA */ 1240 iowrite32(0x00000FFFF, hcr_base + CE); 1241 iowrite32(0x00000FFFF, hcr_base + DE); 1242 1243 /* 1244 * host controller will be brought on-line, during xx_port_start() 1245 * callback, that should also initiate the OOB, COMINIT sequence 1246 */ 1247 1248 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1249 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1250 1251 return 0; 1252 } 1253 1254 /* 1255 * scsi mid-layer and libata interface structures 1256 */ 1257 static struct scsi_host_template sata_fsl_sht = { 1258 ATA_NCQ_SHT("sata_fsl"), 1259 .can_queue = SATA_FSL_QUEUE_DEPTH, 1260 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1261 .dma_boundary = ATA_DMA_BOUNDARY, 1262 }; 1263 1264 static struct ata_port_operations sata_fsl_ops = { 1265 .inherits = &sata_pmp_port_ops, 1266 1267 .qc_defer = ata_std_qc_defer, 1268 .qc_prep = sata_fsl_qc_prep, 1269 .qc_issue = sata_fsl_qc_issue, 1270 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1271 1272 .scr_read = sata_fsl_scr_read, 1273 .scr_write = sata_fsl_scr_write, 1274 1275 .freeze = sata_fsl_freeze, 1276 .thaw = sata_fsl_thaw, 1277 .softreset = sata_fsl_softreset, 1278 .hardreset = sata_fsl_hardreset, 1279 .pmp_softreset = sata_fsl_softreset, 1280 .error_handler = sata_fsl_error_handler, 1281 .post_internal_cmd = sata_fsl_post_internal_cmd, 1282 1283 .port_start = sata_fsl_port_start, 1284 .port_stop = sata_fsl_port_stop, 1285 1286 .pmp_attach = sata_fsl_pmp_attach, 1287 .pmp_detach = sata_fsl_pmp_detach, 1288 }; 1289 1290 static const struct ata_port_info sata_fsl_port_info[] = { 1291 { 1292 .flags = SATA_FSL_HOST_FLAGS, 1293 .pio_mask = ATA_PIO4, 1294 .udma_mask = ATA_UDMA6, 1295 .port_ops = &sata_fsl_ops, 1296 }, 1297 }; 1298 1299 static int sata_fsl_probe(struct platform_device *ofdev) 1300 { 1301 int retval = -ENXIO; 1302 void __iomem *hcr_base = NULL; 1303 void __iomem *ssr_base = NULL; 1304 void __iomem *csr_base = NULL; 1305 struct sata_fsl_host_priv *host_priv = NULL; 1306 int irq; 1307 struct ata_host *host; 1308 u32 temp; 1309 1310 struct ata_port_info pi = sata_fsl_port_info[0]; 1311 const struct ata_port_info *ppi[] = { &pi, NULL }; 1312 1313 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n"); 1314 1315 hcr_base = of_iomap(ofdev->dev.of_node, 0); 1316 if (!hcr_base) 1317 goto error_exit_with_cleanup; 1318 1319 ssr_base = hcr_base + 0x100; 1320 csr_base = hcr_base + 0x140; 1321 1322 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { 1323 temp = ioread32(csr_base + TRANSCFG); 1324 temp = temp & 0xffffffe0; 1325 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); 1326 } 1327 1328 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1329 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1330 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1331 1332 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1333 if (!host_priv) 1334 goto error_exit_with_cleanup; 1335 1336 host_priv->hcr_base = hcr_base; 1337 host_priv->ssr_base = ssr_base; 1338 host_priv->csr_base = csr_base; 1339 1340 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1341 if (irq < 0) { 1342 dev_err(&ofdev->dev, "invalid irq from platform\n"); 1343 goto error_exit_with_cleanup; 1344 } 1345 host_priv->irq = irq; 1346 1347 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) 1348 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; 1349 else 1350 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; 1351 1352 /* allocate host structure */ 1353 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1354 1355 /* host->iomap is not used currently */ 1356 host->private_data = host_priv; 1357 1358 /* initialize host controller */ 1359 sata_fsl_init_controller(host); 1360 1361 /* 1362 * Now, register with libATA core, this will also initiate the 1363 * device discovery process, invoking our port_start() handler & 1364 * error_handler() to execute a dummy Softreset EH session 1365 */ 1366 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1367 &sata_fsl_sht); 1368 1369 dev_set_drvdata(&ofdev->dev, host); 1370 1371 return 0; 1372 1373 error_exit_with_cleanup: 1374 1375 if (hcr_base) 1376 iounmap(hcr_base); 1377 if (host_priv) 1378 kfree(host_priv); 1379 1380 return retval; 1381 } 1382 1383 static int sata_fsl_remove(struct platform_device *ofdev) 1384 { 1385 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1386 struct sata_fsl_host_priv *host_priv = host->private_data; 1387 1388 ata_host_detach(host); 1389 1390 dev_set_drvdata(&ofdev->dev, NULL); 1391 1392 irq_dispose_mapping(host_priv->irq); 1393 iounmap(host_priv->hcr_base); 1394 kfree(host_priv); 1395 1396 return 0; 1397 } 1398 1399 #ifdef CONFIG_PM 1400 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) 1401 { 1402 struct ata_host *host = dev_get_drvdata(&op->dev); 1403 return ata_host_suspend(host, state); 1404 } 1405 1406 static int sata_fsl_resume(struct platform_device *op) 1407 { 1408 struct ata_host *host = dev_get_drvdata(&op->dev); 1409 struct sata_fsl_host_priv *host_priv = host->private_data; 1410 int ret; 1411 void __iomem *hcr_base = host_priv->hcr_base; 1412 struct ata_port *ap = host->ports[0]; 1413 struct sata_fsl_port_priv *pp = ap->private_data; 1414 1415 ret = sata_fsl_init_controller(host); 1416 if (ret) { 1417 dev_err(&op->dev, "Error initializing hardware\n"); 1418 return ret; 1419 } 1420 1421 /* Recovery the CHBA register in host controller cmd register set */ 1422 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 1423 1424 ata_host_resume(host); 1425 return 0; 1426 } 1427 #endif 1428 1429 static struct of_device_id fsl_sata_match[] = { 1430 { 1431 .compatible = "fsl,pq-sata", 1432 }, 1433 { 1434 .compatible = "fsl,pq-sata-v2", 1435 }, 1436 {}, 1437 }; 1438 1439 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1440 1441 static struct platform_driver fsl_sata_driver = { 1442 .driver = { 1443 .name = "fsl-sata", 1444 .owner = THIS_MODULE, 1445 .of_match_table = fsl_sata_match, 1446 }, 1447 .probe = sata_fsl_probe, 1448 .remove = sata_fsl_remove, 1449 #ifdef CONFIG_PM 1450 .suspend = sata_fsl_suspend, 1451 .resume = sata_fsl_resume, 1452 #endif 1453 }; 1454 1455 static int __init sata_fsl_init(void) 1456 { 1457 platform_driver_register(&fsl_sata_driver); 1458 return 0; 1459 } 1460 1461 static void __exit sata_fsl_exit(void) 1462 { 1463 platform_driver_unregister(&fsl_sata_driver); 1464 } 1465 1466 MODULE_LICENSE("GPL"); 1467 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1468 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1469 MODULE_VERSION("1.10"); 1470 1471 module_init(sata_fsl_init); 1472 module_exit(sata_fsl_exit); 1473