1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 23 #include <scsi/scsi_host.h> 24 #include <scsi/scsi_cmnd.h> 25 #include <linux/libata.h> 26 #include <asm/io.h> 27 #include <linux/of_platform.h> 28 29 static unsigned int intr_coalescing_count; 30 module_param(intr_coalescing_count, int, S_IRUGO); 31 MODULE_PARM_DESC(intr_coalescing_count, 32 "INT coalescing count threshold (1..31)"); 33 34 static unsigned int intr_coalescing_ticks; 35 module_param(intr_coalescing_ticks, int, S_IRUGO); 36 MODULE_PARM_DESC(intr_coalescing_ticks, 37 "INT coalescing timer threshold in AHB ticks"); 38 /* Controller information */ 39 enum { 40 SATA_FSL_QUEUE_DEPTH = 16, 41 SATA_FSL_MAX_PRD = 63, 42 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 43 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 44 45 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 46 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN), 47 48 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 49 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 50 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 51 52 /* 53 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 54 * chained indirect PRDEs up to a max count of 63. 55 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will 56 * be setup as an indirect descriptor, pointing to it's next 57 * (contiguous) PRDE. Though chained indirect PRDE arrays are 58 * supported,it will be more efficient to use a direct PRDT and 59 * a single chain/link to indirect PRDE array/PRDT. 60 */ 61 62 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 63 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 64 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 65 SATA_FSL_CMD_DESC_RSRVD = 16, 66 67 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 68 SATA_FSL_CMD_DESC_SFIS_SZ + 69 SATA_FSL_CMD_DESC_ACMD_SZ + 70 SATA_FSL_CMD_DESC_RSRVD + 71 SATA_FSL_MAX_PRD * 16), 72 73 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 74 (SATA_FSL_CMD_DESC_CFIS_SZ + 75 SATA_FSL_CMD_DESC_SFIS_SZ + 76 SATA_FSL_CMD_DESC_ACMD_SZ + 77 SATA_FSL_CMD_DESC_RSRVD), 78 79 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 80 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 81 SATA_FSL_CMD_DESC_AR_SZ), 82 83 /* 84 * MPC8315 has two SATA controllers, SATA1 & SATA2 85 * (one port per controller) 86 * MPC837x has 2/4 controllers, one port per controller 87 */ 88 89 SATA_FSL_MAX_PORTS = 1, 90 91 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 92 }; 93 94 /* 95 * Interrupt Coalescing Control Register bitdefs */ 96 enum { 97 ICC_MIN_INT_COUNT_THRESHOLD = 1, 98 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1), 99 ICC_MIN_INT_TICKS_THRESHOLD = 0, 100 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1), 101 ICC_SAFE_INT_TICKS = 1, 102 }; 103 104 /* 105 * Host Controller command register set - per port 106 */ 107 enum { 108 CQ = 0, 109 CA = 8, 110 CC = 0x10, 111 CE = 0x18, 112 DE = 0x20, 113 CHBA = 0x24, 114 HSTATUS = 0x28, 115 HCONTROL = 0x2C, 116 CQPMP = 0x30, 117 SIGNATURE = 0x34, 118 ICC = 0x38, 119 120 /* 121 * Host Status Register (HStatus) bitdefs 122 */ 123 ONLINE = (1 << 31), 124 GOING_OFFLINE = (1 << 30), 125 BIST_ERR = (1 << 29), 126 127 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 128 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 129 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 130 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 131 FATAL_ERR_DATA_OVERRUN = (1 << 12), 132 FATAL_ERR_CRC_ERR_TX = (1 << 11), 133 FATAL_ERR_CRC_ERR_RX = (1 << 10), 134 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 135 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 136 137 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 138 FATAL_ERR_PARITY_ERR_TX | 139 FATAL_ERR_PARITY_ERR_RX | 140 FATAL_ERR_DATA_UNDERRUN | 141 FATAL_ERR_DATA_OVERRUN | 142 FATAL_ERR_CRC_ERR_TX | 143 FATAL_ERR_CRC_ERR_RX | 144 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 145 146 INT_ON_FATAL_ERR = (1 << 5), 147 INT_ON_PHYRDY_CHG = (1 << 4), 148 149 INT_ON_SIGNATURE_UPDATE = (1 << 3), 150 INT_ON_SNOTIFY_UPDATE = (1 << 2), 151 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 152 INT_ON_CMD_COMPLETE = 1, 153 154 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | 155 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 156 157 /* 158 * Host Control Register (HControl) bitdefs 159 */ 160 HCONTROL_ONLINE_PHY_RST = (1 << 31), 161 HCONTROL_FORCE_OFFLINE = (1 << 30), 162 HCONTROL_LEGACY = (1 << 28), 163 HCONTROL_PARITY_PROT_MOD = (1 << 14), 164 HCONTROL_DPATH_PARITY = (1 << 12), 165 HCONTROL_SNOOP_ENABLE = (1 << 10), 166 HCONTROL_PMP_ATTACHED = (1 << 9), 167 HCONTROL_COPYOUT_STATFIS = (1 << 8), 168 IE_ON_FATAL_ERR = (1 << 5), 169 IE_ON_PHYRDY_CHG = (1 << 4), 170 IE_ON_SIGNATURE_UPDATE = (1 << 3), 171 IE_ON_SNOTIFY_UPDATE = (1 << 2), 172 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 173 IE_ON_CMD_COMPLETE = 1, 174 175 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 176 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | 177 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 178 179 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 180 DATA_SNOOP_ENABLE_V1 = (1 << 22), 181 DATA_SNOOP_ENABLE_V2 = (1 << 28), 182 }; 183 184 /* 185 * SATA Superset Registers 186 */ 187 enum { 188 SSTATUS = 0, 189 SERROR = 4, 190 SCONTROL = 8, 191 SNOTIFY = 0xC, 192 }; 193 194 /* 195 * Control Status Register Set 196 */ 197 enum { 198 TRANSCFG = 0, 199 TRANSSTATUS = 4, 200 LINKCFG = 8, 201 LINKCFG1 = 0xC, 202 LINKCFG2 = 0x10, 203 LINKSTATUS = 0x14, 204 LINKSTATUS1 = 0x18, 205 PHYCTRLCFG = 0x1C, 206 COMMANDSTAT = 0x20, 207 }; 208 209 /* TRANSCFG (transport-layer) configuration control */ 210 enum { 211 TRANSCFG_RX_WATER_MARK = (1 << 4), 212 }; 213 214 /* PHY (link-layer) configuration control */ 215 enum { 216 PHY_BIST_ENABLE = 0x01, 217 }; 218 219 /* 220 * Command Header Table entry, i.e, command slot 221 * 4 Dwords per command slot, command header size == 64 Dwords. 222 */ 223 struct cmdhdr_tbl_entry { 224 u32 cda; 225 u32 prde_fis_len; 226 u32 ttl; 227 u32 desc_info; 228 }; 229 230 /* 231 * Description information bitdefs 232 */ 233 enum { 234 CMD_DESC_RES = (1 << 11), 235 VENDOR_SPECIFIC_BIST = (1 << 10), 236 CMD_DESC_SNOOP_ENABLE = (1 << 9), 237 FPDMA_QUEUED_CMD = (1 << 8), 238 SRST_CMD = (1 << 7), 239 BIST = (1 << 6), 240 ATAPI_CMD = (1 << 5), 241 }; 242 243 /* 244 * Command Descriptor 245 */ 246 struct command_desc { 247 u8 cfis[8 * 4]; 248 u8 sfis[8 * 4]; 249 u8 acmd[4 * 4]; 250 u8 fill[4 * 4]; 251 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 252 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 253 }; 254 255 /* 256 * Physical region table descriptor(PRD) 257 */ 258 259 struct prde { 260 u32 dba; 261 u8 fill[2 * 4]; 262 u32 ddc_and_ext; 263 }; 264 265 /* 266 * ata_port private data 267 * This is our per-port instance data. 268 */ 269 struct sata_fsl_port_priv { 270 struct cmdhdr_tbl_entry *cmdslot; 271 dma_addr_t cmdslot_paddr; 272 struct command_desc *cmdentry; 273 dma_addr_t cmdentry_paddr; 274 }; 275 276 /* 277 * ata_port->host_set private data 278 */ 279 struct sata_fsl_host_priv { 280 void __iomem *hcr_base; 281 void __iomem *ssr_base; 282 void __iomem *csr_base; 283 int irq; 284 int data_snoop; 285 struct device_attribute intr_coalescing; 286 }; 287 288 static void fsl_sata_set_irq_coalescing(struct ata_host *host, 289 unsigned int count, unsigned int ticks) 290 { 291 struct sata_fsl_host_priv *host_priv = host->private_data; 292 void __iomem *hcr_base = host_priv->hcr_base; 293 294 if (count > ICC_MAX_INT_COUNT_THRESHOLD) 295 count = ICC_MAX_INT_COUNT_THRESHOLD; 296 else if (count < ICC_MIN_INT_COUNT_THRESHOLD) 297 count = ICC_MIN_INT_COUNT_THRESHOLD; 298 299 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD) 300 ticks = ICC_MAX_INT_TICKS_THRESHOLD; 301 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) && 302 (count > ICC_MIN_INT_COUNT_THRESHOLD)) 303 ticks = ICC_SAFE_INT_TICKS; 304 305 spin_lock(&host->lock); 306 iowrite32((count << 24 | ticks), hcr_base + ICC); 307 308 intr_coalescing_count = count; 309 intr_coalescing_ticks = ticks; 310 spin_unlock(&host->lock); 311 312 DPRINTK("intrrupt coalescing, count = 0x%x, ticks = %x\n", 313 intr_coalescing_count, intr_coalescing_ticks); 314 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n", 315 hcr_base, ioread32(hcr_base + ICC)); 316 } 317 318 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev, 319 struct device_attribute *attr, char *buf) 320 { 321 return sprintf(buf, "%d %d\n", 322 intr_coalescing_count, intr_coalescing_ticks); 323 } 324 325 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev, 326 struct device_attribute *attr, 327 const char *buf, size_t count) 328 { 329 unsigned int coalescing_count, coalescing_ticks; 330 331 if (sscanf(buf, "%d%d", 332 &coalescing_count, 333 &coalescing_ticks) != 2) { 334 printk(KERN_ERR "fsl-sata: wrong parameter format.\n"); 335 return -EINVAL; 336 } 337 338 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev), 339 coalescing_count, coalescing_ticks); 340 341 return strlen(buf); 342 } 343 344 static inline unsigned int sata_fsl_tag(unsigned int tag, 345 void __iomem *hcr_base) 346 { 347 /* We let libATA core do actual (queue) tag allocation */ 348 349 /* all non NCQ/queued commands should have tag#0 */ 350 if (ata_tag_internal(tag)) { 351 DPRINTK("mapping internal cmds to tag#0\n"); 352 return 0; 353 } 354 355 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 356 DPRINTK("tag %d invalid : out of range\n", tag); 357 return 0; 358 } 359 360 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 361 DPRINTK("tag %d invalid : in use!!\n", tag); 362 return 0; 363 } 364 365 return tag; 366 } 367 368 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 369 unsigned int tag, u32 desc_info, 370 u32 data_xfer_len, u8 num_prde, 371 u8 fis_len) 372 { 373 dma_addr_t cmd_descriptor_address; 374 375 cmd_descriptor_address = pp->cmdentry_paddr + 376 tag * SATA_FSL_CMD_DESC_SIZE; 377 378 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 379 380 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 381 pp->cmdslot[tag].prde_fis_len = 382 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 383 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 384 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 385 386 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 387 pp->cmdslot[tag].cda, 388 pp->cmdslot[tag].prde_fis_len, 389 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 390 391 } 392 393 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 394 u32 *ttl, dma_addr_t cmd_desc_paddr, 395 int data_snoop) 396 { 397 struct scatterlist *sg; 398 unsigned int num_prde = 0; 399 u32 ttl_dwords = 0; 400 401 /* 402 * NOTE : direct & indirect prdt's are contiguously allocated 403 */ 404 struct prde *prd = (struct prde *)&((struct command_desc *) 405 cmd_desc)->prdt; 406 407 struct prde *prd_ptr_to_indirect_ext = NULL; 408 unsigned indirect_ext_segment_sz = 0; 409 dma_addr_t indirect_ext_segment_paddr; 410 unsigned int si; 411 412 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 413 414 indirect_ext_segment_paddr = cmd_desc_paddr + 415 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 416 417 for_each_sg(qc->sg, sg, qc->n_elem, si) { 418 dma_addr_t sg_addr = sg_dma_address(sg); 419 u32 sg_len = sg_dma_len(sg); 420 421 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", 422 (unsigned long long)sg_addr, sg_len); 423 424 /* warn if each s/g element is not dword aligned */ 425 if (unlikely(sg_addr & 0x03)) 426 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n", 427 (unsigned long long)sg_addr); 428 if (unlikely(sg_len & 0x03)) 429 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n", 430 sg_len); 431 432 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 433 sg_next(sg) != NULL) { 434 VPRINTK("setting indirect prde\n"); 435 prd_ptr_to_indirect_ext = prd; 436 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 437 indirect_ext_segment_sz = 0; 438 ++prd; 439 ++num_prde; 440 } 441 442 ttl_dwords += sg_len; 443 prd->dba = cpu_to_le32(sg_addr); 444 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); 445 446 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 447 ttl_dwords, prd->dba, prd->ddc_and_ext); 448 449 ++num_prde; 450 ++prd; 451 if (prd_ptr_to_indirect_ext) 452 indirect_ext_segment_sz += sg_len; 453 } 454 455 if (prd_ptr_to_indirect_ext) { 456 /* set indirect extension flag along with indirect ext. size */ 457 prd_ptr_to_indirect_ext->ddc_and_ext = 458 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 459 data_snoop | 460 (indirect_ext_segment_sz & ~0x03))); 461 } 462 463 *ttl = ttl_dwords; 464 return num_prde; 465 } 466 467 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 468 { 469 struct ata_port *ap = qc->ap; 470 struct sata_fsl_port_priv *pp = ap->private_data; 471 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 472 void __iomem *hcr_base = host_priv->hcr_base; 473 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 474 struct command_desc *cd; 475 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 476 u32 num_prde = 0; 477 u32 ttl_dwords = 0; 478 dma_addr_t cd_paddr; 479 480 cd = (struct command_desc *)pp->cmdentry + tag; 481 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 482 483 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 484 485 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 486 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 487 488 if (qc->tf.protocol == ATA_PROT_NCQ) { 489 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 490 cd->cfis[3], cd->cfis[11]); 491 } 492 493 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 494 if (ata_is_atapi(qc->tf.protocol)) { 495 desc_info |= ATAPI_CMD; 496 memset((void *)&cd->acmd, 0, 32); 497 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 498 } 499 500 if (qc->flags & ATA_QCFLAG_DMAMAP) 501 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 502 &ttl_dwords, cd_paddr, 503 host_priv->data_snoop); 504 505 if (qc->tf.protocol == ATA_PROT_NCQ) 506 desc_info |= FPDMA_QUEUED_CMD; 507 508 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 509 num_prde, 5); 510 511 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 512 desc_info, ttl_dwords, num_prde); 513 } 514 515 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 516 { 517 struct ata_port *ap = qc->ap; 518 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 519 void __iomem *hcr_base = host_priv->hcr_base; 520 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 521 522 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 523 ioread32(CQ + hcr_base), 524 ioread32(CA + hcr_base), 525 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 526 527 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 528 529 /* Simply queue command to the controller/device */ 530 iowrite32(1 << tag, CQ + hcr_base); 531 532 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 533 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 534 535 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 536 ioread32(CE + hcr_base), 537 ioread32(DE + hcr_base), 538 ioread32(CC + hcr_base), 539 ioread32(COMMANDSTAT + host_priv->csr_base)); 540 541 return 0; 542 } 543 544 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 545 { 546 struct sata_fsl_port_priv *pp = qc->ap->private_data; 547 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 548 void __iomem *hcr_base = host_priv->hcr_base; 549 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 550 struct command_desc *cd; 551 552 cd = pp->cmdentry + tag; 553 554 ata_tf_from_fis(cd->sfis, &qc->result_tf); 555 return true; 556 } 557 558 static int sata_fsl_scr_write(struct ata_link *link, 559 unsigned int sc_reg_in, u32 val) 560 { 561 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 562 void __iomem *ssr_base = host_priv->ssr_base; 563 unsigned int sc_reg; 564 565 switch (sc_reg_in) { 566 case SCR_STATUS: 567 case SCR_ERROR: 568 case SCR_CONTROL: 569 case SCR_ACTIVE: 570 sc_reg = sc_reg_in; 571 break; 572 default: 573 return -EINVAL; 574 } 575 576 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 577 578 iowrite32(val, ssr_base + (sc_reg * 4)); 579 return 0; 580 } 581 582 static int sata_fsl_scr_read(struct ata_link *link, 583 unsigned int sc_reg_in, u32 *val) 584 { 585 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 586 void __iomem *ssr_base = host_priv->ssr_base; 587 unsigned int sc_reg; 588 589 switch (sc_reg_in) { 590 case SCR_STATUS: 591 case SCR_ERROR: 592 case SCR_CONTROL: 593 case SCR_ACTIVE: 594 sc_reg = sc_reg_in; 595 break; 596 default: 597 return -EINVAL; 598 } 599 600 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 601 602 *val = ioread32(ssr_base + (sc_reg * 4)); 603 return 0; 604 } 605 606 static void sata_fsl_freeze(struct ata_port *ap) 607 { 608 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 609 void __iomem *hcr_base = host_priv->hcr_base; 610 u32 temp; 611 612 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 613 ioread32(CQ + hcr_base), 614 ioread32(CA + hcr_base), 615 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 616 VPRINTK("CmdStat = 0x%x\n", 617 ioread32(host_priv->csr_base + COMMANDSTAT)); 618 619 /* disable interrupts on the controller/port */ 620 temp = ioread32(hcr_base + HCONTROL); 621 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 622 623 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 624 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 625 } 626 627 static void sata_fsl_thaw(struct ata_port *ap) 628 { 629 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 630 void __iomem *hcr_base = host_priv->hcr_base; 631 u32 temp; 632 633 /* ack. any pending IRQs for this controller/port */ 634 temp = ioread32(hcr_base + HSTATUS); 635 636 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 637 638 if (temp & 0x3F) 639 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 640 641 /* enable interrupts on the controller/port */ 642 temp = ioread32(hcr_base + HCONTROL); 643 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 644 645 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 646 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 647 } 648 649 static void sata_fsl_pmp_attach(struct ata_port *ap) 650 { 651 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 652 void __iomem *hcr_base = host_priv->hcr_base; 653 u32 temp; 654 655 temp = ioread32(hcr_base + HCONTROL); 656 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 657 } 658 659 static void sata_fsl_pmp_detach(struct ata_port *ap) 660 { 661 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 662 void __iomem *hcr_base = host_priv->hcr_base; 663 u32 temp; 664 665 temp = ioread32(hcr_base + HCONTROL); 666 temp &= ~HCONTROL_PMP_ATTACHED; 667 iowrite32(temp, hcr_base + HCONTROL); 668 669 /* enable interrupts on the controller/port */ 670 temp = ioread32(hcr_base + HCONTROL); 671 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 672 673 } 674 675 static int sata_fsl_port_start(struct ata_port *ap) 676 { 677 struct device *dev = ap->host->dev; 678 struct sata_fsl_port_priv *pp; 679 void *mem; 680 dma_addr_t mem_dma; 681 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 682 void __iomem *hcr_base = host_priv->hcr_base; 683 u32 temp; 684 685 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 686 if (!pp) 687 return -ENOMEM; 688 689 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 690 GFP_KERNEL); 691 if (!mem) { 692 kfree(pp); 693 return -ENOMEM; 694 } 695 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 696 697 pp->cmdslot = mem; 698 pp->cmdslot_paddr = mem_dma; 699 700 mem += SATA_FSL_CMD_SLOT_SIZE; 701 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 702 703 pp->cmdentry = mem; 704 pp->cmdentry_paddr = mem_dma; 705 706 ap->private_data = pp; 707 708 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 709 pp->cmdslot_paddr, pp->cmdentry_paddr); 710 711 /* Now, update the CHBA register in host controller cmd register set */ 712 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 713 714 /* 715 * Now, we can bring the controller on-line & also initiate 716 * the COMINIT sequence, we simply return here and the boot-probing 717 * & device discovery process is re-initiated by libATA using a 718 * Softreset EH (dummy) session. Hence, boot probing and device 719 * discovey will be part of sata_fsl_softreset() callback. 720 */ 721 722 temp = ioread32(hcr_base + HCONTROL); 723 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 724 725 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 726 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 727 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 728 729 #ifdef CONFIG_MPC8315_DS 730 /* 731 * Workaround for 8315DS board 3gbps link-up issue, 732 * currently limit SATA port to GEN1 speed 733 */ 734 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 735 temp &= ~(0xF << 4); 736 temp |= (0x1 << 4); 737 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp); 738 739 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 740 dev_warn(dev, "scr_control, speed limited to %x\n", temp); 741 #endif 742 743 return 0; 744 } 745 746 static void sata_fsl_port_stop(struct ata_port *ap) 747 { 748 struct device *dev = ap->host->dev; 749 struct sata_fsl_port_priv *pp = ap->private_data; 750 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 751 void __iomem *hcr_base = host_priv->hcr_base; 752 u32 temp; 753 754 /* 755 * Force host controller to go off-line, aborting current operations 756 */ 757 temp = ioread32(hcr_base + HCONTROL); 758 temp &= ~HCONTROL_ONLINE_PHY_RST; 759 temp |= HCONTROL_FORCE_OFFLINE; 760 iowrite32(temp, hcr_base + HCONTROL); 761 762 /* Poll for controller to go offline - should happen immediately */ 763 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 764 765 ap->private_data = NULL; 766 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 767 pp->cmdslot, pp->cmdslot_paddr); 768 769 kfree(pp); 770 } 771 772 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 773 { 774 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 775 void __iomem *hcr_base = host_priv->hcr_base; 776 struct ata_taskfile tf; 777 u32 temp; 778 779 temp = ioread32(hcr_base + SIGNATURE); 780 781 VPRINTK("raw sig = 0x%x\n", temp); 782 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 783 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 784 785 tf.lbah = (temp >> 24) & 0xff; 786 tf.lbam = (temp >> 16) & 0xff; 787 tf.lbal = (temp >> 8) & 0xff; 788 tf.nsect = temp & 0xff; 789 790 return ata_dev_classify(&tf); 791 } 792 793 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, 794 unsigned long deadline) 795 { 796 struct ata_port *ap = link->ap; 797 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 798 void __iomem *hcr_base = host_priv->hcr_base; 799 u32 temp; 800 int i = 0; 801 unsigned long start_jiffies; 802 803 DPRINTK("in xx_hardreset\n"); 804 805 try_offline_again: 806 /* 807 * Force host controller to go off-line, aborting current operations 808 */ 809 temp = ioread32(hcr_base + HCONTROL); 810 temp &= ~HCONTROL_ONLINE_PHY_RST; 811 iowrite32(temp, hcr_base + HCONTROL); 812 813 /* Poll for controller to go offline */ 814 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 815 1, 500); 816 817 if (temp & ONLINE) { 818 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i); 819 820 /* 821 * Try to offline controller atleast twice 822 */ 823 i++; 824 if (i == 2) 825 goto err; 826 else 827 goto try_offline_again; 828 } 829 830 DPRINTK("hardreset, controller off-lined\n"); 831 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 832 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 833 834 /* 835 * PHY reset should remain asserted for atleast 1ms 836 */ 837 ata_msleep(ap, 1); 838 839 /* 840 * Now, bring the host controller online again, this can take time 841 * as PHY reset and communication establishment, 1st D2H FIS and 842 * device signature update is done, on safe side assume 500ms 843 * NOTE : Host online status may be indicated immediately!! 844 */ 845 846 temp = ioread32(hcr_base + HCONTROL); 847 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 848 temp |= HCONTROL_PMP_ATTACHED; 849 iowrite32(temp, hcr_base + HCONTROL); 850 851 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); 852 853 if (!(temp & ONLINE)) { 854 ata_port_err(ap, "Hardreset failed, not on-lined\n"); 855 goto err; 856 } 857 858 DPRINTK("hardreset, controller off-lined & on-lined\n"); 859 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 860 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 861 862 /* 863 * First, wait for the PHYRDY change to occur before waiting for 864 * the signature, and also verify if SStatus indicates device 865 * presence 866 */ 867 868 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); 869 if ((!(temp & 0x10)) || ata_link_offline(link)) { 870 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n", 871 ioread32(hcr_base + HSTATUS)); 872 *class = ATA_DEV_NONE; 873 return 0; 874 } 875 876 /* 877 * Wait for the first D2H from device,i.e,signature update notification 878 */ 879 start_jiffies = jiffies; 880 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, 881 500, jiffies_to_msecs(deadline - start_jiffies)); 882 883 if ((temp & 0xFF) != 0x18) { 884 ata_port_warn(ap, "No Signature Update\n"); 885 *class = ATA_DEV_NONE; 886 goto do_followup_srst; 887 } else { 888 ata_port_info(ap, "Signature Update detected @ %d msecs\n", 889 jiffies_to_msecs(jiffies - start_jiffies)); 890 *class = sata_fsl_dev_classify(ap); 891 return 0; 892 } 893 894 do_followup_srst: 895 /* 896 * request libATA to perform follow-up softreset 897 */ 898 return -EAGAIN; 899 900 err: 901 return -EIO; 902 } 903 904 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 905 unsigned long deadline) 906 { 907 struct ata_port *ap = link->ap; 908 struct sata_fsl_port_priv *pp = ap->private_data; 909 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 910 void __iomem *hcr_base = host_priv->hcr_base; 911 int pmp = sata_srst_pmp(link); 912 u32 temp; 913 struct ata_taskfile tf; 914 u8 *cfis; 915 u32 Serror; 916 917 DPRINTK("in xx_softreset\n"); 918 919 if (ata_link_offline(link)) { 920 DPRINTK("PHY reports no device\n"); 921 *class = ATA_DEV_NONE; 922 return 0; 923 } 924 925 /* 926 * Send a device reset (SRST) explicitly on command slot #0 927 * Check : will the command queue (reg) be cleared during offlining ?? 928 * Also we will be online only if Phy commn. has been established 929 * and device presence has been detected, therefore if we have 930 * reached here, we can send a command to the target device 931 */ 932 933 DPRINTK("Sending SRST/device reset\n"); 934 935 ata_tf_init(link->device, &tf); 936 cfis = (u8 *) &pp->cmdentry->cfis; 937 938 /* device reset/SRST is a control register update FIS, uses tag0 */ 939 sata_fsl_setup_cmd_hdr_entry(pp, 0, 940 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 941 942 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 943 ata_tf_to_fis(&tf, pmp, 0, cfis); 944 945 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 946 cfis[0], cfis[1], cfis[2], cfis[3]); 947 948 /* 949 * Queue SRST command to the controller/device, ensure that no 950 * other commands are active on the controller/device 951 */ 952 953 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 954 ioread32(CQ + hcr_base), 955 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 956 957 iowrite32(0xFFFF, CC + hcr_base); 958 if (pmp != SATA_PMP_CTRL_PORT) 959 iowrite32(pmp, CQPMP + hcr_base); 960 iowrite32(1, CQ + hcr_base); 961 962 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); 963 if (temp & 0x1) { 964 ata_port_warn(ap, "ATA_SRST issue failed\n"); 965 966 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 967 ioread32(CQ + hcr_base), 968 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 969 970 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 971 972 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 973 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 974 DPRINTK("Serror = 0x%x\n", Serror); 975 goto err; 976 } 977 978 ata_msleep(ap, 1); 979 980 /* 981 * SATA device enters reset state after receiving a Control register 982 * FIS with SRST bit asserted and it awaits another H2D Control reg. 983 * FIS with SRST bit cleared, then the device does internal diags & 984 * initialization, followed by indicating it's initialization status 985 * using ATA signature D2H register FIS to the host controller. 986 */ 987 988 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 989 0, 0, 5); 990 991 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 992 ata_tf_to_fis(&tf, pmp, 0, cfis); 993 994 if (pmp != SATA_PMP_CTRL_PORT) 995 iowrite32(pmp, CQPMP + hcr_base); 996 iowrite32(1, CQ + hcr_base); 997 ata_msleep(ap, 150); /* ?? */ 998 999 /* 1000 * The above command would have signalled an interrupt on command 1001 * complete, which needs special handling, by clearing the Nth 1002 * command bit of the CCreg 1003 */ 1004 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 1005 1006 DPRINTK("SATA FSL : Now checking device signature\n"); 1007 1008 *class = ATA_DEV_NONE; 1009 1010 /* Verify if SStatus indicates device presence */ 1011 if (ata_link_online(link)) { 1012 /* 1013 * if we are here, device presence has been detected, 1014 * 1st D2H FIS would have been received, but sfis in 1015 * command desc. is not updated, but signature register 1016 * would have been updated 1017 */ 1018 1019 *class = sata_fsl_dev_classify(ap); 1020 1021 DPRINTK("class = %d\n", *class); 1022 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 1023 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 1024 } 1025 1026 return 0; 1027 1028 err: 1029 return -EIO; 1030 } 1031 1032 static void sata_fsl_error_handler(struct ata_port *ap) 1033 { 1034 1035 DPRINTK("in xx_error_handler\n"); 1036 sata_pmp_error_handler(ap); 1037 1038 } 1039 1040 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 1041 { 1042 if (qc->flags & ATA_QCFLAG_FAILED) 1043 qc->err_mask |= AC_ERR_OTHER; 1044 1045 if (qc->err_mask) { 1046 /* make DMA engine forget about the failed command */ 1047 1048 } 1049 } 1050 1051 static void sata_fsl_error_intr(struct ata_port *ap) 1052 { 1053 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1054 void __iomem *hcr_base = host_priv->hcr_base; 1055 u32 hstatus, dereg=0, cereg = 0, SError = 0; 1056 unsigned int err_mask = 0, action = 0; 1057 int freeze = 0, abort=0; 1058 struct ata_link *link = NULL; 1059 struct ata_queued_cmd *qc = NULL; 1060 struct ata_eh_info *ehi; 1061 1062 hstatus = ioread32(hcr_base + HSTATUS); 1063 cereg = ioread32(hcr_base + CE); 1064 1065 /* first, analyze and record host port events */ 1066 link = &ap->link; 1067 ehi = &link->eh_info; 1068 ata_ehi_clear_desc(ehi); 1069 1070 /* 1071 * Handle & Clear SError 1072 */ 1073 1074 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1075 if (unlikely(SError & 0xFFFF0000)) 1076 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 1077 1078 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 1079 hstatus, cereg, ioread32(hcr_base + DE), SError); 1080 1081 /* handle fatal errors */ 1082 if (hstatus & FATAL_ERROR_DECODE) { 1083 ehi->err_mask |= AC_ERR_ATA_BUS; 1084 ehi->action |= ATA_EH_SOFTRESET; 1085 1086 freeze = 1; 1087 } 1088 1089 /* Handle SDB FIS receive & notify update */ 1090 if (hstatus & INT_ON_SNOTIFY_UPDATE) 1091 sata_async_notification(ap); 1092 1093 /* Handle PHYRDY change notification */ 1094 if (hstatus & INT_ON_PHYRDY_CHG) { 1095 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1096 1097 /* Setup a soft-reset EH action */ 1098 ata_ehi_hotplugged(ehi); 1099 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1100 freeze = 1; 1101 } 1102 1103 /* handle single device errors */ 1104 if (cereg) { 1105 /* 1106 * clear the command error, also clears queue to the device 1107 * in error, and we can (re)issue commands to this device. 1108 * When a device is in error all commands queued into the 1109 * host controller and at the device are considered aborted 1110 * and the queue for that device is stopped. Now, after 1111 * clearing the device error, we can issue commands to the 1112 * device to interrogate it to find the source of the error. 1113 */ 1114 abort = 1; 1115 1116 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 1117 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1118 1119 /* find out the offending link and qc */ 1120 if (ap->nr_pmp_links) { 1121 unsigned int dev_num; 1122 1123 dereg = ioread32(hcr_base + DE); 1124 iowrite32(dereg, hcr_base + DE); 1125 iowrite32(cereg, hcr_base + CE); 1126 1127 dev_num = ffs(dereg) - 1; 1128 if (dev_num < ap->nr_pmp_links && dereg != 0) { 1129 link = &ap->pmp_link[dev_num]; 1130 ehi = &link->eh_info; 1131 qc = ata_qc_from_tag(ap, link->active_tag); 1132 /* 1133 * We should consider this as non fatal error, 1134 * and TF must be updated as done below. 1135 */ 1136 1137 err_mask |= AC_ERR_DEV; 1138 1139 } else { 1140 err_mask |= AC_ERR_HSM; 1141 action |= ATA_EH_HARDRESET; 1142 freeze = 1; 1143 } 1144 } else { 1145 dereg = ioread32(hcr_base + DE); 1146 iowrite32(dereg, hcr_base + DE); 1147 iowrite32(cereg, hcr_base + CE); 1148 1149 qc = ata_qc_from_tag(ap, link->active_tag); 1150 /* 1151 * We should consider this as non fatal error, 1152 * and TF must be updated as done below. 1153 */ 1154 err_mask |= AC_ERR_DEV; 1155 } 1156 } 1157 1158 /* record error info */ 1159 if (qc) 1160 qc->err_mask |= err_mask; 1161 else 1162 ehi->err_mask |= err_mask; 1163 1164 ehi->action |= action; 1165 1166 /* freeze or abort */ 1167 if (freeze) 1168 ata_port_freeze(ap); 1169 else if (abort) { 1170 if (qc) 1171 ata_link_abort(qc->dev->link); 1172 else 1173 ata_port_abort(ap); 1174 } 1175 } 1176 1177 static void sata_fsl_host_intr(struct ata_port *ap) 1178 { 1179 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1180 void __iomem *hcr_base = host_priv->hcr_base; 1181 u32 hstatus, done_mask = 0; 1182 struct ata_queued_cmd *qc; 1183 u32 SError; 1184 1185 hstatus = ioread32(hcr_base + HSTATUS); 1186 1187 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1188 1189 if (unlikely(SError & 0xFFFF0000)) { 1190 DPRINTK("serror @host_intr : 0x%x\n", SError); 1191 sata_fsl_error_intr(ap); 1192 } 1193 1194 if (unlikely(hstatus & INT_ON_ERROR)) { 1195 DPRINTK("error interrupt!!\n"); 1196 sata_fsl_error_intr(ap); 1197 return; 1198 } 1199 1200 /* Read command completed register */ 1201 done_mask = ioread32(hcr_base + CC); 1202 1203 VPRINTK("Status of all queues :\n"); 1204 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", 1205 done_mask, 1206 ioread32(hcr_base + CA), 1207 ioread32(hcr_base + CE), 1208 ioread32(hcr_base + CQ), 1209 ap->qc_active); 1210 1211 if (done_mask & ap->qc_active) { 1212 int i; 1213 /* clear CC bit, this will also complete the interrupt */ 1214 iowrite32(done_mask, hcr_base + CC); 1215 1216 DPRINTK("Status of all queues :\n"); 1217 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1218 done_mask, ioread32(hcr_base + CA), 1219 ioread32(hcr_base + CE)); 1220 1221 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1222 if (done_mask & (1 << i)) 1223 DPRINTK 1224 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1225 i, ioread32(hcr_base + CC), 1226 ioread32(hcr_base + CA)); 1227 } 1228 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); 1229 return; 1230 1231 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { 1232 iowrite32(1, hcr_base + CC); 1233 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1234 1235 DPRINTK("completing non-ncq cmd, CC=0x%x\n", 1236 ioread32(hcr_base + CC)); 1237 1238 if (qc) { 1239 ata_qc_complete(qc); 1240 } 1241 } else { 1242 /* Spurious Interrupt!! */ 1243 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1244 ioread32(hcr_base + CC)); 1245 iowrite32(done_mask, hcr_base + CC); 1246 return; 1247 } 1248 } 1249 1250 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1251 { 1252 struct ata_host *host = dev_instance; 1253 struct sata_fsl_host_priv *host_priv = host->private_data; 1254 void __iomem *hcr_base = host_priv->hcr_base; 1255 u32 interrupt_enables; 1256 unsigned handled = 0; 1257 struct ata_port *ap; 1258 1259 /* ack. any pending IRQs for this controller/port */ 1260 interrupt_enables = ioread32(hcr_base + HSTATUS); 1261 interrupt_enables &= 0x3F; 1262 1263 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1264 1265 if (!interrupt_enables) 1266 return IRQ_NONE; 1267 1268 spin_lock(&host->lock); 1269 1270 /* Assuming one port per host controller */ 1271 1272 ap = host->ports[0]; 1273 if (ap) { 1274 sata_fsl_host_intr(ap); 1275 } else { 1276 dev_warn(host->dev, "interrupt on disabled port 0\n"); 1277 } 1278 1279 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1280 handled = 1; 1281 1282 spin_unlock(&host->lock); 1283 1284 return IRQ_RETVAL(handled); 1285 } 1286 1287 /* 1288 * Multiple ports are represented by multiple SATA controllers with 1289 * one port per controller 1290 */ 1291 static int sata_fsl_init_controller(struct ata_host *host) 1292 { 1293 struct sata_fsl_host_priv *host_priv = host->private_data; 1294 void __iomem *hcr_base = host_priv->hcr_base; 1295 u32 temp; 1296 1297 /* 1298 * NOTE : We cannot bring the controller online before setting 1299 * the CHBA, hence main controller initialization is done as 1300 * part of the port_start() callback 1301 */ 1302 1303 /* sata controller to operate in enterprise mode */ 1304 temp = ioread32(hcr_base + HCONTROL); 1305 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); 1306 1307 /* ack. any pending IRQs for this controller/port */ 1308 temp = ioread32(hcr_base + HSTATUS); 1309 if (temp & 0x3F) 1310 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1311 1312 /* Keep interrupts disabled on the controller */ 1313 temp = ioread32(hcr_base + HCONTROL); 1314 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1315 1316 /* Disable interrupt coalescing control(icc), for the moment */ 1317 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1318 iowrite32(0x01000000, hcr_base + ICC); 1319 1320 /* clear error registers, SError is cleared by libATA */ 1321 iowrite32(0x00000FFFF, hcr_base + CE); 1322 iowrite32(0x00000FFFF, hcr_base + DE); 1323 1324 /* 1325 * reset the number of command complete bits which will cause the 1326 * interrupt to be signaled 1327 */ 1328 fsl_sata_set_irq_coalescing(host, intr_coalescing_count, 1329 intr_coalescing_ticks); 1330 1331 /* 1332 * host controller will be brought on-line, during xx_port_start() 1333 * callback, that should also initiate the OOB, COMINIT sequence 1334 */ 1335 1336 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1337 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1338 1339 return 0; 1340 } 1341 1342 /* 1343 * scsi mid-layer and libata interface structures 1344 */ 1345 static struct scsi_host_template sata_fsl_sht = { 1346 ATA_NCQ_SHT("sata_fsl"), 1347 .can_queue = SATA_FSL_QUEUE_DEPTH, 1348 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1349 .dma_boundary = ATA_DMA_BOUNDARY, 1350 }; 1351 1352 static struct ata_port_operations sata_fsl_ops = { 1353 .inherits = &sata_pmp_port_ops, 1354 1355 .qc_defer = ata_std_qc_defer, 1356 .qc_prep = sata_fsl_qc_prep, 1357 .qc_issue = sata_fsl_qc_issue, 1358 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1359 1360 .scr_read = sata_fsl_scr_read, 1361 .scr_write = sata_fsl_scr_write, 1362 1363 .freeze = sata_fsl_freeze, 1364 .thaw = sata_fsl_thaw, 1365 .softreset = sata_fsl_softreset, 1366 .hardreset = sata_fsl_hardreset, 1367 .pmp_softreset = sata_fsl_softreset, 1368 .error_handler = sata_fsl_error_handler, 1369 .post_internal_cmd = sata_fsl_post_internal_cmd, 1370 1371 .port_start = sata_fsl_port_start, 1372 .port_stop = sata_fsl_port_stop, 1373 1374 .pmp_attach = sata_fsl_pmp_attach, 1375 .pmp_detach = sata_fsl_pmp_detach, 1376 }; 1377 1378 static const struct ata_port_info sata_fsl_port_info[] = { 1379 { 1380 .flags = SATA_FSL_HOST_FLAGS, 1381 .pio_mask = ATA_PIO4, 1382 .udma_mask = ATA_UDMA6, 1383 .port_ops = &sata_fsl_ops, 1384 }, 1385 }; 1386 1387 static int sata_fsl_probe(struct platform_device *ofdev) 1388 { 1389 int retval = -ENXIO; 1390 void __iomem *hcr_base = NULL; 1391 void __iomem *ssr_base = NULL; 1392 void __iomem *csr_base = NULL; 1393 struct sata_fsl_host_priv *host_priv = NULL; 1394 int irq; 1395 struct ata_host *host = NULL; 1396 u32 temp; 1397 1398 struct ata_port_info pi = sata_fsl_port_info[0]; 1399 const struct ata_port_info *ppi[] = { &pi, NULL }; 1400 1401 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n"); 1402 1403 hcr_base = of_iomap(ofdev->dev.of_node, 0); 1404 if (!hcr_base) 1405 goto error_exit_with_cleanup; 1406 1407 ssr_base = hcr_base + 0x100; 1408 csr_base = hcr_base + 0x140; 1409 1410 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { 1411 temp = ioread32(csr_base + TRANSCFG); 1412 temp = temp & 0xffffffe0; 1413 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); 1414 } 1415 1416 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1417 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1418 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1419 1420 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1421 if (!host_priv) 1422 goto error_exit_with_cleanup; 1423 1424 host_priv->hcr_base = hcr_base; 1425 host_priv->ssr_base = ssr_base; 1426 host_priv->csr_base = csr_base; 1427 1428 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1429 if (irq < 0) { 1430 dev_err(&ofdev->dev, "invalid irq from platform\n"); 1431 goto error_exit_with_cleanup; 1432 } 1433 host_priv->irq = irq; 1434 1435 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) 1436 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; 1437 else 1438 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; 1439 1440 /* allocate host structure */ 1441 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1442 if (!host) { 1443 retval = -ENOMEM; 1444 goto error_exit_with_cleanup; 1445 } 1446 1447 /* host->iomap is not used currently */ 1448 host->private_data = host_priv; 1449 1450 /* initialize host controller */ 1451 sata_fsl_init_controller(host); 1452 1453 /* 1454 * Now, register with libATA core, this will also initiate the 1455 * device discovery process, invoking our port_start() handler & 1456 * error_handler() to execute a dummy Softreset EH session 1457 */ 1458 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1459 &sata_fsl_sht); 1460 1461 dev_set_drvdata(&ofdev->dev, host); 1462 1463 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show; 1464 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store; 1465 sysfs_attr_init(&host_priv->intr_coalescing.attr); 1466 host_priv->intr_coalescing.attr.name = "intr_coalescing"; 1467 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR; 1468 retval = device_create_file(host->dev, &host_priv->intr_coalescing); 1469 if (retval) 1470 goto error_exit_with_cleanup; 1471 1472 return 0; 1473 1474 error_exit_with_cleanup: 1475 1476 if (host) { 1477 dev_set_drvdata(&ofdev->dev, NULL); 1478 ata_host_detach(host); 1479 } 1480 1481 if (hcr_base) 1482 iounmap(hcr_base); 1483 if (host_priv) 1484 kfree(host_priv); 1485 1486 return retval; 1487 } 1488 1489 static int sata_fsl_remove(struct platform_device *ofdev) 1490 { 1491 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1492 struct sata_fsl_host_priv *host_priv = host->private_data; 1493 1494 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); 1495 1496 ata_host_detach(host); 1497 1498 dev_set_drvdata(&ofdev->dev, NULL); 1499 1500 irq_dispose_mapping(host_priv->irq); 1501 iounmap(host_priv->hcr_base); 1502 kfree(host_priv); 1503 1504 return 0; 1505 } 1506 1507 #ifdef CONFIG_PM 1508 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) 1509 { 1510 struct ata_host *host = dev_get_drvdata(&op->dev); 1511 return ata_host_suspend(host, state); 1512 } 1513 1514 static int sata_fsl_resume(struct platform_device *op) 1515 { 1516 struct ata_host *host = dev_get_drvdata(&op->dev); 1517 struct sata_fsl_host_priv *host_priv = host->private_data; 1518 int ret; 1519 void __iomem *hcr_base = host_priv->hcr_base; 1520 struct ata_port *ap = host->ports[0]; 1521 struct sata_fsl_port_priv *pp = ap->private_data; 1522 1523 ret = sata_fsl_init_controller(host); 1524 if (ret) { 1525 dev_err(&op->dev, "Error initializing hardware\n"); 1526 return ret; 1527 } 1528 1529 /* Recovery the CHBA register in host controller cmd register set */ 1530 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 1531 1532 iowrite32((ioread32(hcr_base + HCONTROL) 1533 | HCONTROL_ONLINE_PHY_RST 1534 | HCONTROL_SNOOP_ENABLE 1535 | HCONTROL_PMP_ATTACHED), 1536 hcr_base + HCONTROL); 1537 1538 ata_host_resume(host); 1539 return 0; 1540 } 1541 #endif 1542 1543 static struct of_device_id fsl_sata_match[] = { 1544 { 1545 .compatible = "fsl,pq-sata", 1546 }, 1547 { 1548 .compatible = "fsl,pq-sata-v2", 1549 }, 1550 {}, 1551 }; 1552 1553 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1554 1555 static struct platform_driver fsl_sata_driver = { 1556 .driver = { 1557 .name = "fsl-sata", 1558 .owner = THIS_MODULE, 1559 .of_match_table = fsl_sata_match, 1560 }, 1561 .probe = sata_fsl_probe, 1562 .remove = sata_fsl_remove, 1563 #ifdef CONFIG_PM 1564 .suspend = sata_fsl_suspend, 1565 .resume = sata_fsl_resume, 1566 #endif 1567 }; 1568 1569 module_platform_driver(fsl_sata_driver); 1570 1571 MODULE_LICENSE("GPL"); 1572 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1573 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1574 MODULE_VERSION("1.10"); 1575