1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 22 #include <scsi/scsi_host.h> 23 #include <scsi/scsi_cmnd.h> 24 #include <linux/libata.h> 25 #include <asm/io.h> 26 #include <linux/of_platform.h> 27 28 /* Controller information */ 29 enum { 30 SATA_FSL_QUEUE_DEPTH = 16, 31 SATA_FSL_MAX_PRD = 63, 32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 34 35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 37 ATA_FLAG_PMP | ATA_FLAG_NCQ), 38 39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 42 43 /* 44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 45 * chained indirect PRDEs upto a max count of 63. 46 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will 47 * be setup as an indirect descriptor, pointing to it's next 48 * (contigious) PRDE. Though chained indirect PRDE arrays are 49 * supported,it will be more efficient to use a direct PRDT and 50 * a single chain/link to indirect PRDE array/PRDT. 51 */ 52 53 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 54 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 55 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 56 SATA_FSL_CMD_DESC_RSRVD = 16, 57 58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 59 SATA_FSL_CMD_DESC_SFIS_SZ + 60 SATA_FSL_CMD_DESC_ACMD_SZ + 61 SATA_FSL_CMD_DESC_RSRVD + 62 SATA_FSL_MAX_PRD * 16), 63 64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 65 (SATA_FSL_CMD_DESC_CFIS_SZ + 66 SATA_FSL_CMD_DESC_SFIS_SZ + 67 SATA_FSL_CMD_DESC_ACMD_SZ + 68 SATA_FSL_CMD_DESC_RSRVD), 69 70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 72 SATA_FSL_CMD_DESC_AR_SZ), 73 74 /* 75 * MPC8315 has two SATA controllers, SATA1 & SATA2 76 * (one port per controller) 77 * MPC837x has 2/4 controllers, one port per controller 78 */ 79 80 SATA_FSL_MAX_PORTS = 1, 81 82 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 83 }; 84 85 /* 86 * Host Controller command register set - per port 87 */ 88 enum { 89 CQ = 0, 90 CA = 8, 91 CC = 0x10, 92 CE = 0x18, 93 DE = 0x20, 94 CHBA = 0x24, 95 HSTATUS = 0x28, 96 HCONTROL = 0x2C, 97 CQPMP = 0x30, 98 SIGNATURE = 0x34, 99 ICC = 0x38, 100 101 /* 102 * Host Status Register (HStatus) bitdefs 103 */ 104 ONLINE = (1 << 31), 105 GOING_OFFLINE = (1 << 30), 106 BIST_ERR = (1 << 29), 107 108 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 109 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 110 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 111 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 112 FATAL_ERR_DATA_OVERRUN = (1 << 12), 113 FATAL_ERR_CRC_ERR_TX = (1 << 11), 114 FATAL_ERR_CRC_ERR_RX = (1 << 10), 115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 117 118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 119 FATAL_ERR_PARITY_ERR_TX | 120 FATAL_ERR_PARITY_ERR_RX | 121 FATAL_ERR_DATA_UNDERRUN | 122 FATAL_ERR_DATA_OVERRUN | 123 FATAL_ERR_CRC_ERR_TX | 124 FATAL_ERR_CRC_ERR_RX | 125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 126 127 INT_ON_FATAL_ERR = (1 << 5), 128 INT_ON_PHYRDY_CHG = (1 << 4), 129 130 INT_ON_SIGNATURE_UPDATE = (1 << 3), 131 INT_ON_SNOTIFY_UPDATE = (1 << 2), 132 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 133 INT_ON_CMD_COMPLETE = 1, 134 135 INT_ON_ERROR = INT_ON_FATAL_ERR | 136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 137 138 /* 139 * Host Control Register (HControl) bitdefs 140 */ 141 HCONTROL_ONLINE_PHY_RST = (1 << 31), 142 HCONTROL_FORCE_OFFLINE = (1 << 30), 143 HCONTROL_PARITY_PROT_MOD = (1 << 14), 144 HCONTROL_DPATH_PARITY = (1 << 12), 145 HCONTROL_SNOOP_ENABLE = (1 << 10), 146 HCONTROL_PMP_ATTACHED = (1 << 9), 147 HCONTROL_COPYOUT_STATFIS = (1 << 8), 148 IE_ON_FATAL_ERR = (1 << 5), 149 IE_ON_PHYRDY_CHG = (1 << 4), 150 IE_ON_SIGNATURE_UPDATE = (1 << 3), 151 IE_ON_SNOTIFY_UPDATE = (1 << 2), 152 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 153 IE_ON_CMD_COMPLETE = 1, 154 155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 156 IE_ON_SIGNATURE_UPDATE | 157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 158 159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 160 DATA_SNOOP_ENABLE = (1 << 22), 161 }; 162 163 /* 164 * SATA Superset Registers 165 */ 166 enum { 167 SSTATUS = 0, 168 SERROR = 4, 169 SCONTROL = 8, 170 SNOTIFY = 0xC, 171 }; 172 173 /* 174 * Control Status Register Set 175 */ 176 enum { 177 TRANSCFG = 0, 178 TRANSSTATUS = 4, 179 LINKCFG = 8, 180 LINKCFG1 = 0xC, 181 LINKCFG2 = 0x10, 182 LINKSTATUS = 0x14, 183 LINKSTATUS1 = 0x18, 184 PHYCTRLCFG = 0x1C, 185 COMMANDSTAT = 0x20, 186 }; 187 188 /* PHY (link-layer) configuration control */ 189 enum { 190 PHY_BIST_ENABLE = 0x01, 191 }; 192 193 /* 194 * Command Header Table entry, i.e, command slot 195 * 4 Dwords per command slot, command header size == 64 Dwords. 196 */ 197 struct cmdhdr_tbl_entry { 198 u32 cda; 199 u32 prde_fis_len; 200 u32 ttl; 201 u32 desc_info; 202 }; 203 204 /* 205 * Description information bitdefs 206 */ 207 enum { 208 CMD_DESC_RES = (1 << 11), 209 VENDOR_SPECIFIC_BIST = (1 << 10), 210 CMD_DESC_SNOOP_ENABLE = (1 << 9), 211 FPDMA_QUEUED_CMD = (1 << 8), 212 SRST_CMD = (1 << 7), 213 BIST = (1 << 6), 214 ATAPI_CMD = (1 << 5), 215 }; 216 217 /* 218 * Command Descriptor 219 */ 220 struct command_desc { 221 u8 cfis[8 * 4]; 222 u8 sfis[8 * 4]; 223 u8 acmd[4 * 4]; 224 u8 fill[4 * 4]; 225 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 226 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 227 }; 228 229 /* 230 * Physical region table descriptor(PRD) 231 */ 232 233 struct prde { 234 u32 dba; 235 u8 fill[2 * 4]; 236 u32 ddc_and_ext; 237 }; 238 239 /* 240 * ata_port private data 241 * This is our per-port instance data. 242 */ 243 struct sata_fsl_port_priv { 244 struct cmdhdr_tbl_entry *cmdslot; 245 dma_addr_t cmdslot_paddr; 246 struct command_desc *cmdentry; 247 dma_addr_t cmdentry_paddr; 248 }; 249 250 /* 251 * ata_port->host_set private data 252 */ 253 struct sata_fsl_host_priv { 254 void __iomem *hcr_base; 255 void __iomem *ssr_base; 256 void __iomem *csr_base; 257 int irq; 258 }; 259 260 static inline unsigned int sata_fsl_tag(unsigned int tag, 261 void __iomem *hcr_base) 262 { 263 /* We let libATA core do actual (queue) tag allocation */ 264 265 /* all non NCQ/queued commands should have tag#0 */ 266 if (ata_tag_internal(tag)) { 267 DPRINTK("mapping internal cmds to tag#0\n"); 268 return 0; 269 } 270 271 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 272 DPRINTK("tag %d invalid : out of range\n", tag); 273 return 0; 274 } 275 276 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 277 DPRINTK("tag %d invalid : in use!!\n", tag); 278 return 0; 279 } 280 281 return tag; 282 } 283 284 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 285 unsigned int tag, u32 desc_info, 286 u32 data_xfer_len, u8 num_prde, 287 u8 fis_len) 288 { 289 dma_addr_t cmd_descriptor_address; 290 291 cmd_descriptor_address = pp->cmdentry_paddr + 292 tag * SATA_FSL_CMD_DESC_SIZE; 293 294 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 295 296 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 297 pp->cmdslot[tag].prde_fis_len = 298 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 299 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 300 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 301 302 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 303 pp->cmdslot[tag].cda, 304 pp->cmdslot[tag].prde_fis_len, 305 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 306 307 } 308 309 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 310 u32 *ttl, dma_addr_t cmd_desc_paddr) 311 { 312 struct scatterlist *sg; 313 unsigned int num_prde = 0; 314 u32 ttl_dwords = 0; 315 316 /* 317 * NOTE : direct & indirect prdt's are contigiously allocated 318 */ 319 struct prde *prd = (struct prde *)&((struct command_desc *) 320 cmd_desc)->prdt; 321 322 struct prde *prd_ptr_to_indirect_ext = NULL; 323 unsigned indirect_ext_segment_sz = 0; 324 dma_addr_t indirect_ext_segment_paddr; 325 unsigned int si; 326 327 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 328 329 indirect_ext_segment_paddr = cmd_desc_paddr + 330 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 331 332 for_each_sg(qc->sg, sg, qc->n_elem, si) { 333 dma_addr_t sg_addr = sg_dma_address(sg); 334 u32 sg_len = sg_dma_len(sg); 335 336 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", 337 (unsigned long long)sg_addr, sg_len); 338 339 /* warn if each s/g element is not dword aligned */ 340 if (sg_addr & 0x03) 341 ata_port_printk(qc->ap, KERN_ERR, 342 "s/g addr unaligned : 0x%llx\n", 343 (unsigned long long)sg_addr); 344 if (sg_len & 0x03) 345 ata_port_printk(qc->ap, KERN_ERR, 346 "s/g len unaligned : 0x%x\n", sg_len); 347 348 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 349 sg_next(sg) != NULL) { 350 VPRINTK("setting indirect prde\n"); 351 prd_ptr_to_indirect_ext = prd; 352 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 353 indirect_ext_segment_sz = 0; 354 ++prd; 355 ++num_prde; 356 } 357 358 ttl_dwords += sg_len; 359 prd->dba = cpu_to_le32(sg_addr); 360 prd->ddc_and_ext = 361 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); 362 363 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 364 ttl_dwords, prd->dba, prd->ddc_and_ext); 365 366 ++num_prde; 367 ++prd; 368 if (prd_ptr_to_indirect_ext) 369 indirect_ext_segment_sz += sg_len; 370 } 371 372 if (prd_ptr_to_indirect_ext) { 373 /* set indirect extension flag along with indirect ext. size */ 374 prd_ptr_to_indirect_ext->ddc_and_ext = 375 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 376 DATA_SNOOP_ENABLE | 377 (indirect_ext_segment_sz & ~0x03))); 378 } 379 380 *ttl = ttl_dwords; 381 return num_prde; 382 } 383 384 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 385 { 386 struct ata_port *ap = qc->ap; 387 struct sata_fsl_port_priv *pp = ap->private_data; 388 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 389 void __iomem *hcr_base = host_priv->hcr_base; 390 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 391 struct command_desc *cd; 392 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 393 u32 num_prde = 0; 394 u32 ttl_dwords = 0; 395 dma_addr_t cd_paddr; 396 397 cd = (struct command_desc *)pp->cmdentry + tag; 398 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 399 400 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 401 402 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 403 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 404 405 if (qc->tf.protocol == ATA_PROT_NCQ) { 406 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 407 cd->cfis[3], cd->cfis[11]); 408 } 409 410 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 411 if (ata_is_atapi(qc->tf.protocol)) { 412 desc_info |= ATAPI_CMD; 413 memset((void *)&cd->acmd, 0, 32); 414 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 415 } 416 417 if (qc->flags & ATA_QCFLAG_DMAMAP) 418 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 419 &ttl_dwords, cd_paddr); 420 421 if (qc->tf.protocol == ATA_PROT_NCQ) 422 desc_info |= FPDMA_QUEUED_CMD; 423 424 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 425 num_prde, 5); 426 427 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 428 desc_info, ttl_dwords, num_prde); 429 } 430 431 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 432 { 433 struct ata_port *ap = qc->ap; 434 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 435 void __iomem *hcr_base = host_priv->hcr_base; 436 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 437 438 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 439 ioread32(CQ + hcr_base), 440 ioread32(CA + hcr_base), 441 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 442 443 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 444 445 /* Simply queue command to the controller/device */ 446 iowrite32(1 << tag, CQ + hcr_base); 447 448 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 449 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 450 451 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 452 ioread32(CE + hcr_base), 453 ioread32(DE + hcr_base), 454 ioread32(CC + hcr_base), 455 ioread32(COMMANDSTAT + host_priv->csr_base)); 456 457 return 0; 458 } 459 460 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 461 { 462 struct sata_fsl_port_priv *pp = qc->ap->private_data; 463 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 464 void __iomem *hcr_base = host_priv->hcr_base; 465 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 466 struct command_desc *cd; 467 468 cd = pp->cmdentry + tag; 469 470 ata_tf_from_fis(cd->sfis, &qc->result_tf); 471 return true; 472 } 473 474 static int sata_fsl_scr_write(struct ata_link *link, 475 unsigned int sc_reg_in, u32 val) 476 { 477 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 478 void __iomem *ssr_base = host_priv->ssr_base; 479 unsigned int sc_reg; 480 481 switch (sc_reg_in) { 482 case SCR_STATUS: 483 case SCR_ERROR: 484 case SCR_CONTROL: 485 case SCR_ACTIVE: 486 sc_reg = sc_reg_in; 487 break; 488 default: 489 return -EINVAL; 490 } 491 492 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 493 494 iowrite32(val, ssr_base + (sc_reg * 4)); 495 return 0; 496 } 497 498 static int sata_fsl_scr_read(struct ata_link *link, 499 unsigned int sc_reg_in, u32 *val) 500 { 501 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 502 void __iomem *ssr_base = host_priv->ssr_base; 503 unsigned int sc_reg; 504 505 switch (sc_reg_in) { 506 case SCR_STATUS: 507 case SCR_ERROR: 508 case SCR_CONTROL: 509 case SCR_ACTIVE: 510 sc_reg = sc_reg_in; 511 break; 512 default: 513 return -EINVAL; 514 } 515 516 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 517 518 *val = ioread32(ssr_base + (sc_reg * 4)); 519 return 0; 520 } 521 522 static void sata_fsl_freeze(struct ata_port *ap) 523 { 524 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 525 void __iomem *hcr_base = host_priv->hcr_base; 526 u32 temp; 527 528 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 529 ioread32(CQ + hcr_base), 530 ioread32(CA + hcr_base), 531 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 532 VPRINTK("CmdStat = 0x%x\n", 533 ioread32(host_priv->csr_base + COMMANDSTAT)); 534 535 /* disable interrupts on the controller/port */ 536 temp = ioread32(hcr_base + HCONTROL); 537 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 538 539 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 540 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 541 } 542 543 static void sata_fsl_thaw(struct ata_port *ap) 544 { 545 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 546 void __iomem *hcr_base = host_priv->hcr_base; 547 u32 temp; 548 549 /* ack. any pending IRQs for this controller/port */ 550 temp = ioread32(hcr_base + HSTATUS); 551 552 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 553 554 if (temp & 0x3F) 555 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 556 557 /* enable interrupts on the controller/port */ 558 temp = ioread32(hcr_base + HCONTROL); 559 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 560 561 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 562 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 563 } 564 565 static void sata_fsl_pmp_attach(struct ata_port *ap) 566 { 567 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 568 void __iomem *hcr_base = host_priv->hcr_base; 569 u32 temp; 570 571 temp = ioread32(hcr_base + HCONTROL); 572 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 573 } 574 575 static void sata_fsl_pmp_detach(struct ata_port *ap) 576 { 577 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 578 void __iomem *hcr_base = host_priv->hcr_base; 579 u32 temp; 580 581 temp = ioread32(hcr_base + HCONTROL); 582 temp &= ~HCONTROL_PMP_ATTACHED; 583 iowrite32(temp, hcr_base + HCONTROL); 584 585 /* enable interrupts on the controller/port */ 586 temp = ioread32(hcr_base + HCONTROL); 587 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 588 589 } 590 591 static int sata_fsl_port_start(struct ata_port *ap) 592 { 593 struct device *dev = ap->host->dev; 594 struct sata_fsl_port_priv *pp; 595 void *mem; 596 dma_addr_t mem_dma; 597 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 598 void __iomem *hcr_base = host_priv->hcr_base; 599 u32 temp; 600 601 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 602 if (!pp) 603 return -ENOMEM; 604 605 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 606 GFP_KERNEL); 607 if (!mem) { 608 kfree(pp); 609 return -ENOMEM; 610 } 611 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 612 613 pp->cmdslot = mem; 614 pp->cmdslot_paddr = mem_dma; 615 616 mem += SATA_FSL_CMD_SLOT_SIZE; 617 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 618 619 pp->cmdentry = mem; 620 pp->cmdentry_paddr = mem_dma; 621 622 ap->private_data = pp; 623 624 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 625 pp->cmdslot_paddr, pp->cmdentry_paddr); 626 627 /* Now, update the CHBA register in host controller cmd register set */ 628 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 629 630 /* 631 * Now, we can bring the controller on-line & also initiate 632 * the COMINIT sequence, we simply return here and the boot-probing 633 * & device discovery process is re-initiated by libATA using a 634 * Softreset EH (dummy) session. Hence, boot probing and device 635 * discovey will be part of sata_fsl_softreset() callback. 636 */ 637 638 temp = ioread32(hcr_base + HCONTROL); 639 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 640 641 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 642 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 643 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 644 645 #ifdef CONFIG_MPC8315_DS 646 /* 647 * Workaround for 8315DS board 3gbps link-up issue, 648 * currently limit SATA port to GEN1 speed 649 */ 650 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 651 temp &= ~(0xF << 4); 652 temp |= (0x1 << 4); 653 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp); 654 655 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 656 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", 657 temp); 658 #endif 659 660 return 0; 661 } 662 663 static void sata_fsl_port_stop(struct ata_port *ap) 664 { 665 struct device *dev = ap->host->dev; 666 struct sata_fsl_port_priv *pp = ap->private_data; 667 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 668 void __iomem *hcr_base = host_priv->hcr_base; 669 u32 temp; 670 671 /* 672 * Force host controller to go off-line, aborting current operations 673 */ 674 temp = ioread32(hcr_base + HCONTROL); 675 temp &= ~HCONTROL_ONLINE_PHY_RST; 676 temp |= HCONTROL_FORCE_OFFLINE; 677 iowrite32(temp, hcr_base + HCONTROL); 678 679 /* Poll for controller to go offline - should happen immediately */ 680 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 681 682 ap->private_data = NULL; 683 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 684 pp->cmdslot, pp->cmdslot_paddr); 685 686 kfree(pp); 687 } 688 689 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 690 { 691 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 692 void __iomem *hcr_base = host_priv->hcr_base; 693 struct ata_taskfile tf; 694 u32 temp; 695 696 temp = ioread32(hcr_base + SIGNATURE); 697 698 VPRINTK("raw sig = 0x%x\n", temp); 699 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 700 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 701 702 tf.lbah = (temp >> 24) & 0xff; 703 tf.lbam = (temp >> 16) & 0xff; 704 tf.lbal = (temp >> 8) & 0xff; 705 tf.nsect = temp & 0xff; 706 707 return ata_dev_classify(&tf); 708 } 709 710 static int sata_fsl_prereset(struct ata_link *link, unsigned long deadline) 711 { 712 /* FIXME: Never skip softreset, sata_fsl_softreset() is 713 * combination of soft and hard resets. sata_fsl_softreset() 714 * needs to be splitted into soft and hard resets. 715 */ 716 return 0; 717 } 718 719 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 720 unsigned long deadline) 721 { 722 struct ata_port *ap = link->ap; 723 struct sata_fsl_port_priv *pp = ap->private_data; 724 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 725 void __iomem *hcr_base = host_priv->hcr_base; 726 int pmp = sata_srst_pmp(link); 727 u32 temp; 728 struct ata_taskfile tf; 729 u8 *cfis; 730 u32 Serror; 731 int i = 0; 732 unsigned long start_jiffies; 733 734 DPRINTK("in xx_softreset\n"); 735 736 if (pmp != SATA_PMP_CTRL_PORT) 737 goto issue_srst; 738 739 try_offline_again: 740 /* 741 * Force host controller to go off-line, aborting current operations 742 */ 743 temp = ioread32(hcr_base + HCONTROL); 744 temp &= ~HCONTROL_ONLINE_PHY_RST; 745 iowrite32(temp, hcr_base + HCONTROL); 746 747 /* Poll for controller to go offline */ 748 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); 749 750 if (temp & ONLINE) { 751 ata_port_printk(ap, KERN_ERR, 752 "Softreset failed, not off-lined %d\n", i); 753 754 /* 755 * Try to offline controller atleast twice 756 */ 757 i++; 758 if (i == 2) 759 goto err; 760 else 761 goto try_offline_again; 762 } 763 764 DPRINTK("softreset, controller off-lined\n"); 765 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 766 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 767 768 /* 769 * PHY reset should remain asserted for atleast 1ms 770 */ 771 msleep(1); 772 773 /* 774 * Now, bring the host controller online again, this can take time 775 * as PHY reset and communication establishment, 1st D2H FIS and 776 * device signature update is done, on safe side assume 500ms 777 * NOTE : Host online status may be indicated immediately!! 778 */ 779 780 temp = ioread32(hcr_base + HCONTROL); 781 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 782 temp |= HCONTROL_PMP_ATTACHED; 783 iowrite32(temp, hcr_base + HCONTROL); 784 785 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); 786 787 if (!(temp & ONLINE)) { 788 ata_port_printk(ap, KERN_ERR, 789 "Softreset failed, not on-lined\n"); 790 goto err; 791 } 792 793 DPRINTK("softreset, controller off-lined & on-lined\n"); 794 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 795 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 796 797 /* 798 * First, wait for the PHYRDY change to occur before waiting for 799 * the signature, and also verify if SStatus indicates device 800 * presence 801 */ 802 803 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); 804 if ((!(temp & 0x10)) || ata_link_offline(link)) { 805 ata_port_printk(ap, KERN_WARNING, 806 "No Device OR PHYRDY change,Hstatus = 0x%x\n", 807 ioread32(hcr_base + HSTATUS)); 808 *class = ATA_DEV_NONE; 809 goto out; 810 } 811 812 /* 813 * Wait for the first D2H from device,i.e,signature update notification 814 */ 815 start_jiffies = jiffies; 816 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, 817 500, jiffies_to_msecs(deadline - start_jiffies)); 818 819 if ((temp & 0xFF) != 0x18) { 820 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); 821 *class = ATA_DEV_NONE; 822 goto out; 823 } else { 824 ata_port_printk(ap, KERN_INFO, 825 "Signature Update detected @ %d msecs\n", 826 jiffies_to_msecs(jiffies - start_jiffies)); 827 } 828 829 /* 830 * Send a device reset (SRST) explicitly on command slot #0 831 * Check : will the command queue (reg) be cleared during offlining ?? 832 * Also we will be online only if Phy commn. has been established 833 * and device presence has been detected, therefore if we have 834 * reached here, we can send a command to the target device 835 */ 836 837 issue_srst: 838 DPRINTK("Sending SRST/device reset\n"); 839 840 ata_tf_init(link->device, &tf); 841 cfis = (u8 *) &pp->cmdentry->cfis; 842 843 /* device reset/SRST is a control register update FIS, uses tag0 */ 844 sata_fsl_setup_cmd_hdr_entry(pp, 0, 845 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 846 847 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 848 ata_tf_to_fis(&tf, pmp, 0, cfis); 849 850 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 851 cfis[0], cfis[1], cfis[2], cfis[3]); 852 853 /* 854 * Queue SRST command to the controller/device, ensure that no 855 * other commands are active on the controller/device 856 */ 857 858 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 859 ioread32(CQ + hcr_base), 860 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 861 862 iowrite32(0xFFFF, CC + hcr_base); 863 iowrite32(1, CQ + hcr_base); 864 865 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); 866 if (temp & 0x1) { 867 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); 868 869 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 870 ioread32(CQ + hcr_base), 871 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 872 873 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 874 875 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 876 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 877 DPRINTK("Serror = 0x%x\n", Serror); 878 goto err; 879 } 880 881 msleep(1); 882 883 /* 884 * SATA device enters reset state after receving a Control register 885 * FIS with SRST bit asserted and it awaits another H2D Control reg. 886 * FIS with SRST bit cleared, then the device does internal diags & 887 * initialization, followed by indicating it's initialization status 888 * using ATA signature D2H register FIS to the host controller. 889 */ 890 891 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 892 0, 0, 5); 893 894 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 895 ata_tf_to_fis(&tf, pmp, 0, cfis); 896 897 if (pmp != SATA_PMP_CTRL_PORT) 898 iowrite32(pmp, CQPMP + hcr_base); 899 iowrite32(1, CQ + hcr_base); 900 msleep(150); /* ?? */ 901 902 /* 903 * The above command would have signalled an interrupt on command 904 * complete, which needs special handling, by clearing the Nth 905 * command bit of the CCreg 906 */ 907 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 908 909 DPRINTK("SATA FSL : Now checking device signature\n"); 910 911 *class = ATA_DEV_NONE; 912 913 /* Verify if SStatus indicates device presence */ 914 if (ata_link_online(link)) { 915 /* 916 * if we are here, device presence has been detected, 917 * 1st D2H FIS would have been received, but sfis in 918 * command desc. is not updated, but signature register 919 * would have been updated 920 */ 921 922 *class = sata_fsl_dev_classify(ap); 923 924 DPRINTK("class = %d\n", *class); 925 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 926 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 927 } 928 929 out: 930 return 0; 931 932 err: 933 return -EIO; 934 } 935 936 static void sata_fsl_error_handler(struct ata_port *ap) 937 { 938 939 DPRINTK("in xx_error_handler\n"); 940 sata_pmp_error_handler(ap); 941 942 } 943 944 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 945 { 946 if (qc->flags & ATA_QCFLAG_FAILED) 947 qc->err_mask |= AC_ERR_OTHER; 948 949 if (qc->err_mask) { 950 /* make DMA engine forget about the failed command */ 951 952 } 953 } 954 955 static void sata_fsl_error_intr(struct ata_port *ap) 956 { 957 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 958 void __iomem *hcr_base = host_priv->hcr_base; 959 u32 hstatus, dereg=0, cereg = 0, SError = 0; 960 unsigned int err_mask = 0, action = 0; 961 int freeze = 0, abort=0; 962 struct ata_link *link = NULL; 963 struct ata_queued_cmd *qc = NULL; 964 struct ata_eh_info *ehi; 965 966 hstatus = ioread32(hcr_base + HSTATUS); 967 cereg = ioread32(hcr_base + CE); 968 969 /* first, analyze and record host port events */ 970 link = &ap->link; 971 ehi = &link->eh_info; 972 ata_ehi_clear_desc(ehi); 973 974 /* 975 * Handle & Clear SError 976 */ 977 978 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 979 if (unlikely(SError & 0xFFFF0000)) { 980 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 981 } 982 983 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 984 hstatus, cereg, ioread32(hcr_base + DE), SError); 985 986 /* handle fatal errors */ 987 if (hstatus & FATAL_ERROR_DECODE) { 988 ehi->err_mask |= AC_ERR_ATA_BUS; 989 ehi->action |= ATA_EH_SOFTRESET; 990 991 /* 992 * Ignore serror in case of fatal errors as we always want 993 * to do a soft-reset of the FSL SATA controller. Analyzing 994 * serror may cause libata to schedule a hard-reset action, 995 * and hard-reset currently does not do controller 996 * offline/online, causing command timeouts and leads to an 997 * un-recoverable state, hence make libATA ignore 998 * autopsy in case of fatal errors. 999 */ 1000 1001 ehi->flags |= ATA_EHI_NO_AUTOPSY; 1002 1003 freeze = 1; 1004 } 1005 1006 /* Handle PHYRDY change notification */ 1007 if (hstatus & INT_ON_PHYRDY_CHG) { 1008 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1009 1010 /* Setup a soft-reset EH action */ 1011 ata_ehi_hotplugged(ehi); 1012 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1013 freeze = 1; 1014 } 1015 1016 /* handle single device errors */ 1017 if (cereg) { 1018 /* 1019 * clear the command error, also clears queue to the device 1020 * in error, and we can (re)issue commands to this device. 1021 * When a device is in error all commands queued into the 1022 * host controller and at the device are considered aborted 1023 * and the queue for that device is stopped. Now, after 1024 * clearing the device error, we can issue commands to the 1025 * device to interrogate it to find the source of the error. 1026 */ 1027 abort = 1; 1028 1029 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 1030 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1031 1032 /* find out the offending link and qc */ 1033 if (ap->nr_pmp_links) { 1034 dereg = ioread32(hcr_base + DE); 1035 iowrite32(dereg, hcr_base + DE); 1036 iowrite32(cereg, hcr_base + CE); 1037 1038 if (dereg < ap->nr_pmp_links) { 1039 link = &ap->pmp_link[dereg]; 1040 ehi = &link->eh_info; 1041 qc = ata_qc_from_tag(ap, link->active_tag); 1042 /* 1043 * We should consider this as non fatal error, 1044 * and TF must be updated as done below. 1045 */ 1046 1047 err_mask |= AC_ERR_DEV; 1048 1049 } else { 1050 err_mask |= AC_ERR_HSM; 1051 action |= ATA_EH_HARDRESET; 1052 freeze = 1; 1053 } 1054 } else { 1055 dereg = ioread32(hcr_base + DE); 1056 iowrite32(dereg, hcr_base + DE); 1057 iowrite32(cereg, hcr_base + CE); 1058 1059 qc = ata_qc_from_tag(ap, link->active_tag); 1060 /* 1061 * We should consider this as non fatal error, 1062 * and TF must be updated as done below. 1063 */ 1064 err_mask |= AC_ERR_DEV; 1065 } 1066 } 1067 1068 /* record error info */ 1069 if (qc) { 1070 qc->err_mask |= err_mask; 1071 } else 1072 ehi->err_mask |= err_mask; 1073 1074 ehi->action |= action; 1075 1076 /* freeze or abort */ 1077 if (freeze) 1078 ata_port_freeze(ap); 1079 else if (abort) { 1080 if (qc) 1081 ata_link_abort(qc->dev->link); 1082 else 1083 ata_port_abort(ap); 1084 } 1085 } 1086 1087 static void sata_fsl_host_intr(struct ata_port *ap) 1088 { 1089 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1090 void __iomem *hcr_base = host_priv->hcr_base; 1091 u32 hstatus, qc_active = 0; 1092 struct ata_queued_cmd *qc; 1093 u32 SError; 1094 1095 hstatus = ioread32(hcr_base + HSTATUS); 1096 1097 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1098 1099 if (unlikely(SError & 0xFFFF0000)) { 1100 DPRINTK("serror @host_intr : 0x%x\n", SError); 1101 sata_fsl_error_intr(ap); 1102 1103 } 1104 1105 if (unlikely(hstatus & INT_ON_ERROR)) { 1106 DPRINTK("error interrupt!!\n"); 1107 sata_fsl_error_intr(ap); 1108 return; 1109 } 1110 1111 /* Read command completed register */ 1112 qc_active = ioread32(hcr_base + CC); 1113 1114 VPRINTK("Status of all queues :\n"); 1115 VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", 1116 qc_active, 1117 ioread32(hcr_base + CA), 1118 ioread32(hcr_base + CE), 1119 ioread32(hcr_base + CQ), 1120 ap->qc_active); 1121 1122 if (qc_active & ap->qc_active) { 1123 int i; 1124 /* clear CC bit, this will also complete the interrupt */ 1125 iowrite32(qc_active, hcr_base + CC); 1126 1127 DPRINTK("Status of all queues :\n"); 1128 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1129 qc_active, ioread32(hcr_base + CA), 1130 ioread32(hcr_base + CE)); 1131 1132 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1133 if (qc_active & (1 << i)) { 1134 qc = ata_qc_from_tag(ap, i); 1135 if (qc) { 1136 ata_qc_complete(qc); 1137 } 1138 DPRINTK 1139 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1140 i, ioread32(hcr_base + CC), 1141 ioread32(hcr_base + CA)); 1142 } 1143 } 1144 return; 1145 1146 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { 1147 iowrite32(1, hcr_base + CC); 1148 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1149 1150 DPRINTK("completing non-ncq cmd, CC=0x%x\n", 1151 ioread32(hcr_base + CC)); 1152 1153 if (qc) { 1154 ata_qc_complete(qc); 1155 } 1156 } else { 1157 /* Spurious Interrupt!! */ 1158 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1159 ioread32(hcr_base + CC)); 1160 iowrite32(qc_active, hcr_base + CC); 1161 return; 1162 } 1163 } 1164 1165 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1166 { 1167 struct ata_host *host = dev_instance; 1168 struct sata_fsl_host_priv *host_priv = host->private_data; 1169 void __iomem *hcr_base = host_priv->hcr_base; 1170 u32 interrupt_enables; 1171 unsigned handled = 0; 1172 struct ata_port *ap; 1173 1174 /* ack. any pending IRQs for this controller/port */ 1175 interrupt_enables = ioread32(hcr_base + HSTATUS); 1176 interrupt_enables &= 0x3F; 1177 1178 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1179 1180 if (!interrupt_enables) 1181 return IRQ_NONE; 1182 1183 spin_lock(&host->lock); 1184 1185 /* Assuming one port per host controller */ 1186 1187 ap = host->ports[0]; 1188 if (ap) { 1189 sata_fsl_host_intr(ap); 1190 } else { 1191 dev_printk(KERN_WARNING, host->dev, 1192 "interrupt on disabled port 0\n"); 1193 } 1194 1195 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1196 handled = 1; 1197 1198 spin_unlock(&host->lock); 1199 1200 return IRQ_RETVAL(handled); 1201 } 1202 1203 /* 1204 * Multiple ports are represented by multiple SATA controllers with 1205 * one port per controller 1206 */ 1207 static int sata_fsl_init_controller(struct ata_host *host) 1208 { 1209 struct sata_fsl_host_priv *host_priv = host->private_data; 1210 void __iomem *hcr_base = host_priv->hcr_base; 1211 u32 temp; 1212 1213 /* 1214 * NOTE : We cannot bring the controller online before setting 1215 * the CHBA, hence main controller initialization is done as 1216 * part of the port_start() callback 1217 */ 1218 1219 /* ack. any pending IRQs for this controller/port */ 1220 temp = ioread32(hcr_base + HSTATUS); 1221 if (temp & 0x3F) 1222 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1223 1224 /* Keep interrupts disabled on the controller */ 1225 temp = ioread32(hcr_base + HCONTROL); 1226 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1227 1228 /* Disable interrupt coalescing control(icc), for the moment */ 1229 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1230 iowrite32(0x01000000, hcr_base + ICC); 1231 1232 /* clear error registers, SError is cleared by libATA */ 1233 iowrite32(0x00000FFFF, hcr_base + CE); 1234 iowrite32(0x00000FFFF, hcr_base + DE); 1235 1236 /* 1237 * host controller will be brought on-line, during xx_port_start() 1238 * callback, that should also initiate the OOB, COMINIT sequence 1239 */ 1240 1241 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1242 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1243 1244 return 0; 1245 } 1246 1247 /* 1248 * scsi mid-layer and libata interface structures 1249 */ 1250 static struct scsi_host_template sata_fsl_sht = { 1251 ATA_NCQ_SHT("sata_fsl"), 1252 .can_queue = SATA_FSL_QUEUE_DEPTH, 1253 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1254 .dma_boundary = ATA_DMA_BOUNDARY, 1255 }; 1256 1257 static struct ata_port_operations sata_fsl_ops = { 1258 .inherits = &sata_pmp_port_ops, 1259 1260 .qc_prep = sata_fsl_qc_prep, 1261 .qc_issue = sata_fsl_qc_issue, 1262 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1263 1264 .scr_read = sata_fsl_scr_read, 1265 .scr_write = sata_fsl_scr_write, 1266 1267 .freeze = sata_fsl_freeze, 1268 .thaw = sata_fsl_thaw, 1269 .prereset = sata_fsl_prereset, 1270 .softreset = sata_fsl_softreset, 1271 .pmp_softreset = sata_fsl_softreset, 1272 .error_handler = sata_fsl_error_handler, 1273 .post_internal_cmd = sata_fsl_post_internal_cmd, 1274 1275 .port_start = sata_fsl_port_start, 1276 .port_stop = sata_fsl_port_stop, 1277 1278 .pmp_attach = sata_fsl_pmp_attach, 1279 .pmp_detach = sata_fsl_pmp_detach, 1280 }; 1281 1282 static const struct ata_port_info sata_fsl_port_info[] = { 1283 { 1284 .flags = SATA_FSL_HOST_FLAGS, 1285 .pio_mask = ATA_PIO4, 1286 .udma_mask = ATA_UDMA6, 1287 .port_ops = &sata_fsl_ops, 1288 }, 1289 }; 1290 1291 static int sata_fsl_probe(struct of_device *ofdev, 1292 const struct of_device_id *match) 1293 { 1294 int retval = -ENXIO; 1295 void __iomem *hcr_base = NULL; 1296 void __iomem *ssr_base = NULL; 1297 void __iomem *csr_base = NULL; 1298 struct sata_fsl_host_priv *host_priv = NULL; 1299 int irq; 1300 struct ata_host *host; 1301 1302 struct ata_port_info pi = sata_fsl_port_info[0]; 1303 const struct ata_port_info *ppi[] = { &pi, NULL }; 1304 1305 dev_printk(KERN_INFO, &ofdev->dev, 1306 "Sata FSL Platform/CSB Driver init\n"); 1307 1308 hcr_base = of_iomap(ofdev->node, 0); 1309 if (!hcr_base) 1310 goto error_exit_with_cleanup; 1311 1312 ssr_base = hcr_base + 0x100; 1313 csr_base = hcr_base + 0x140; 1314 1315 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1316 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1317 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1318 1319 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1320 if (!host_priv) 1321 goto error_exit_with_cleanup; 1322 1323 host_priv->hcr_base = hcr_base; 1324 host_priv->ssr_base = ssr_base; 1325 host_priv->csr_base = csr_base; 1326 1327 irq = irq_of_parse_and_map(ofdev->node, 0); 1328 if (irq < 0) { 1329 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); 1330 goto error_exit_with_cleanup; 1331 } 1332 host_priv->irq = irq; 1333 1334 /* allocate host structure */ 1335 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1336 1337 /* host->iomap is not used currently */ 1338 host->private_data = host_priv; 1339 1340 /* initialize host controller */ 1341 sata_fsl_init_controller(host); 1342 1343 /* 1344 * Now, register with libATA core, this will also initiate the 1345 * device discovery process, invoking our port_start() handler & 1346 * error_handler() to execute a dummy Softreset EH session 1347 */ 1348 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1349 &sata_fsl_sht); 1350 1351 dev_set_drvdata(&ofdev->dev, host); 1352 1353 return 0; 1354 1355 error_exit_with_cleanup: 1356 1357 if (hcr_base) 1358 iounmap(hcr_base); 1359 if (host_priv) 1360 kfree(host_priv); 1361 1362 return retval; 1363 } 1364 1365 static int sata_fsl_remove(struct of_device *ofdev) 1366 { 1367 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1368 struct sata_fsl_host_priv *host_priv = host->private_data; 1369 1370 ata_host_detach(host); 1371 1372 dev_set_drvdata(&ofdev->dev, NULL); 1373 1374 irq_dispose_mapping(host_priv->irq); 1375 iounmap(host_priv->hcr_base); 1376 kfree(host_priv); 1377 1378 return 0; 1379 } 1380 1381 static struct of_device_id fsl_sata_match[] = { 1382 { 1383 .compatible = "fsl,pq-sata", 1384 }, 1385 {}, 1386 }; 1387 1388 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1389 1390 static struct of_platform_driver fsl_sata_driver = { 1391 .name = "fsl-sata", 1392 .match_table = fsl_sata_match, 1393 .probe = sata_fsl_probe, 1394 .remove = sata_fsl_remove, 1395 }; 1396 1397 static int __init sata_fsl_init(void) 1398 { 1399 of_register_platform_driver(&fsl_sata_driver); 1400 return 0; 1401 } 1402 1403 static void __exit sata_fsl_exit(void) 1404 { 1405 of_unregister_platform_driver(&fsl_sata_driver); 1406 } 1407 1408 MODULE_LICENSE("GPL"); 1409 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1410 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1411 MODULE_VERSION("1.10"); 1412 1413 module_init(sata_fsl_init); 1414 module_exit(sata_fsl_exit); 1415