1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/ata/sata_fsl.c 4 * 5 * Freescale 3.0Gbps SATA device driver 6 * 7 * Author: Ashish Kalra <ashish.kalra@freescale.com> 8 * Li Yang <leoli@freescale.com> 9 * 10 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 18 #include <scsi/scsi_host.h> 19 #include <scsi/scsi_cmnd.h> 20 #include <linux/libata.h> 21 #include <asm/io.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 26 static unsigned int intr_coalescing_count; 27 module_param(intr_coalescing_count, int, S_IRUGO); 28 MODULE_PARM_DESC(intr_coalescing_count, 29 "INT coalescing count threshold (1..31)"); 30 31 static unsigned int intr_coalescing_ticks; 32 module_param(intr_coalescing_ticks, int, S_IRUGO); 33 MODULE_PARM_DESC(intr_coalescing_ticks, 34 "INT coalescing timer threshold in AHB ticks"); 35 /* Controller information */ 36 enum { 37 SATA_FSL_QUEUE_DEPTH = 16, 38 SATA_FSL_MAX_PRD = 63, 39 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 40 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 41 42 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 43 ATA_FLAG_PMP | ATA_FLAG_NCQ | 44 ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE), 45 46 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 47 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 48 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 49 50 /* 51 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 52 * chained indirect PRDEs up to a max count of 63. 53 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will 54 * be setup as an indirect descriptor, pointing to it's next 55 * (contiguous) PRDE. Though chained indirect PRDE arrays are 56 * supported,it will be more efficient to use a direct PRDT and 57 * a single chain/link to indirect PRDE array/PRDT. 58 */ 59 60 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 61 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 62 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 63 SATA_FSL_CMD_DESC_RSRVD = 16, 64 65 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 66 SATA_FSL_CMD_DESC_SFIS_SZ + 67 SATA_FSL_CMD_DESC_ACMD_SZ + 68 SATA_FSL_CMD_DESC_RSRVD + 69 SATA_FSL_MAX_PRD * 16), 70 71 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 72 (SATA_FSL_CMD_DESC_CFIS_SZ + 73 SATA_FSL_CMD_DESC_SFIS_SZ + 74 SATA_FSL_CMD_DESC_ACMD_SZ + 75 SATA_FSL_CMD_DESC_RSRVD), 76 77 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 78 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 79 SATA_FSL_CMD_DESC_AR_SZ), 80 81 /* 82 * MPC8315 has two SATA controllers, SATA1 & SATA2 83 * (one port per controller) 84 * MPC837x has 2/4 controllers, one port per controller 85 */ 86 87 SATA_FSL_MAX_PORTS = 1, 88 89 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 90 }; 91 92 /* 93 * Interrupt Coalescing Control Register bitdefs */ 94 enum { 95 ICC_MIN_INT_COUNT_THRESHOLD = 1, 96 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1), 97 ICC_MIN_INT_TICKS_THRESHOLD = 0, 98 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1), 99 ICC_SAFE_INT_TICKS = 1, 100 }; 101 102 /* 103 * Host Controller command register set - per port 104 */ 105 enum { 106 CQ = 0, 107 CA = 8, 108 CC = 0x10, 109 CE = 0x18, 110 DE = 0x20, 111 CHBA = 0x24, 112 HSTATUS = 0x28, 113 HCONTROL = 0x2C, 114 CQPMP = 0x30, 115 SIGNATURE = 0x34, 116 ICC = 0x38, 117 118 /* 119 * Host Status Register (HStatus) bitdefs 120 */ 121 ONLINE = (1 << 31), 122 GOING_OFFLINE = (1 << 30), 123 BIST_ERR = (1 << 29), 124 CLEAR_ERROR = (1 << 27), 125 126 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 127 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 128 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 129 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 130 FATAL_ERR_DATA_OVERRUN = (1 << 12), 131 FATAL_ERR_CRC_ERR_TX = (1 << 11), 132 FATAL_ERR_CRC_ERR_RX = (1 << 10), 133 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 134 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 135 136 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 137 FATAL_ERR_PARITY_ERR_TX | 138 FATAL_ERR_PARITY_ERR_RX | 139 FATAL_ERR_DATA_UNDERRUN | 140 FATAL_ERR_DATA_OVERRUN | 141 FATAL_ERR_CRC_ERR_TX | 142 FATAL_ERR_CRC_ERR_RX | 143 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 144 145 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12), 146 INT_ON_FATAL_ERR = (1 << 5), 147 INT_ON_PHYRDY_CHG = (1 << 4), 148 149 INT_ON_SIGNATURE_UPDATE = (1 << 3), 150 INT_ON_SNOTIFY_UPDATE = (1 << 2), 151 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 152 INT_ON_CMD_COMPLETE = 1, 153 154 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | 155 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 156 157 /* 158 * Host Control Register (HControl) bitdefs 159 */ 160 HCONTROL_ONLINE_PHY_RST = (1 << 31), 161 HCONTROL_FORCE_OFFLINE = (1 << 30), 162 HCONTROL_LEGACY = (1 << 28), 163 HCONTROL_PARITY_PROT_MOD = (1 << 14), 164 HCONTROL_DPATH_PARITY = (1 << 12), 165 HCONTROL_SNOOP_ENABLE = (1 << 10), 166 HCONTROL_PMP_ATTACHED = (1 << 9), 167 HCONTROL_COPYOUT_STATFIS = (1 << 8), 168 IE_ON_FATAL_ERR = (1 << 5), 169 IE_ON_PHYRDY_CHG = (1 << 4), 170 IE_ON_SIGNATURE_UPDATE = (1 << 3), 171 IE_ON_SNOTIFY_UPDATE = (1 << 2), 172 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 173 IE_ON_CMD_COMPLETE = 1, 174 175 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 176 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | 177 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 178 179 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 180 DATA_SNOOP_ENABLE_V1 = (1 << 22), 181 DATA_SNOOP_ENABLE_V2 = (1 << 28), 182 }; 183 184 /* 185 * SATA Superset Registers 186 */ 187 enum { 188 SSTATUS = 0, 189 SERROR = 4, 190 SCONTROL = 8, 191 SNOTIFY = 0xC, 192 }; 193 194 /* 195 * Control Status Register Set 196 */ 197 enum { 198 TRANSCFG = 0, 199 TRANSSTATUS = 4, 200 LINKCFG = 8, 201 LINKCFG1 = 0xC, 202 LINKCFG2 = 0x10, 203 LINKSTATUS = 0x14, 204 LINKSTATUS1 = 0x18, 205 PHYCTRLCFG = 0x1C, 206 COMMANDSTAT = 0x20, 207 }; 208 209 /* TRANSCFG (transport-layer) configuration control */ 210 enum { 211 TRANSCFG_RX_WATER_MARK = (1 << 4), 212 }; 213 214 /* PHY (link-layer) configuration control */ 215 enum { 216 PHY_BIST_ENABLE = 0x01, 217 }; 218 219 /* 220 * Command Header Table entry, i.e, command slot 221 * 4 Dwords per command slot, command header size == 64 Dwords. 222 */ 223 struct cmdhdr_tbl_entry { 224 __le32 cda; 225 __le32 prde_fis_len; 226 __le32 ttl; 227 __le32 desc_info; 228 }; 229 230 /* 231 * Description information bitdefs 232 */ 233 enum { 234 CMD_DESC_RES = (1 << 11), 235 VENDOR_SPECIFIC_BIST = (1 << 10), 236 CMD_DESC_SNOOP_ENABLE = (1 << 9), 237 FPDMA_QUEUED_CMD = (1 << 8), 238 SRST_CMD = (1 << 7), 239 BIST = (1 << 6), 240 ATAPI_CMD = (1 << 5), 241 }; 242 243 /* 244 * Command Descriptor 245 */ 246 struct command_desc { 247 u8 cfis[8 * 4]; 248 u8 sfis[8 * 4]; 249 struct_group(cdb, 250 u8 acmd[4 * 4]; 251 u8 fill[4 * 4]; 252 ); 253 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 254 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 255 }; 256 257 /* 258 * Physical region table descriptor(PRD) 259 */ 260 261 struct prde { 262 __le32 dba; 263 u8 fill[2 * 4]; 264 __le32 ddc_and_ext; 265 }; 266 267 /* 268 * ata_port private data 269 * This is our per-port instance data. 270 */ 271 struct sata_fsl_port_priv { 272 struct cmdhdr_tbl_entry *cmdslot; 273 dma_addr_t cmdslot_paddr; 274 struct command_desc *cmdentry; 275 dma_addr_t cmdentry_paddr; 276 }; 277 278 /* 279 * ata_port->host_set private data 280 */ 281 struct sata_fsl_host_priv { 282 void __iomem *hcr_base; 283 void __iomem *ssr_base; 284 void __iomem *csr_base; 285 int irq; 286 int data_snoop; 287 struct device_attribute intr_coalescing; 288 struct device_attribute rx_watermark; 289 }; 290 291 static void fsl_sata_set_irq_coalescing(struct ata_host *host, 292 unsigned int count, unsigned int ticks) 293 { 294 struct sata_fsl_host_priv *host_priv = host->private_data; 295 void __iomem *hcr_base = host_priv->hcr_base; 296 unsigned long flags; 297 298 if (count > ICC_MAX_INT_COUNT_THRESHOLD) 299 count = ICC_MAX_INT_COUNT_THRESHOLD; 300 else if (count < ICC_MIN_INT_COUNT_THRESHOLD) 301 count = ICC_MIN_INT_COUNT_THRESHOLD; 302 303 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD) 304 ticks = ICC_MAX_INT_TICKS_THRESHOLD; 305 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) && 306 (count > ICC_MIN_INT_COUNT_THRESHOLD)) 307 ticks = ICC_SAFE_INT_TICKS; 308 309 spin_lock_irqsave(&host->lock, flags); 310 iowrite32((count << 24 | ticks), hcr_base + ICC); 311 312 intr_coalescing_count = count; 313 intr_coalescing_ticks = ticks; 314 spin_unlock_irqrestore(&host->lock, flags); 315 316 dev_dbg(host->dev, "interrupt coalescing, count = 0x%x, ticks = %x\n", 317 intr_coalescing_count, intr_coalescing_ticks); 318 dev_dbg(host->dev, "ICC register status: (hcr base: 0x%p) = 0x%x\n", 319 hcr_base, ioread32(hcr_base + ICC)); 320 } 321 322 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev, 323 struct device_attribute *attr, char *buf) 324 { 325 return sysfs_emit(buf, "%u %u\n", 326 intr_coalescing_count, intr_coalescing_ticks); 327 } 328 329 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev, 330 struct device_attribute *attr, 331 const char *buf, size_t count) 332 { 333 unsigned int coalescing_count, coalescing_ticks; 334 335 if (sscanf(buf, "%u%u", &coalescing_count, &coalescing_ticks) != 2) { 336 dev_err(dev, "fsl-sata: wrong parameter format.\n"); 337 return -EINVAL; 338 } 339 340 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev), 341 coalescing_count, coalescing_ticks); 342 343 return strlen(buf); 344 } 345 346 static ssize_t fsl_sata_rx_watermark_show(struct device *dev, 347 struct device_attribute *attr, char *buf) 348 { 349 unsigned int rx_watermark; 350 unsigned long flags; 351 struct ata_host *host = dev_get_drvdata(dev); 352 struct sata_fsl_host_priv *host_priv = host->private_data; 353 void __iomem *csr_base = host_priv->csr_base; 354 355 spin_lock_irqsave(&host->lock, flags); 356 rx_watermark = ioread32(csr_base + TRANSCFG); 357 rx_watermark &= 0x1f; 358 spin_unlock_irqrestore(&host->lock, flags); 359 360 return sysfs_emit(buf, "%u\n", rx_watermark); 361 } 362 363 static ssize_t fsl_sata_rx_watermark_store(struct device *dev, 364 struct device_attribute *attr, 365 const char *buf, size_t count) 366 { 367 unsigned int rx_watermark; 368 unsigned long flags; 369 struct ata_host *host = dev_get_drvdata(dev); 370 struct sata_fsl_host_priv *host_priv = host->private_data; 371 void __iomem *csr_base = host_priv->csr_base; 372 u32 temp; 373 374 if (kstrtouint(buf, 10, &rx_watermark) < 0) { 375 dev_err(dev, "fsl-sata: wrong parameter format.\n"); 376 return -EINVAL; 377 } 378 379 spin_lock_irqsave(&host->lock, flags); 380 temp = ioread32(csr_base + TRANSCFG); 381 temp &= 0xffffffe0; 382 iowrite32(temp | rx_watermark, csr_base + TRANSCFG); 383 spin_unlock_irqrestore(&host->lock, flags); 384 385 return strlen(buf); 386 } 387 388 static inline unsigned int sata_fsl_tag(struct ata_port *ap, 389 unsigned int tag, 390 void __iomem *hcr_base) 391 { 392 /* We let libATA core do actual (queue) tag allocation */ 393 394 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 395 ata_port_dbg(ap, "tag %d invalid : out of range\n", tag); 396 return 0; 397 } 398 399 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 400 ata_port_dbg(ap, "tag %d invalid : in use!!\n", tag); 401 return 0; 402 } 403 404 return tag; 405 } 406 407 static void sata_fsl_setup_cmd_hdr_entry(struct ata_port *ap, 408 struct sata_fsl_port_priv *pp, 409 unsigned int tag, u32 desc_info, 410 u32 data_xfer_len, u8 num_prde, 411 u8 fis_len) 412 { 413 dma_addr_t cmd_descriptor_address; 414 415 cmd_descriptor_address = pp->cmdentry_paddr + 416 tag * SATA_FSL_CMD_DESC_SIZE; 417 418 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 419 420 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 421 pp->cmdslot[tag].prde_fis_len = 422 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 423 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 424 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 425 426 ata_port_dbg(ap, "cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 427 le32_to_cpu(pp->cmdslot[tag].cda), 428 le32_to_cpu(pp->cmdslot[tag].prde_fis_len), 429 le32_to_cpu(pp->cmdslot[tag].ttl), 430 le32_to_cpu(pp->cmdslot[tag].desc_info)); 431 } 432 433 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 434 u32 *ttl, dma_addr_t cmd_desc_paddr, 435 int data_snoop) 436 { 437 struct scatterlist *sg; 438 unsigned int num_prde = 0; 439 u32 ttl_dwords = 0; 440 441 /* 442 * NOTE : direct & indirect prdt's are contiguously allocated 443 */ 444 struct prde *prd = (struct prde *)&((struct command_desc *) 445 cmd_desc)->prdt; 446 447 struct prde *prd_ptr_to_indirect_ext = NULL; 448 unsigned indirect_ext_segment_sz = 0; 449 dma_addr_t indirect_ext_segment_paddr; 450 unsigned int si; 451 452 indirect_ext_segment_paddr = cmd_desc_paddr + 453 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 454 455 for_each_sg(qc->sg, sg, qc->n_elem, si) { 456 dma_addr_t sg_addr = sg_dma_address(sg); 457 u32 sg_len = sg_dma_len(sg); 458 459 /* warn if each s/g element is not dword aligned */ 460 if (unlikely(sg_addr & 0x03)) 461 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n", 462 (unsigned long long)sg_addr); 463 if (unlikely(sg_len & 0x03)) 464 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n", 465 sg_len); 466 467 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 468 sg_next(sg) != NULL) { 469 prd_ptr_to_indirect_ext = prd; 470 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 471 indirect_ext_segment_sz = 0; 472 ++prd; 473 ++num_prde; 474 } 475 476 ttl_dwords += sg_len; 477 prd->dba = cpu_to_le32(sg_addr); 478 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); 479 480 ++num_prde; 481 ++prd; 482 if (prd_ptr_to_indirect_ext) 483 indirect_ext_segment_sz += sg_len; 484 } 485 486 if (prd_ptr_to_indirect_ext) { 487 /* set indirect extension flag along with indirect ext. size */ 488 prd_ptr_to_indirect_ext->ddc_and_ext = 489 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 490 data_snoop | 491 (indirect_ext_segment_sz & ~0x03))); 492 } 493 494 *ttl = ttl_dwords; 495 return num_prde; 496 } 497 498 static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc) 499 { 500 struct ata_port *ap = qc->ap; 501 struct sata_fsl_port_priv *pp = ap->private_data; 502 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 503 void __iomem *hcr_base = host_priv->hcr_base; 504 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base); 505 struct command_desc *cd; 506 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 507 u32 num_prde = 0; 508 u32 ttl_dwords = 0; 509 dma_addr_t cd_paddr; 510 511 cd = (struct command_desc *)pp->cmdentry + tag; 512 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 513 514 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 515 516 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 517 if (ata_is_atapi(qc->tf.protocol)) { 518 desc_info |= ATAPI_CMD; 519 memset(&cd->cdb, 0, sizeof(cd->cdb)); 520 memcpy(&cd->cdb, qc->cdb, qc->dev->cdb_len); 521 } 522 523 if (qc->flags & ATA_QCFLAG_DMAMAP) 524 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 525 &ttl_dwords, cd_paddr, 526 host_priv->data_snoop); 527 528 if (qc->tf.protocol == ATA_PROT_NCQ) 529 desc_info |= FPDMA_QUEUED_CMD; 530 531 sata_fsl_setup_cmd_hdr_entry(ap, pp, tag, desc_info, ttl_dwords, 532 num_prde, 5); 533 534 ata_port_dbg(ap, "SATA FSL : di = 0x%x, ttl = %d, num_prde = %d\n", 535 desc_info, ttl_dwords, num_prde); 536 537 return AC_ERR_OK; 538 } 539 540 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 541 { 542 struct ata_port *ap = qc->ap; 543 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 544 void __iomem *hcr_base = host_priv->hcr_base; 545 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base); 546 547 ata_port_dbg(ap, "CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 548 ioread32(CQ + hcr_base), 549 ioread32(CA + hcr_base), 550 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 551 552 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 553 554 /* Simply queue command to the controller/device */ 555 iowrite32(1 << tag, CQ + hcr_base); 556 557 ata_port_dbg(ap, "tag=%d, CQ=0x%x, CA=0x%x\n", 558 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 559 560 ata_port_dbg(ap, "CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 561 ioread32(CE + hcr_base), 562 ioread32(DE + hcr_base), 563 ioread32(CC + hcr_base), 564 ioread32(COMMANDSTAT + host_priv->csr_base)); 565 566 return 0; 567 } 568 569 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 570 { 571 struct sata_fsl_port_priv *pp = qc->ap->private_data; 572 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 573 void __iomem *hcr_base = host_priv->hcr_base; 574 unsigned int tag = sata_fsl_tag(qc->ap, qc->hw_tag, hcr_base); 575 struct command_desc *cd; 576 577 cd = pp->cmdentry + tag; 578 579 ata_tf_from_fis(cd->sfis, &qc->result_tf); 580 return true; 581 } 582 583 static int sata_fsl_scr_write(struct ata_link *link, 584 unsigned int sc_reg_in, u32 val) 585 { 586 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 587 void __iomem *ssr_base = host_priv->ssr_base; 588 unsigned int sc_reg; 589 590 switch (sc_reg_in) { 591 case SCR_STATUS: 592 case SCR_ERROR: 593 case SCR_CONTROL: 594 case SCR_ACTIVE: 595 sc_reg = sc_reg_in; 596 break; 597 default: 598 return -EINVAL; 599 } 600 601 ata_link_dbg(link, "reg_in = %d\n", sc_reg); 602 603 iowrite32(val, ssr_base + (sc_reg * 4)); 604 return 0; 605 } 606 607 static int sata_fsl_scr_read(struct ata_link *link, 608 unsigned int sc_reg_in, u32 *val) 609 { 610 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 611 void __iomem *ssr_base = host_priv->ssr_base; 612 unsigned int sc_reg; 613 614 switch (sc_reg_in) { 615 case SCR_STATUS: 616 case SCR_ERROR: 617 case SCR_CONTROL: 618 case SCR_ACTIVE: 619 sc_reg = sc_reg_in; 620 break; 621 default: 622 return -EINVAL; 623 } 624 625 ata_link_dbg(link, "reg_in = %d\n", sc_reg); 626 627 *val = ioread32(ssr_base + (sc_reg * 4)); 628 return 0; 629 } 630 631 static void sata_fsl_freeze(struct ata_port *ap) 632 { 633 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 634 void __iomem *hcr_base = host_priv->hcr_base; 635 u32 temp; 636 637 ata_port_dbg(ap, "CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 638 ioread32(CQ + hcr_base), 639 ioread32(CA + hcr_base), 640 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 641 ata_port_dbg(ap, "CmdStat = 0x%x\n", 642 ioread32(host_priv->csr_base + COMMANDSTAT)); 643 644 /* disable interrupts on the controller/port */ 645 temp = ioread32(hcr_base + HCONTROL); 646 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 647 648 ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n", 649 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 650 } 651 652 static void sata_fsl_thaw(struct ata_port *ap) 653 { 654 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 655 void __iomem *hcr_base = host_priv->hcr_base; 656 u32 temp; 657 658 /* ack. any pending IRQs for this controller/port */ 659 temp = ioread32(hcr_base + HSTATUS); 660 661 ata_port_dbg(ap, "pending IRQs = 0x%x\n", (temp & 0x3F)); 662 663 if (temp & 0x3F) 664 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 665 666 /* enable interrupts on the controller/port */ 667 temp = ioread32(hcr_base + HCONTROL); 668 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 669 670 ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n", 671 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 672 } 673 674 static void sata_fsl_pmp_attach(struct ata_port *ap) 675 { 676 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 677 void __iomem *hcr_base = host_priv->hcr_base; 678 u32 temp; 679 680 temp = ioread32(hcr_base + HCONTROL); 681 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 682 } 683 684 static void sata_fsl_pmp_detach(struct ata_port *ap) 685 { 686 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 687 void __iomem *hcr_base = host_priv->hcr_base; 688 u32 temp; 689 690 temp = ioread32(hcr_base + HCONTROL); 691 temp &= ~HCONTROL_PMP_ATTACHED; 692 iowrite32(temp, hcr_base + HCONTROL); 693 694 /* enable interrupts on the controller/port */ 695 temp = ioread32(hcr_base + HCONTROL); 696 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 697 698 } 699 700 static int sata_fsl_port_start(struct ata_port *ap) 701 { 702 struct device *dev = ap->host->dev; 703 struct sata_fsl_port_priv *pp; 704 void *mem; 705 dma_addr_t mem_dma; 706 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 707 void __iomem *hcr_base = host_priv->hcr_base; 708 u32 temp; 709 710 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 711 if (!pp) 712 return -ENOMEM; 713 714 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 715 GFP_KERNEL); 716 if (!mem) { 717 kfree(pp); 718 return -ENOMEM; 719 } 720 721 pp->cmdslot = mem; 722 pp->cmdslot_paddr = mem_dma; 723 724 mem += SATA_FSL_CMD_SLOT_SIZE; 725 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 726 727 pp->cmdentry = mem; 728 pp->cmdentry_paddr = mem_dma; 729 730 ap->private_data = pp; 731 732 ata_port_dbg(ap, "CHBA = 0x%lx, cmdentry_phys = 0x%lx\n", 733 (unsigned long)pp->cmdslot_paddr, 734 (unsigned long)pp->cmdentry_paddr); 735 736 /* Now, update the CHBA register in host controller cmd register set */ 737 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 738 739 /* 740 * Now, we can bring the controller on-line & also initiate 741 * the COMINIT sequence, we simply return here and the boot-probing 742 * & device discovery process is re-initiated by libATA using a 743 * Softreset EH (dummy) session. Hence, boot probing and device 744 * discovey will be part of sata_fsl_softreset() callback. 745 */ 746 747 temp = ioread32(hcr_base + HCONTROL); 748 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 749 750 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 751 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 752 ata_port_dbg(ap, "CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 753 754 return 0; 755 } 756 757 static void sata_fsl_port_stop(struct ata_port *ap) 758 { 759 struct device *dev = ap->host->dev; 760 struct sata_fsl_port_priv *pp = ap->private_data; 761 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 762 void __iomem *hcr_base = host_priv->hcr_base; 763 u32 temp; 764 765 /* 766 * Force host controller to go off-line, aborting current operations 767 */ 768 temp = ioread32(hcr_base + HCONTROL); 769 temp &= ~HCONTROL_ONLINE_PHY_RST; 770 temp |= HCONTROL_FORCE_OFFLINE; 771 iowrite32(temp, hcr_base + HCONTROL); 772 773 /* Poll for controller to go offline - should happen immediately */ 774 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 775 776 ap->private_data = NULL; 777 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 778 pp->cmdslot, pp->cmdslot_paddr); 779 780 kfree(pp); 781 } 782 783 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 784 { 785 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 786 void __iomem *hcr_base = host_priv->hcr_base; 787 struct ata_taskfile tf; 788 u32 temp; 789 790 temp = ioread32(hcr_base + SIGNATURE); 791 792 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 793 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 794 795 tf.lbah = (temp >> 24) & 0xff; 796 tf.lbam = (temp >> 16) & 0xff; 797 tf.lbal = (temp >> 8) & 0xff; 798 tf.nsect = temp & 0xff; 799 800 return ata_port_classify(ap, &tf); 801 } 802 803 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, 804 unsigned long deadline) 805 { 806 struct ata_port *ap = link->ap; 807 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 808 void __iomem *hcr_base = host_priv->hcr_base; 809 u32 temp; 810 int i = 0; 811 unsigned long start_jiffies; 812 813 try_offline_again: 814 /* 815 * Force host controller to go off-line, aborting current operations 816 */ 817 temp = ioread32(hcr_base + HCONTROL); 818 temp &= ~HCONTROL_ONLINE_PHY_RST; 819 iowrite32(temp, hcr_base + HCONTROL); 820 821 /* Poll for controller to go offline */ 822 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 823 1, 500); 824 825 if (temp & ONLINE) { 826 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i); 827 828 /* 829 * Try to offline controller atleast twice 830 */ 831 i++; 832 if (i == 2) 833 goto err; 834 else 835 goto try_offline_again; 836 } 837 838 ata_port_dbg(ap, "hardreset, controller off-lined\n" 839 "HStatus = 0x%x HControl = 0x%x\n", 840 ioread32(hcr_base + HSTATUS), 841 ioread32(hcr_base + HCONTROL)); 842 843 /* 844 * PHY reset should remain asserted for atleast 1ms 845 */ 846 ata_msleep(ap, 1); 847 848 sata_set_spd(link); 849 850 /* 851 * Now, bring the host controller online again, this can take time 852 * as PHY reset and communication establishment, 1st D2H FIS and 853 * device signature update is done, on safe side assume 500ms 854 * NOTE : Host online status may be indicated immediately!! 855 */ 856 857 temp = ioread32(hcr_base + HCONTROL); 858 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 859 temp |= HCONTROL_PMP_ATTACHED; 860 iowrite32(temp, hcr_base + HCONTROL); 861 862 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); 863 864 if (!(temp & ONLINE)) { 865 ata_port_err(ap, "Hardreset failed, not on-lined\n"); 866 goto err; 867 } 868 869 ata_port_dbg(ap, "controller off-lined & on-lined\n" 870 "HStatus = 0x%x HControl = 0x%x\n", 871 ioread32(hcr_base + HSTATUS), 872 ioread32(hcr_base + HCONTROL)); 873 874 /* 875 * First, wait for the PHYRDY change to occur before waiting for 876 * the signature, and also verify if SStatus indicates device 877 * presence 878 */ 879 880 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); 881 if ((!(temp & 0x10)) || ata_link_offline(link)) { 882 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n", 883 ioread32(hcr_base + HSTATUS)); 884 *class = ATA_DEV_NONE; 885 return 0; 886 } 887 888 /* 889 * Wait for the first D2H from device,i.e,signature update notification 890 */ 891 start_jiffies = jiffies; 892 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, 893 500, jiffies_to_msecs(deadline - start_jiffies)); 894 895 if ((temp & 0xFF) != 0x18) { 896 ata_port_warn(ap, "No Signature Update\n"); 897 *class = ATA_DEV_NONE; 898 goto do_followup_srst; 899 } else { 900 ata_port_info(ap, "Signature Update detected @ %d msecs\n", 901 jiffies_to_msecs(jiffies - start_jiffies)); 902 *class = sata_fsl_dev_classify(ap); 903 return 0; 904 } 905 906 do_followup_srst: 907 /* 908 * request libATA to perform follow-up softreset 909 */ 910 return -EAGAIN; 911 912 err: 913 return -EIO; 914 } 915 916 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 917 unsigned long deadline) 918 { 919 struct ata_port *ap = link->ap; 920 struct sata_fsl_port_priv *pp = ap->private_data; 921 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 922 void __iomem *hcr_base = host_priv->hcr_base; 923 int pmp = sata_srst_pmp(link); 924 u32 temp; 925 struct ata_taskfile tf; 926 u8 *cfis; 927 u32 Serror; 928 929 if (ata_link_offline(link)) { 930 *class = ATA_DEV_NONE; 931 return 0; 932 } 933 934 /* 935 * Send a device reset (SRST) explicitly on command slot #0 936 * Check : will the command queue (reg) be cleared during offlining ?? 937 * Also we will be online only if Phy commn. has been established 938 * and device presence has been detected, therefore if we have 939 * reached here, we can send a command to the target device 940 */ 941 942 ata_tf_init(link->device, &tf); 943 cfis = (u8 *) &pp->cmdentry->cfis; 944 945 /* device reset/SRST is a control register update FIS, uses tag0 */ 946 sata_fsl_setup_cmd_hdr_entry(ap, pp, 0, 947 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 948 949 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 950 ata_tf_to_fis(&tf, pmp, 0, cfis); 951 952 ata_port_dbg(ap, "Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 953 cfis[0], cfis[1], cfis[2], cfis[3]); 954 955 /* 956 * Queue SRST command to the controller/device, ensure that no 957 * other commands are active on the controller/device 958 */ 959 960 ata_port_dbg(ap, "CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 961 ioread32(CQ + hcr_base), 962 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 963 964 iowrite32(0xFFFF, CC + hcr_base); 965 if (pmp != SATA_PMP_CTRL_PORT) 966 iowrite32(pmp, CQPMP + hcr_base); 967 iowrite32(1, CQ + hcr_base); 968 969 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); 970 if (temp & 0x1) { 971 ata_port_warn(ap, "ATA_SRST issue failed\n"); 972 973 ata_port_dbg(ap, "Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 974 ioread32(CQ + hcr_base), 975 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 976 977 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 978 979 ata_port_dbg(ap, "HStatus = 0x%x HControl = 0x%x Serror = 0x%x\n", 980 ioread32(hcr_base + HSTATUS), 981 ioread32(hcr_base + HCONTROL), 982 Serror); 983 goto err; 984 } 985 986 ata_msleep(ap, 1); 987 988 /* 989 * SATA device enters reset state after receiving a Control register 990 * FIS with SRST bit asserted and it awaits another H2D Control reg. 991 * FIS with SRST bit cleared, then the device does internal diags & 992 * initialization, followed by indicating it's initialization status 993 * using ATA signature D2H register FIS to the host controller. 994 */ 995 996 sata_fsl_setup_cmd_hdr_entry(ap, pp, 0, 997 CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 998 0, 0, 5); 999 1000 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 1001 ata_tf_to_fis(&tf, pmp, 0, cfis); 1002 1003 if (pmp != SATA_PMP_CTRL_PORT) 1004 iowrite32(pmp, CQPMP + hcr_base); 1005 iowrite32(1, CQ + hcr_base); 1006 ata_msleep(ap, 150); /* ?? */ 1007 1008 /* 1009 * The above command would have signalled an interrupt on command 1010 * complete, which needs special handling, by clearing the Nth 1011 * command bit of the CCreg 1012 */ 1013 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 1014 1015 *class = ATA_DEV_NONE; 1016 1017 /* Verify if SStatus indicates device presence */ 1018 if (ata_link_online(link)) { 1019 /* 1020 * if we are here, device presence has been detected, 1021 * 1st D2H FIS would have been received, but sfis in 1022 * command desc. is not updated, but signature register 1023 * would have been updated 1024 */ 1025 1026 *class = sata_fsl_dev_classify(ap); 1027 1028 ata_port_dbg(ap, "ccreg = 0x%x\n", ioread32(hcr_base + CC)); 1029 ata_port_dbg(ap, "cereg = 0x%x\n", ioread32(hcr_base + CE)); 1030 } 1031 1032 return 0; 1033 1034 err: 1035 return -EIO; 1036 } 1037 1038 static void sata_fsl_error_handler(struct ata_port *ap) 1039 { 1040 sata_pmp_error_handler(ap); 1041 } 1042 1043 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 1044 { 1045 if (qc->flags & ATA_QCFLAG_FAILED) 1046 qc->err_mask |= AC_ERR_OTHER; 1047 1048 if (qc->err_mask) { 1049 /* make DMA engine forget about the failed command */ 1050 1051 } 1052 } 1053 1054 static void sata_fsl_error_intr(struct ata_port *ap) 1055 { 1056 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1057 void __iomem *hcr_base = host_priv->hcr_base; 1058 u32 hstatus, dereg=0, cereg = 0, SError = 0; 1059 unsigned int err_mask = 0, action = 0; 1060 int freeze = 0, abort=0; 1061 struct ata_link *link = NULL; 1062 struct ata_queued_cmd *qc = NULL; 1063 struct ata_eh_info *ehi; 1064 1065 hstatus = ioread32(hcr_base + HSTATUS); 1066 cereg = ioread32(hcr_base + CE); 1067 1068 /* first, analyze and record host port events */ 1069 link = &ap->link; 1070 ehi = &link->eh_info; 1071 ata_ehi_clear_desc(ehi); 1072 1073 /* 1074 * Handle & Clear SError 1075 */ 1076 1077 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1078 if (unlikely(SError & 0xFFFF0000)) 1079 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 1080 1081 ata_port_dbg(ap, "hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 1082 hstatus, cereg, ioread32(hcr_base + DE), SError); 1083 1084 /* handle fatal errors */ 1085 if (hstatus & FATAL_ERROR_DECODE) { 1086 ehi->err_mask |= AC_ERR_ATA_BUS; 1087 ehi->action |= ATA_EH_SOFTRESET; 1088 1089 freeze = 1; 1090 } 1091 1092 /* Handle SDB FIS receive & notify update */ 1093 if (hstatus & INT_ON_SNOTIFY_UPDATE) 1094 sata_async_notification(ap); 1095 1096 /* Handle PHYRDY change notification */ 1097 if (hstatus & INT_ON_PHYRDY_CHG) { 1098 ata_port_dbg(ap, "PHYRDY change indication\n"); 1099 1100 /* Setup a soft-reset EH action */ 1101 ata_ehi_hotplugged(ehi); 1102 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1103 freeze = 1; 1104 } 1105 1106 /* handle single device errors */ 1107 if (cereg) { 1108 /* 1109 * clear the command error, also clears queue to the device 1110 * in error, and we can (re)issue commands to this device. 1111 * When a device is in error all commands queued into the 1112 * host controller and at the device are considered aborted 1113 * and the queue for that device is stopped. Now, after 1114 * clearing the device error, we can issue commands to the 1115 * device to interrogate it to find the source of the error. 1116 */ 1117 abort = 1; 1118 1119 ata_port_dbg(ap, "single device error, CE=0x%x, DE=0x%x\n", 1120 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1121 1122 /* find out the offending link and qc */ 1123 if (ap->nr_pmp_links) { 1124 unsigned int dev_num; 1125 1126 dereg = ioread32(hcr_base + DE); 1127 iowrite32(dereg, hcr_base + DE); 1128 iowrite32(cereg, hcr_base + CE); 1129 1130 dev_num = ffs(dereg) - 1; 1131 if (dev_num < ap->nr_pmp_links && dereg != 0) { 1132 link = &ap->pmp_link[dev_num]; 1133 ehi = &link->eh_info; 1134 qc = ata_qc_from_tag(ap, link->active_tag); 1135 /* 1136 * We should consider this as non fatal error, 1137 * and TF must be updated as done below. 1138 */ 1139 1140 err_mask |= AC_ERR_DEV; 1141 1142 } else { 1143 err_mask |= AC_ERR_HSM; 1144 action |= ATA_EH_HARDRESET; 1145 freeze = 1; 1146 } 1147 } else { 1148 dereg = ioread32(hcr_base + DE); 1149 iowrite32(dereg, hcr_base + DE); 1150 iowrite32(cereg, hcr_base + CE); 1151 1152 qc = ata_qc_from_tag(ap, link->active_tag); 1153 /* 1154 * We should consider this as non fatal error, 1155 * and TF must be updated as done below. 1156 */ 1157 err_mask |= AC_ERR_DEV; 1158 } 1159 } 1160 1161 /* record error info */ 1162 if (qc) 1163 qc->err_mask |= err_mask; 1164 else 1165 ehi->err_mask |= err_mask; 1166 1167 ehi->action |= action; 1168 1169 /* freeze or abort */ 1170 if (freeze) 1171 ata_port_freeze(ap); 1172 else if (abort) { 1173 if (qc) 1174 ata_link_abort(qc->dev->link); 1175 else 1176 ata_port_abort(ap); 1177 } 1178 } 1179 1180 static void sata_fsl_host_intr(struct ata_port *ap) 1181 { 1182 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1183 void __iomem *hcr_base = host_priv->hcr_base; 1184 u32 hstatus, done_mask = 0; 1185 struct ata_queued_cmd *qc; 1186 u32 SError; 1187 u32 tag; 1188 u32 status_mask = INT_ON_ERROR; 1189 1190 hstatus = ioread32(hcr_base + HSTATUS); 1191 1192 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1193 1194 /* Read command completed register */ 1195 done_mask = ioread32(hcr_base + CC); 1196 1197 /* Workaround for data length mismatch errata */ 1198 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) { 1199 ata_qc_for_each_with_internal(ap, qc, tag) { 1200 if (qc && ata_is_atapi(qc->tf.protocol)) { 1201 u32 hcontrol; 1202 /* Set HControl[27] to clear error registers */ 1203 hcontrol = ioread32(hcr_base + HCONTROL); 1204 iowrite32(hcontrol | CLEAR_ERROR, 1205 hcr_base + HCONTROL); 1206 1207 /* Clear HControl[27] */ 1208 iowrite32(hcontrol & ~CLEAR_ERROR, 1209 hcr_base + HCONTROL); 1210 1211 /* Clear SError[E] bit */ 1212 sata_fsl_scr_write(&ap->link, SCR_ERROR, 1213 SError); 1214 1215 /* Ignore fatal error and device error */ 1216 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR 1217 | INT_ON_FATAL_ERR); 1218 break; 1219 } 1220 } 1221 } 1222 1223 if (unlikely(SError & 0xFFFF0000)) { 1224 ata_port_dbg(ap, "serror @host_intr : 0x%x\n", SError); 1225 sata_fsl_error_intr(ap); 1226 } 1227 1228 if (unlikely(hstatus & status_mask)) { 1229 ata_port_dbg(ap, "error interrupt!!\n"); 1230 sata_fsl_error_intr(ap); 1231 return; 1232 } 1233 1234 ata_port_dbg(ap, "Status of all queues :\n"); 1235 ata_port_dbg(ap, "done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n", 1236 done_mask, 1237 ioread32(hcr_base + CA), 1238 ioread32(hcr_base + CE), 1239 ioread32(hcr_base + CQ), 1240 ap->qc_active); 1241 1242 if (done_mask & ap->qc_active) { 1243 int i; 1244 /* clear CC bit, this will also complete the interrupt */ 1245 iowrite32(done_mask, hcr_base + CC); 1246 1247 ata_port_dbg(ap, "Status of all queues: done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1248 done_mask, ioread32(hcr_base + CA), 1249 ioread32(hcr_base + CE)); 1250 1251 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1252 if (done_mask & (1 << i)) 1253 ata_port_dbg(ap, "completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1254 i, ioread32(hcr_base + CC), 1255 ioread32(hcr_base + CA)); 1256 } 1257 ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask); 1258 return; 1259 1260 } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) { 1261 iowrite32(1, hcr_base + CC); 1262 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1263 1264 ata_port_dbg(ap, "completing non-ncq cmd, CC=0x%x\n", 1265 ioread32(hcr_base + CC)); 1266 1267 if (qc) { 1268 ata_qc_complete(qc); 1269 } 1270 } else { 1271 /* Spurious Interrupt!! */ 1272 ata_port_dbg(ap, "spurious interrupt!!, CC = 0x%x\n", 1273 ioread32(hcr_base + CC)); 1274 iowrite32(done_mask, hcr_base + CC); 1275 return; 1276 } 1277 } 1278 1279 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1280 { 1281 struct ata_host *host = dev_instance; 1282 struct sata_fsl_host_priv *host_priv = host->private_data; 1283 void __iomem *hcr_base = host_priv->hcr_base; 1284 u32 interrupt_enables; 1285 unsigned handled = 0; 1286 struct ata_port *ap; 1287 1288 /* ack. any pending IRQs for this controller/port */ 1289 interrupt_enables = ioread32(hcr_base + HSTATUS); 1290 interrupt_enables &= 0x3F; 1291 1292 if (!interrupt_enables) 1293 return IRQ_NONE; 1294 1295 spin_lock(&host->lock); 1296 1297 /* Assuming one port per host controller */ 1298 1299 ap = host->ports[0]; 1300 if (ap) { 1301 sata_fsl_host_intr(ap); 1302 } else { 1303 dev_warn(host->dev, "interrupt on disabled port 0\n"); 1304 } 1305 1306 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1307 handled = 1; 1308 1309 spin_unlock(&host->lock); 1310 1311 return IRQ_RETVAL(handled); 1312 } 1313 1314 /* 1315 * Multiple ports are represented by multiple SATA controllers with 1316 * one port per controller 1317 */ 1318 static int sata_fsl_init_controller(struct ata_host *host) 1319 { 1320 struct sata_fsl_host_priv *host_priv = host->private_data; 1321 void __iomem *hcr_base = host_priv->hcr_base; 1322 u32 temp; 1323 1324 /* 1325 * NOTE : We cannot bring the controller online before setting 1326 * the CHBA, hence main controller initialization is done as 1327 * part of the port_start() callback 1328 */ 1329 1330 /* sata controller to operate in enterprise mode */ 1331 temp = ioread32(hcr_base + HCONTROL); 1332 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); 1333 1334 /* ack. any pending IRQs for this controller/port */ 1335 temp = ioread32(hcr_base + HSTATUS); 1336 if (temp & 0x3F) 1337 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1338 1339 /* Keep interrupts disabled on the controller */ 1340 temp = ioread32(hcr_base + HCONTROL); 1341 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1342 1343 /* Disable interrupt coalescing control(icc), for the moment */ 1344 dev_dbg(host->dev, "icc = 0x%x\n", ioread32(hcr_base + ICC)); 1345 iowrite32(0x01000000, hcr_base + ICC); 1346 1347 /* clear error registers, SError is cleared by libATA */ 1348 iowrite32(0x00000FFFF, hcr_base + CE); 1349 iowrite32(0x00000FFFF, hcr_base + DE); 1350 1351 /* 1352 * reset the number of command complete bits which will cause the 1353 * interrupt to be signaled 1354 */ 1355 fsl_sata_set_irq_coalescing(host, intr_coalescing_count, 1356 intr_coalescing_ticks); 1357 1358 /* 1359 * host controller will be brought on-line, during xx_port_start() 1360 * callback, that should also initiate the OOB, COMINIT sequence 1361 */ 1362 1363 dev_dbg(host->dev, "HStatus = 0x%x HControl = 0x%x\n", 1364 ioread32(hcr_base + HSTATUS), ioread32(hcr_base + HCONTROL)); 1365 1366 return 0; 1367 } 1368 1369 static void sata_fsl_host_stop(struct ata_host *host) 1370 { 1371 struct sata_fsl_host_priv *host_priv = host->private_data; 1372 1373 iounmap(host_priv->hcr_base); 1374 kfree(host_priv); 1375 } 1376 1377 /* 1378 * scsi mid-layer and libata interface structures 1379 */ 1380 static struct scsi_host_template sata_fsl_sht = { 1381 ATA_NCQ_SHT_QD("sata_fsl", SATA_FSL_QUEUE_DEPTH), 1382 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1383 .dma_boundary = ATA_DMA_BOUNDARY, 1384 }; 1385 1386 static struct ata_port_operations sata_fsl_ops = { 1387 .inherits = &sata_pmp_port_ops, 1388 1389 .qc_defer = ata_std_qc_defer, 1390 .qc_prep = sata_fsl_qc_prep, 1391 .qc_issue = sata_fsl_qc_issue, 1392 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1393 1394 .scr_read = sata_fsl_scr_read, 1395 .scr_write = sata_fsl_scr_write, 1396 1397 .freeze = sata_fsl_freeze, 1398 .thaw = sata_fsl_thaw, 1399 .softreset = sata_fsl_softreset, 1400 .hardreset = sata_fsl_hardreset, 1401 .pmp_softreset = sata_fsl_softreset, 1402 .error_handler = sata_fsl_error_handler, 1403 .post_internal_cmd = sata_fsl_post_internal_cmd, 1404 1405 .port_start = sata_fsl_port_start, 1406 .port_stop = sata_fsl_port_stop, 1407 1408 .host_stop = sata_fsl_host_stop, 1409 1410 .pmp_attach = sata_fsl_pmp_attach, 1411 .pmp_detach = sata_fsl_pmp_detach, 1412 }; 1413 1414 static const struct ata_port_info sata_fsl_port_info[] = { 1415 { 1416 .flags = SATA_FSL_HOST_FLAGS, 1417 .pio_mask = ATA_PIO4, 1418 .udma_mask = ATA_UDMA6, 1419 .port_ops = &sata_fsl_ops, 1420 }, 1421 }; 1422 1423 static int sata_fsl_probe(struct platform_device *ofdev) 1424 { 1425 int retval = -ENXIO; 1426 void __iomem *hcr_base = NULL; 1427 void __iomem *ssr_base = NULL; 1428 void __iomem *csr_base = NULL; 1429 struct sata_fsl_host_priv *host_priv = NULL; 1430 int irq; 1431 struct ata_host *host = NULL; 1432 u32 temp; 1433 1434 struct ata_port_info pi = sata_fsl_port_info[0]; 1435 const struct ata_port_info *ppi[] = { &pi, NULL }; 1436 1437 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n"); 1438 1439 hcr_base = of_iomap(ofdev->dev.of_node, 0); 1440 if (!hcr_base) 1441 goto error_exit_with_cleanup; 1442 1443 ssr_base = hcr_base + 0x100; 1444 csr_base = hcr_base + 0x140; 1445 1446 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { 1447 temp = ioread32(csr_base + TRANSCFG); 1448 temp = temp & 0xffffffe0; 1449 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); 1450 } 1451 1452 dev_dbg(&ofdev->dev, "@reset i/o = 0x%x\n", 1453 ioread32(csr_base + TRANSCFG)); 1454 1455 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1456 if (!host_priv) 1457 goto error_exit_with_cleanup; 1458 1459 host_priv->hcr_base = hcr_base; 1460 host_priv->ssr_base = ssr_base; 1461 host_priv->csr_base = csr_base; 1462 1463 irq = platform_get_irq(ofdev, 0); 1464 if (irq < 0) { 1465 retval = irq; 1466 goto error_exit_with_cleanup; 1467 } 1468 host_priv->irq = irq; 1469 1470 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) 1471 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; 1472 else 1473 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; 1474 1475 /* allocate host structure */ 1476 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1477 if (!host) { 1478 retval = -ENOMEM; 1479 goto error_exit_with_cleanup; 1480 } 1481 1482 /* host->iomap is not used currently */ 1483 host->private_data = host_priv; 1484 1485 /* initialize host controller */ 1486 sata_fsl_init_controller(host); 1487 1488 /* 1489 * Now, register with libATA core, this will also initiate the 1490 * device discovery process, invoking our port_start() handler & 1491 * error_handler() to execute a dummy Softreset EH session 1492 */ 1493 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1494 &sata_fsl_sht); 1495 1496 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show; 1497 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store; 1498 sysfs_attr_init(&host_priv->intr_coalescing.attr); 1499 host_priv->intr_coalescing.attr.name = "intr_coalescing"; 1500 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR; 1501 retval = device_create_file(host->dev, &host_priv->intr_coalescing); 1502 if (retval) 1503 goto error_exit_with_cleanup; 1504 1505 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show; 1506 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store; 1507 sysfs_attr_init(&host_priv->rx_watermark.attr); 1508 host_priv->rx_watermark.attr.name = "rx_watermark"; 1509 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR; 1510 retval = device_create_file(host->dev, &host_priv->rx_watermark); 1511 if (retval) { 1512 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); 1513 goto error_exit_with_cleanup; 1514 } 1515 1516 return 0; 1517 1518 error_exit_with_cleanup: 1519 1520 if (host) 1521 ata_host_detach(host); 1522 1523 if (hcr_base) 1524 iounmap(hcr_base); 1525 kfree(host_priv); 1526 1527 return retval; 1528 } 1529 1530 static int sata_fsl_remove(struct platform_device *ofdev) 1531 { 1532 struct ata_host *host = platform_get_drvdata(ofdev); 1533 struct sata_fsl_host_priv *host_priv = host->private_data; 1534 1535 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); 1536 device_remove_file(&ofdev->dev, &host_priv->rx_watermark); 1537 1538 ata_host_detach(host); 1539 1540 return 0; 1541 } 1542 1543 #ifdef CONFIG_PM_SLEEP 1544 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) 1545 { 1546 struct ata_host *host = platform_get_drvdata(op); 1547 1548 ata_host_suspend(host, state); 1549 return 0; 1550 } 1551 1552 static int sata_fsl_resume(struct platform_device *op) 1553 { 1554 struct ata_host *host = platform_get_drvdata(op); 1555 struct sata_fsl_host_priv *host_priv = host->private_data; 1556 int ret; 1557 void __iomem *hcr_base = host_priv->hcr_base; 1558 struct ata_port *ap = host->ports[0]; 1559 struct sata_fsl_port_priv *pp = ap->private_data; 1560 1561 ret = sata_fsl_init_controller(host); 1562 if (ret) { 1563 dev_err(&op->dev, "Error initializing hardware\n"); 1564 return ret; 1565 } 1566 1567 /* Recovery the CHBA register in host controller cmd register set */ 1568 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 1569 1570 iowrite32((ioread32(hcr_base + HCONTROL) 1571 | HCONTROL_ONLINE_PHY_RST 1572 | HCONTROL_SNOOP_ENABLE 1573 | HCONTROL_PMP_ATTACHED), 1574 hcr_base + HCONTROL); 1575 1576 ata_host_resume(host); 1577 return 0; 1578 } 1579 #endif 1580 1581 static const struct of_device_id fsl_sata_match[] = { 1582 { .compatible = "fsl,pq-sata", }, 1583 { .compatible = "fsl,pq-sata-v2", }, 1584 { /* sentinel */ } 1585 }; 1586 1587 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1588 1589 static struct platform_driver fsl_sata_driver = { 1590 .driver = { 1591 .name = "fsl-sata", 1592 .of_match_table = fsl_sata_match, 1593 }, 1594 .probe = sata_fsl_probe, 1595 .remove = sata_fsl_remove, 1596 #ifdef CONFIG_PM_SLEEP 1597 .suspend = sata_fsl_suspend, 1598 .resume = sata_fsl_resume, 1599 #endif 1600 }; 1601 1602 module_platform_driver(fsl_sata_driver); 1603 1604 MODULE_LICENSE("GPL"); 1605 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1606 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1607 MODULE_VERSION("1.10"); 1608