1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/ata/sata_fsl.c 4 * 5 * Freescale 3.0Gbps SATA device driver 6 * 7 * Author: Ashish Kalra <ashish.kalra@freescale.com> 8 * Li Yang <leoli@freescale.com> 9 * 10 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 18 #include <scsi/scsi_host.h> 19 #include <scsi/scsi_cmnd.h> 20 #include <linux/libata.h> 21 #include <asm/io.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 26 static unsigned int intr_coalescing_count; 27 module_param(intr_coalescing_count, int, S_IRUGO); 28 MODULE_PARM_DESC(intr_coalescing_count, 29 "INT coalescing count threshold (1..31)"); 30 31 static unsigned int intr_coalescing_ticks; 32 module_param(intr_coalescing_ticks, int, S_IRUGO); 33 MODULE_PARM_DESC(intr_coalescing_ticks, 34 "INT coalescing timer threshold in AHB ticks"); 35 /* Controller information */ 36 enum { 37 SATA_FSL_QUEUE_DEPTH = 16, 38 SATA_FSL_MAX_PRD = 63, 39 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 40 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 41 42 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 43 ATA_FLAG_PMP | ATA_FLAG_NCQ | 44 ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE), 45 46 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 47 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 48 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 49 50 /* 51 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 52 * chained indirect PRDEs up to a max count of 63. 53 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will 54 * be setup as an indirect descriptor, pointing to it's next 55 * (contiguous) PRDE. Though chained indirect PRDE arrays are 56 * supported,it will be more efficient to use a direct PRDT and 57 * a single chain/link to indirect PRDE array/PRDT. 58 */ 59 60 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 61 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 62 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 63 SATA_FSL_CMD_DESC_RSRVD = 16, 64 65 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 66 SATA_FSL_CMD_DESC_SFIS_SZ + 67 SATA_FSL_CMD_DESC_ACMD_SZ + 68 SATA_FSL_CMD_DESC_RSRVD + 69 SATA_FSL_MAX_PRD * 16), 70 71 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 72 (SATA_FSL_CMD_DESC_CFIS_SZ + 73 SATA_FSL_CMD_DESC_SFIS_SZ + 74 SATA_FSL_CMD_DESC_ACMD_SZ + 75 SATA_FSL_CMD_DESC_RSRVD), 76 77 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 78 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 79 SATA_FSL_CMD_DESC_AR_SZ), 80 81 /* 82 * MPC8315 has two SATA controllers, SATA1 & SATA2 83 * (one port per controller) 84 * MPC837x has 2/4 controllers, one port per controller 85 */ 86 87 SATA_FSL_MAX_PORTS = 1, 88 89 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 90 }; 91 92 /* 93 * Interrupt Coalescing Control Register bitdefs */ 94 enum { 95 ICC_MIN_INT_COUNT_THRESHOLD = 1, 96 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1), 97 ICC_MIN_INT_TICKS_THRESHOLD = 0, 98 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1), 99 ICC_SAFE_INT_TICKS = 1, 100 }; 101 102 /* 103 * Host Controller command register set - per port 104 */ 105 enum { 106 CQ = 0, 107 CA = 8, 108 CC = 0x10, 109 CE = 0x18, 110 DE = 0x20, 111 CHBA = 0x24, 112 HSTATUS = 0x28, 113 HCONTROL = 0x2C, 114 CQPMP = 0x30, 115 SIGNATURE = 0x34, 116 ICC = 0x38, 117 118 /* 119 * Host Status Register (HStatus) bitdefs 120 */ 121 ONLINE = (1 << 31), 122 GOING_OFFLINE = (1 << 30), 123 BIST_ERR = (1 << 29), 124 CLEAR_ERROR = (1 << 27), 125 126 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 127 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 128 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 129 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 130 FATAL_ERR_DATA_OVERRUN = (1 << 12), 131 FATAL_ERR_CRC_ERR_TX = (1 << 11), 132 FATAL_ERR_CRC_ERR_RX = (1 << 10), 133 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 134 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 135 136 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 137 FATAL_ERR_PARITY_ERR_TX | 138 FATAL_ERR_PARITY_ERR_RX | 139 FATAL_ERR_DATA_UNDERRUN | 140 FATAL_ERR_DATA_OVERRUN | 141 FATAL_ERR_CRC_ERR_TX | 142 FATAL_ERR_CRC_ERR_RX | 143 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 144 145 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12), 146 INT_ON_FATAL_ERR = (1 << 5), 147 INT_ON_PHYRDY_CHG = (1 << 4), 148 149 INT_ON_SIGNATURE_UPDATE = (1 << 3), 150 INT_ON_SNOTIFY_UPDATE = (1 << 2), 151 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 152 INT_ON_CMD_COMPLETE = 1, 153 154 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | 155 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 156 157 /* 158 * Host Control Register (HControl) bitdefs 159 */ 160 HCONTROL_ONLINE_PHY_RST = (1 << 31), 161 HCONTROL_FORCE_OFFLINE = (1 << 30), 162 HCONTROL_LEGACY = (1 << 28), 163 HCONTROL_PARITY_PROT_MOD = (1 << 14), 164 HCONTROL_DPATH_PARITY = (1 << 12), 165 HCONTROL_SNOOP_ENABLE = (1 << 10), 166 HCONTROL_PMP_ATTACHED = (1 << 9), 167 HCONTROL_COPYOUT_STATFIS = (1 << 8), 168 IE_ON_FATAL_ERR = (1 << 5), 169 IE_ON_PHYRDY_CHG = (1 << 4), 170 IE_ON_SIGNATURE_UPDATE = (1 << 3), 171 IE_ON_SNOTIFY_UPDATE = (1 << 2), 172 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 173 IE_ON_CMD_COMPLETE = 1, 174 175 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 176 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | 177 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 178 179 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 180 DATA_SNOOP_ENABLE_V1 = (1 << 22), 181 DATA_SNOOP_ENABLE_V2 = (1 << 28), 182 }; 183 184 /* 185 * SATA Superset Registers 186 */ 187 enum { 188 SSTATUS = 0, 189 SERROR = 4, 190 SCONTROL = 8, 191 SNOTIFY = 0xC, 192 }; 193 194 /* 195 * Control Status Register Set 196 */ 197 enum { 198 TRANSCFG = 0, 199 TRANSSTATUS = 4, 200 LINKCFG = 8, 201 LINKCFG1 = 0xC, 202 LINKCFG2 = 0x10, 203 LINKSTATUS = 0x14, 204 LINKSTATUS1 = 0x18, 205 PHYCTRLCFG = 0x1C, 206 COMMANDSTAT = 0x20, 207 }; 208 209 /* TRANSCFG (transport-layer) configuration control */ 210 enum { 211 TRANSCFG_RX_WATER_MARK = (1 << 4), 212 }; 213 214 /* PHY (link-layer) configuration control */ 215 enum { 216 PHY_BIST_ENABLE = 0x01, 217 }; 218 219 /* 220 * Command Header Table entry, i.e, command slot 221 * 4 Dwords per command slot, command header size == 64 Dwords. 222 */ 223 struct cmdhdr_tbl_entry { 224 __le32 cda; 225 __le32 prde_fis_len; 226 __le32 ttl; 227 __le32 desc_info; 228 }; 229 230 /* 231 * Description information bitdefs 232 */ 233 enum { 234 CMD_DESC_RES = (1 << 11), 235 VENDOR_SPECIFIC_BIST = (1 << 10), 236 CMD_DESC_SNOOP_ENABLE = (1 << 9), 237 FPDMA_QUEUED_CMD = (1 << 8), 238 SRST_CMD = (1 << 7), 239 BIST = (1 << 6), 240 ATAPI_CMD = (1 << 5), 241 }; 242 243 /* 244 * Command Descriptor 245 */ 246 struct command_desc { 247 u8 cfis[8 * 4]; 248 u8 sfis[8 * 4]; 249 struct_group(cdb, 250 u8 acmd[4 * 4]; 251 u8 fill[4 * 4]; 252 ); 253 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 254 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 255 }; 256 257 /* 258 * Physical region table descriptor(PRD) 259 */ 260 261 struct prde { 262 __le32 dba; 263 u8 fill[2 * 4]; 264 __le32 ddc_and_ext; 265 }; 266 267 /* 268 * ata_port private data 269 * This is our per-port instance data. 270 */ 271 struct sata_fsl_port_priv { 272 struct cmdhdr_tbl_entry *cmdslot; 273 dma_addr_t cmdslot_paddr; 274 struct command_desc *cmdentry; 275 dma_addr_t cmdentry_paddr; 276 }; 277 278 /* 279 * ata_port->host_set private data 280 */ 281 struct sata_fsl_host_priv { 282 void __iomem *hcr_base; 283 void __iomem *ssr_base; 284 void __iomem *csr_base; 285 int irq; 286 int data_snoop; 287 struct device_attribute intr_coalescing; 288 struct device_attribute rx_watermark; 289 }; 290 291 static void fsl_sata_set_irq_coalescing(struct ata_host *host, 292 unsigned int count, unsigned int ticks) 293 { 294 struct sata_fsl_host_priv *host_priv = host->private_data; 295 void __iomem *hcr_base = host_priv->hcr_base; 296 unsigned long flags; 297 298 if (count > ICC_MAX_INT_COUNT_THRESHOLD) 299 count = ICC_MAX_INT_COUNT_THRESHOLD; 300 else if (count < ICC_MIN_INT_COUNT_THRESHOLD) 301 count = ICC_MIN_INT_COUNT_THRESHOLD; 302 303 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD) 304 ticks = ICC_MAX_INT_TICKS_THRESHOLD; 305 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) && 306 (count > ICC_MIN_INT_COUNT_THRESHOLD)) 307 ticks = ICC_SAFE_INT_TICKS; 308 309 spin_lock_irqsave(&host->lock, flags); 310 iowrite32((count << 24 | ticks), hcr_base + ICC); 311 312 intr_coalescing_count = count; 313 intr_coalescing_ticks = ticks; 314 spin_unlock_irqrestore(&host->lock, flags); 315 316 dev_dbg(host->dev, "interrupt coalescing, count = 0x%x, ticks = %x\n", 317 intr_coalescing_count, intr_coalescing_ticks); 318 dev_dbg(host->dev, "ICC register status: (hcr base: 0x%p) = 0x%x\n", 319 hcr_base, ioread32(hcr_base + ICC)); 320 } 321 322 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev, 323 struct device_attribute *attr, char *buf) 324 { 325 return sysfs_emit(buf, "%d %d\n", 326 intr_coalescing_count, intr_coalescing_ticks); 327 } 328 329 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev, 330 struct device_attribute *attr, 331 const char *buf, size_t count) 332 { 333 unsigned int coalescing_count, coalescing_ticks; 334 335 if (sscanf(buf, "%d%d", 336 &coalescing_count, 337 &coalescing_ticks) != 2) { 338 printk(KERN_ERR "fsl-sata: wrong parameter format.\n"); 339 return -EINVAL; 340 } 341 342 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev), 343 coalescing_count, coalescing_ticks); 344 345 return strlen(buf); 346 } 347 348 static ssize_t fsl_sata_rx_watermark_show(struct device *dev, 349 struct device_attribute *attr, char *buf) 350 { 351 unsigned int rx_watermark; 352 unsigned long flags; 353 struct ata_host *host = dev_get_drvdata(dev); 354 struct sata_fsl_host_priv *host_priv = host->private_data; 355 void __iomem *csr_base = host_priv->csr_base; 356 357 spin_lock_irqsave(&host->lock, flags); 358 rx_watermark = ioread32(csr_base + TRANSCFG); 359 rx_watermark &= 0x1f; 360 spin_unlock_irqrestore(&host->lock, flags); 361 362 return sysfs_emit(buf, "%d\n", rx_watermark); 363 } 364 365 static ssize_t fsl_sata_rx_watermark_store(struct device *dev, 366 struct device_attribute *attr, 367 const char *buf, size_t count) 368 { 369 unsigned int rx_watermark; 370 unsigned long flags; 371 struct ata_host *host = dev_get_drvdata(dev); 372 struct sata_fsl_host_priv *host_priv = host->private_data; 373 void __iomem *csr_base = host_priv->csr_base; 374 u32 temp; 375 376 if (sscanf(buf, "%d", &rx_watermark) != 1) { 377 printk(KERN_ERR "fsl-sata: wrong parameter format.\n"); 378 return -EINVAL; 379 } 380 381 spin_lock_irqsave(&host->lock, flags); 382 temp = ioread32(csr_base + TRANSCFG); 383 temp &= 0xffffffe0; 384 iowrite32(temp | rx_watermark, csr_base + TRANSCFG); 385 386 spin_unlock_irqrestore(&host->lock, flags); 387 return strlen(buf); 388 } 389 390 static inline unsigned int sata_fsl_tag(struct ata_port *ap, 391 unsigned int tag, 392 void __iomem *hcr_base) 393 { 394 /* We let libATA core do actual (queue) tag allocation */ 395 396 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 397 ata_port_dbg(ap, "tag %d invalid : out of range\n", tag); 398 return 0; 399 } 400 401 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 402 ata_port_dbg(ap, "tag %d invalid : in use!!\n", tag); 403 return 0; 404 } 405 406 return tag; 407 } 408 409 static void sata_fsl_setup_cmd_hdr_entry(struct ata_port *ap, 410 struct sata_fsl_port_priv *pp, 411 unsigned int tag, u32 desc_info, 412 u32 data_xfer_len, u8 num_prde, 413 u8 fis_len) 414 { 415 dma_addr_t cmd_descriptor_address; 416 417 cmd_descriptor_address = pp->cmdentry_paddr + 418 tag * SATA_FSL_CMD_DESC_SIZE; 419 420 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 421 422 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 423 pp->cmdslot[tag].prde_fis_len = 424 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 425 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 426 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 427 428 ata_port_dbg(ap, "cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 429 le32_to_cpu(pp->cmdslot[tag].cda), 430 le32_to_cpu(pp->cmdslot[tag].prde_fis_len), 431 le32_to_cpu(pp->cmdslot[tag].ttl), 432 le32_to_cpu(pp->cmdslot[tag].desc_info)); 433 } 434 435 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 436 u32 *ttl, dma_addr_t cmd_desc_paddr, 437 int data_snoop) 438 { 439 struct scatterlist *sg; 440 unsigned int num_prde = 0; 441 u32 ttl_dwords = 0; 442 443 /* 444 * NOTE : direct & indirect prdt's are contiguously allocated 445 */ 446 struct prde *prd = (struct prde *)&((struct command_desc *) 447 cmd_desc)->prdt; 448 449 struct prde *prd_ptr_to_indirect_ext = NULL; 450 unsigned indirect_ext_segment_sz = 0; 451 dma_addr_t indirect_ext_segment_paddr; 452 unsigned int si; 453 454 indirect_ext_segment_paddr = cmd_desc_paddr + 455 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 456 457 for_each_sg(qc->sg, sg, qc->n_elem, si) { 458 dma_addr_t sg_addr = sg_dma_address(sg); 459 u32 sg_len = sg_dma_len(sg); 460 461 /* warn if each s/g element is not dword aligned */ 462 if (unlikely(sg_addr & 0x03)) 463 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n", 464 (unsigned long long)sg_addr); 465 if (unlikely(sg_len & 0x03)) 466 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n", 467 sg_len); 468 469 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 470 sg_next(sg) != NULL) { 471 prd_ptr_to_indirect_ext = prd; 472 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 473 indirect_ext_segment_sz = 0; 474 ++prd; 475 ++num_prde; 476 } 477 478 ttl_dwords += sg_len; 479 prd->dba = cpu_to_le32(sg_addr); 480 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); 481 482 ++num_prde; 483 ++prd; 484 if (prd_ptr_to_indirect_ext) 485 indirect_ext_segment_sz += sg_len; 486 } 487 488 if (prd_ptr_to_indirect_ext) { 489 /* set indirect extension flag along with indirect ext. size */ 490 prd_ptr_to_indirect_ext->ddc_and_ext = 491 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 492 data_snoop | 493 (indirect_ext_segment_sz & ~0x03))); 494 } 495 496 *ttl = ttl_dwords; 497 return num_prde; 498 } 499 500 static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc) 501 { 502 struct ata_port *ap = qc->ap; 503 struct sata_fsl_port_priv *pp = ap->private_data; 504 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 505 void __iomem *hcr_base = host_priv->hcr_base; 506 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base); 507 struct command_desc *cd; 508 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 509 u32 num_prde = 0; 510 u32 ttl_dwords = 0; 511 dma_addr_t cd_paddr; 512 513 cd = (struct command_desc *)pp->cmdentry + tag; 514 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 515 516 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 517 518 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 519 if (ata_is_atapi(qc->tf.protocol)) { 520 desc_info |= ATAPI_CMD; 521 memset(&cd->cdb, 0, sizeof(cd->cdb)); 522 memcpy(&cd->cdb, qc->cdb, qc->dev->cdb_len); 523 } 524 525 if (qc->flags & ATA_QCFLAG_DMAMAP) 526 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 527 &ttl_dwords, cd_paddr, 528 host_priv->data_snoop); 529 530 if (qc->tf.protocol == ATA_PROT_NCQ) 531 desc_info |= FPDMA_QUEUED_CMD; 532 533 sata_fsl_setup_cmd_hdr_entry(ap, pp, tag, desc_info, ttl_dwords, 534 num_prde, 5); 535 536 ata_port_dbg(ap, "SATA FSL : di = 0x%x, ttl = %d, num_prde = %d\n", 537 desc_info, ttl_dwords, num_prde); 538 539 return AC_ERR_OK; 540 } 541 542 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 543 { 544 struct ata_port *ap = qc->ap; 545 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 546 void __iomem *hcr_base = host_priv->hcr_base; 547 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base); 548 549 ata_port_dbg(ap, "CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 550 ioread32(CQ + hcr_base), 551 ioread32(CA + hcr_base), 552 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 553 554 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 555 556 /* Simply queue command to the controller/device */ 557 iowrite32(1 << tag, CQ + hcr_base); 558 559 ata_port_dbg(ap, "tag=%d, CQ=0x%x, CA=0x%x\n", 560 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 561 562 ata_port_dbg(ap, "CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 563 ioread32(CE + hcr_base), 564 ioread32(DE + hcr_base), 565 ioread32(CC + hcr_base), 566 ioread32(COMMANDSTAT + host_priv->csr_base)); 567 568 return 0; 569 } 570 571 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 572 { 573 struct sata_fsl_port_priv *pp = qc->ap->private_data; 574 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 575 void __iomem *hcr_base = host_priv->hcr_base; 576 unsigned int tag = sata_fsl_tag(qc->ap, qc->hw_tag, hcr_base); 577 struct command_desc *cd; 578 579 cd = pp->cmdentry + tag; 580 581 ata_tf_from_fis(cd->sfis, &qc->result_tf); 582 return true; 583 } 584 585 static int sata_fsl_scr_write(struct ata_link *link, 586 unsigned int sc_reg_in, u32 val) 587 { 588 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 589 void __iomem *ssr_base = host_priv->ssr_base; 590 unsigned int sc_reg; 591 592 switch (sc_reg_in) { 593 case SCR_STATUS: 594 case SCR_ERROR: 595 case SCR_CONTROL: 596 case SCR_ACTIVE: 597 sc_reg = sc_reg_in; 598 break; 599 default: 600 return -EINVAL; 601 } 602 603 ata_link_dbg(link, "reg_in = %d\n", sc_reg); 604 605 iowrite32(val, ssr_base + (sc_reg * 4)); 606 return 0; 607 } 608 609 static int sata_fsl_scr_read(struct ata_link *link, 610 unsigned int sc_reg_in, u32 *val) 611 { 612 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 613 void __iomem *ssr_base = host_priv->ssr_base; 614 unsigned int sc_reg; 615 616 switch (sc_reg_in) { 617 case SCR_STATUS: 618 case SCR_ERROR: 619 case SCR_CONTROL: 620 case SCR_ACTIVE: 621 sc_reg = sc_reg_in; 622 break; 623 default: 624 return -EINVAL; 625 } 626 627 ata_link_dbg(link, "reg_in = %d\n", sc_reg); 628 629 *val = ioread32(ssr_base + (sc_reg * 4)); 630 return 0; 631 } 632 633 static void sata_fsl_freeze(struct ata_port *ap) 634 { 635 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 636 void __iomem *hcr_base = host_priv->hcr_base; 637 u32 temp; 638 639 ata_port_dbg(ap, "CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 640 ioread32(CQ + hcr_base), 641 ioread32(CA + hcr_base), 642 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 643 ata_port_dbg(ap, "CmdStat = 0x%x\n", 644 ioread32(host_priv->csr_base + COMMANDSTAT)); 645 646 /* disable interrupts on the controller/port */ 647 temp = ioread32(hcr_base + HCONTROL); 648 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 649 650 ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n", 651 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 652 } 653 654 static void sata_fsl_thaw(struct ata_port *ap) 655 { 656 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 657 void __iomem *hcr_base = host_priv->hcr_base; 658 u32 temp; 659 660 /* ack. any pending IRQs for this controller/port */ 661 temp = ioread32(hcr_base + HSTATUS); 662 663 ata_port_dbg(ap, "pending IRQs = 0x%x\n", (temp & 0x3F)); 664 665 if (temp & 0x3F) 666 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 667 668 /* enable interrupts on the controller/port */ 669 temp = ioread32(hcr_base + HCONTROL); 670 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 671 672 ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n", 673 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 674 } 675 676 static void sata_fsl_pmp_attach(struct ata_port *ap) 677 { 678 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 679 void __iomem *hcr_base = host_priv->hcr_base; 680 u32 temp; 681 682 temp = ioread32(hcr_base + HCONTROL); 683 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 684 } 685 686 static void sata_fsl_pmp_detach(struct ata_port *ap) 687 { 688 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 689 void __iomem *hcr_base = host_priv->hcr_base; 690 u32 temp; 691 692 temp = ioread32(hcr_base + HCONTROL); 693 temp &= ~HCONTROL_PMP_ATTACHED; 694 iowrite32(temp, hcr_base + HCONTROL); 695 696 /* enable interrupts on the controller/port */ 697 temp = ioread32(hcr_base + HCONTROL); 698 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 699 700 } 701 702 static int sata_fsl_port_start(struct ata_port *ap) 703 { 704 struct device *dev = ap->host->dev; 705 struct sata_fsl_port_priv *pp; 706 void *mem; 707 dma_addr_t mem_dma; 708 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 709 void __iomem *hcr_base = host_priv->hcr_base; 710 u32 temp; 711 712 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 713 if (!pp) 714 return -ENOMEM; 715 716 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 717 GFP_KERNEL); 718 if (!mem) { 719 kfree(pp); 720 return -ENOMEM; 721 } 722 723 pp->cmdslot = mem; 724 pp->cmdslot_paddr = mem_dma; 725 726 mem += SATA_FSL_CMD_SLOT_SIZE; 727 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 728 729 pp->cmdentry = mem; 730 pp->cmdentry_paddr = mem_dma; 731 732 ap->private_data = pp; 733 734 ata_port_dbg(ap, "CHBA = 0x%lx, cmdentry_phys = 0x%lx\n", 735 (unsigned long)pp->cmdslot_paddr, 736 (unsigned long)pp->cmdentry_paddr); 737 738 /* Now, update the CHBA register in host controller cmd register set */ 739 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 740 741 /* 742 * Now, we can bring the controller on-line & also initiate 743 * the COMINIT sequence, we simply return here and the boot-probing 744 * & device discovery process is re-initiated by libATA using a 745 * Softreset EH (dummy) session. Hence, boot probing and device 746 * discovey will be part of sata_fsl_softreset() callback. 747 */ 748 749 temp = ioread32(hcr_base + HCONTROL); 750 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 751 752 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 753 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 754 ata_port_dbg(ap, "CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 755 756 return 0; 757 } 758 759 static void sata_fsl_port_stop(struct ata_port *ap) 760 { 761 struct device *dev = ap->host->dev; 762 struct sata_fsl_port_priv *pp = ap->private_data; 763 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 764 void __iomem *hcr_base = host_priv->hcr_base; 765 u32 temp; 766 767 /* 768 * Force host controller to go off-line, aborting current operations 769 */ 770 temp = ioread32(hcr_base + HCONTROL); 771 temp &= ~HCONTROL_ONLINE_PHY_RST; 772 temp |= HCONTROL_FORCE_OFFLINE; 773 iowrite32(temp, hcr_base + HCONTROL); 774 775 /* Poll for controller to go offline - should happen immediately */ 776 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 777 778 ap->private_data = NULL; 779 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 780 pp->cmdslot, pp->cmdslot_paddr); 781 782 kfree(pp); 783 } 784 785 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 786 { 787 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 788 void __iomem *hcr_base = host_priv->hcr_base; 789 struct ata_taskfile tf; 790 u32 temp; 791 792 temp = ioread32(hcr_base + SIGNATURE); 793 794 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 795 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 796 797 tf.lbah = (temp >> 24) & 0xff; 798 tf.lbam = (temp >> 16) & 0xff; 799 tf.lbal = (temp >> 8) & 0xff; 800 tf.nsect = temp & 0xff; 801 802 return ata_port_classify(ap, &tf); 803 } 804 805 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, 806 unsigned long deadline) 807 { 808 struct ata_port *ap = link->ap; 809 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 810 void __iomem *hcr_base = host_priv->hcr_base; 811 u32 temp; 812 int i = 0; 813 unsigned long start_jiffies; 814 815 try_offline_again: 816 /* 817 * Force host controller to go off-line, aborting current operations 818 */ 819 temp = ioread32(hcr_base + HCONTROL); 820 temp &= ~HCONTROL_ONLINE_PHY_RST; 821 iowrite32(temp, hcr_base + HCONTROL); 822 823 /* Poll for controller to go offline */ 824 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 825 1, 500); 826 827 if (temp & ONLINE) { 828 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i); 829 830 /* 831 * Try to offline controller atleast twice 832 */ 833 i++; 834 if (i == 2) 835 goto err; 836 else 837 goto try_offline_again; 838 } 839 840 ata_port_dbg(ap, "hardreset, controller off-lined\n" 841 "HStatus = 0x%x HControl = 0x%x\n", 842 ioread32(hcr_base + HSTATUS), 843 ioread32(hcr_base + HCONTROL)); 844 845 /* 846 * PHY reset should remain asserted for atleast 1ms 847 */ 848 ata_msleep(ap, 1); 849 850 sata_set_spd(link); 851 852 /* 853 * Now, bring the host controller online again, this can take time 854 * as PHY reset and communication establishment, 1st D2H FIS and 855 * device signature update is done, on safe side assume 500ms 856 * NOTE : Host online status may be indicated immediately!! 857 */ 858 859 temp = ioread32(hcr_base + HCONTROL); 860 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 861 temp |= HCONTROL_PMP_ATTACHED; 862 iowrite32(temp, hcr_base + HCONTROL); 863 864 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); 865 866 if (!(temp & ONLINE)) { 867 ata_port_err(ap, "Hardreset failed, not on-lined\n"); 868 goto err; 869 } 870 871 ata_port_dbg(ap, "controller off-lined & on-lined\n" 872 "HStatus = 0x%x HControl = 0x%x\n", 873 ioread32(hcr_base + HSTATUS), 874 ioread32(hcr_base + HCONTROL)); 875 876 /* 877 * First, wait for the PHYRDY change to occur before waiting for 878 * the signature, and also verify if SStatus indicates device 879 * presence 880 */ 881 882 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); 883 if ((!(temp & 0x10)) || ata_link_offline(link)) { 884 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n", 885 ioread32(hcr_base + HSTATUS)); 886 *class = ATA_DEV_NONE; 887 return 0; 888 } 889 890 /* 891 * Wait for the first D2H from device,i.e,signature update notification 892 */ 893 start_jiffies = jiffies; 894 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, 895 500, jiffies_to_msecs(deadline - start_jiffies)); 896 897 if ((temp & 0xFF) != 0x18) { 898 ata_port_warn(ap, "No Signature Update\n"); 899 *class = ATA_DEV_NONE; 900 goto do_followup_srst; 901 } else { 902 ata_port_info(ap, "Signature Update detected @ %d msecs\n", 903 jiffies_to_msecs(jiffies - start_jiffies)); 904 *class = sata_fsl_dev_classify(ap); 905 return 0; 906 } 907 908 do_followup_srst: 909 /* 910 * request libATA to perform follow-up softreset 911 */ 912 return -EAGAIN; 913 914 err: 915 return -EIO; 916 } 917 918 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 919 unsigned long deadline) 920 { 921 struct ata_port *ap = link->ap; 922 struct sata_fsl_port_priv *pp = ap->private_data; 923 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 924 void __iomem *hcr_base = host_priv->hcr_base; 925 int pmp = sata_srst_pmp(link); 926 u32 temp; 927 struct ata_taskfile tf; 928 u8 *cfis; 929 u32 Serror; 930 931 if (ata_link_offline(link)) { 932 *class = ATA_DEV_NONE; 933 return 0; 934 } 935 936 /* 937 * Send a device reset (SRST) explicitly on command slot #0 938 * Check : will the command queue (reg) be cleared during offlining ?? 939 * Also we will be online only if Phy commn. has been established 940 * and device presence has been detected, therefore if we have 941 * reached here, we can send a command to the target device 942 */ 943 944 ata_tf_init(link->device, &tf); 945 cfis = (u8 *) &pp->cmdentry->cfis; 946 947 /* device reset/SRST is a control register update FIS, uses tag0 */ 948 sata_fsl_setup_cmd_hdr_entry(ap, pp, 0, 949 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 950 951 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 952 ata_tf_to_fis(&tf, pmp, 0, cfis); 953 954 ata_port_dbg(ap, "Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 955 cfis[0], cfis[1], cfis[2], cfis[3]); 956 957 /* 958 * Queue SRST command to the controller/device, ensure that no 959 * other commands are active on the controller/device 960 */ 961 962 ata_port_dbg(ap, "CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 963 ioread32(CQ + hcr_base), 964 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 965 966 iowrite32(0xFFFF, CC + hcr_base); 967 if (pmp != SATA_PMP_CTRL_PORT) 968 iowrite32(pmp, CQPMP + hcr_base); 969 iowrite32(1, CQ + hcr_base); 970 971 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); 972 if (temp & 0x1) { 973 ata_port_warn(ap, "ATA_SRST issue failed\n"); 974 975 ata_port_dbg(ap, "Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 976 ioread32(CQ + hcr_base), 977 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 978 979 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 980 981 ata_port_dbg(ap, "HStatus = 0x%x HControl = 0x%x Serror = 0x%x\n", 982 ioread32(hcr_base + HSTATUS), 983 ioread32(hcr_base + HCONTROL), 984 Serror); 985 goto err; 986 } 987 988 ata_msleep(ap, 1); 989 990 /* 991 * SATA device enters reset state after receiving a Control register 992 * FIS with SRST bit asserted and it awaits another H2D Control reg. 993 * FIS with SRST bit cleared, then the device does internal diags & 994 * initialization, followed by indicating it's initialization status 995 * using ATA signature D2H register FIS to the host controller. 996 */ 997 998 sata_fsl_setup_cmd_hdr_entry(ap, pp, 0, 999 CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 1000 0, 0, 5); 1001 1002 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 1003 ata_tf_to_fis(&tf, pmp, 0, cfis); 1004 1005 if (pmp != SATA_PMP_CTRL_PORT) 1006 iowrite32(pmp, CQPMP + hcr_base); 1007 iowrite32(1, CQ + hcr_base); 1008 ata_msleep(ap, 150); /* ?? */ 1009 1010 /* 1011 * The above command would have signalled an interrupt on command 1012 * complete, which needs special handling, by clearing the Nth 1013 * command bit of the CCreg 1014 */ 1015 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 1016 1017 *class = ATA_DEV_NONE; 1018 1019 /* Verify if SStatus indicates device presence */ 1020 if (ata_link_online(link)) { 1021 /* 1022 * if we are here, device presence has been detected, 1023 * 1st D2H FIS would have been received, but sfis in 1024 * command desc. is not updated, but signature register 1025 * would have been updated 1026 */ 1027 1028 *class = sata_fsl_dev_classify(ap); 1029 1030 ata_port_dbg(ap, "ccreg = 0x%x\n", ioread32(hcr_base + CC)); 1031 ata_port_dbg(ap, "cereg = 0x%x\n", ioread32(hcr_base + CE)); 1032 } 1033 1034 return 0; 1035 1036 err: 1037 return -EIO; 1038 } 1039 1040 static void sata_fsl_error_handler(struct ata_port *ap) 1041 { 1042 sata_pmp_error_handler(ap); 1043 } 1044 1045 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 1046 { 1047 if (qc->flags & ATA_QCFLAG_FAILED) 1048 qc->err_mask |= AC_ERR_OTHER; 1049 1050 if (qc->err_mask) { 1051 /* make DMA engine forget about the failed command */ 1052 1053 } 1054 } 1055 1056 static void sata_fsl_error_intr(struct ata_port *ap) 1057 { 1058 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1059 void __iomem *hcr_base = host_priv->hcr_base; 1060 u32 hstatus, dereg=0, cereg = 0, SError = 0; 1061 unsigned int err_mask = 0, action = 0; 1062 int freeze = 0, abort=0; 1063 struct ata_link *link = NULL; 1064 struct ata_queued_cmd *qc = NULL; 1065 struct ata_eh_info *ehi; 1066 1067 hstatus = ioread32(hcr_base + HSTATUS); 1068 cereg = ioread32(hcr_base + CE); 1069 1070 /* first, analyze and record host port events */ 1071 link = &ap->link; 1072 ehi = &link->eh_info; 1073 ata_ehi_clear_desc(ehi); 1074 1075 /* 1076 * Handle & Clear SError 1077 */ 1078 1079 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1080 if (unlikely(SError & 0xFFFF0000)) 1081 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 1082 1083 ata_port_dbg(ap, "hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 1084 hstatus, cereg, ioread32(hcr_base + DE), SError); 1085 1086 /* handle fatal errors */ 1087 if (hstatus & FATAL_ERROR_DECODE) { 1088 ehi->err_mask |= AC_ERR_ATA_BUS; 1089 ehi->action |= ATA_EH_SOFTRESET; 1090 1091 freeze = 1; 1092 } 1093 1094 /* Handle SDB FIS receive & notify update */ 1095 if (hstatus & INT_ON_SNOTIFY_UPDATE) 1096 sata_async_notification(ap); 1097 1098 /* Handle PHYRDY change notification */ 1099 if (hstatus & INT_ON_PHYRDY_CHG) { 1100 ata_port_dbg(ap, "PHYRDY change indication\n"); 1101 1102 /* Setup a soft-reset EH action */ 1103 ata_ehi_hotplugged(ehi); 1104 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1105 freeze = 1; 1106 } 1107 1108 /* handle single device errors */ 1109 if (cereg) { 1110 /* 1111 * clear the command error, also clears queue to the device 1112 * in error, and we can (re)issue commands to this device. 1113 * When a device is in error all commands queued into the 1114 * host controller and at the device are considered aborted 1115 * and the queue for that device is stopped. Now, after 1116 * clearing the device error, we can issue commands to the 1117 * device to interrogate it to find the source of the error. 1118 */ 1119 abort = 1; 1120 1121 ata_port_dbg(ap, "single device error, CE=0x%x, DE=0x%x\n", 1122 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1123 1124 /* find out the offending link and qc */ 1125 if (ap->nr_pmp_links) { 1126 unsigned int dev_num; 1127 1128 dereg = ioread32(hcr_base + DE); 1129 iowrite32(dereg, hcr_base + DE); 1130 iowrite32(cereg, hcr_base + CE); 1131 1132 dev_num = ffs(dereg) - 1; 1133 if (dev_num < ap->nr_pmp_links && dereg != 0) { 1134 link = &ap->pmp_link[dev_num]; 1135 ehi = &link->eh_info; 1136 qc = ata_qc_from_tag(ap, link->active_tag); 1137 /* 1138 * We should consider this as non fatal error, 1139 * and TF must be updated as done below. 1140 */ 1141 1142 err_mask |= AC_ERR_DEV; 1143 1144 } else { 1145 err_mask |= AC_ERR_HSM; 1146 action |= ATA_EH_HARDRESET; 1147 freeze = 1; 1148 } 1149 } else { 1150 dereg = ioread32(hcr_base + DE); 1151 iowrite32(dereg, hcr_base + DE); 1152 iowrite32(cereg, hcr_base + CE); 1153 1154 qc = ata_qc_from_tag(ap, link->active_tag); 1155 /* 1156 * We should consider this as non fatal error, 1157 * and TF must be updated as done below. 1158 */ 1159 err_mask |= AC_ERR_DEV; 1160 } 1161 } 1162 1163 /* record error info */ 1164 if (qc) 1165 qc->err_mask |= err_mask; 1166 else 1167 ehi->err_mask |= err_mask; 1168 1169 ehi->action |= action; 1170 1171 /* freeze or abort */ 1172 if (freeze) 1173 ata_port_freeze(ap); 1174 else if (abort) { 1175 if (qc) 1176 ata_link_abort(qc->dev->link); 1177 else 1178 ata_port_abort(ap); 1179 } 1180 } 1181 1182 static void sata_fsl_host_intr(struct ata_port *ap) 1183 { 1184 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1185 void __iomem *hcr_base = host_priv->hcr_base; 1186 u32 hstatus, done_mask = 0; 1187 struct ata_queued_cmd *qc; 1188 u32 SError; 1189 u32 tag; 1190 u32 status_mask = INT_ON_ERROR; 1191 1192 hstatus = ioread32(hcr_base + HSTATUS); 1193 1194 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1195 1196 /* Read command completed register */ 1197 done_mask = ioread32(hcr_base + CC); 1198 1199 /* Workaround for data length mismatch errata */ 1200 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) { 1201 ata_qc_for_each_with_internal(ap, qc, tag) { 1202 if (qc && ata_is_atapi(qc->tf.protocol)) { 1203 u32 hcontrol; 1204 /* Set HControl[27] to clear error registers */ 1205 hcontrol = ioread32(hcr_base + HCONTROL); 1206 iowrite32(hcontrol | CLEAR_ERROR, 1207 hcr_base + HCONTROL); 1208 1209 /* Clear HControl[27] */ 1210 iowrite32(hcontrol & ~CLEAR_ERROR, 1211 hcr_base + HCONTROL); 1212 1213 /* Clear SError[E] bit */ 1214 sata_fsl_scr_write(&ap->link, SCR_ERROR, 1215 SError); 1216 1217 /* Ignore fatal error and device error */ 1218 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR 1219 | INT_ON_FATAL_ERR); 1220 break; 1221 } 1222 } 1223 } 1224 1225 if (unlikely(SError & 0xFFFF0000)) { 1226 ata_port_dbg(ap, "serror @host_intr : 0x%x\n", SError); 1227 sata_fsl_error_intr(ap); 1228 } 1229 1230 if (unlikely(hstatus & status_mask)) { 1231 ata_port_dbg(ap, "error interrupt!!\n"); 1232 sata_fsl_error_intr(ap); 1233 return; 1234 } 1235 1236 ata_port_dbg(ap, "Status of all queues :\n"); 1237 ata_port_dbg(ap, "done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n", 1238 done_mask, 1239 ioread32(hcr_base + CA), 1240 ioread32(hcr_base + CE), 1241 ioread32(hcr_base + CQ), 1242 ap->qc_active); 1243 1244 if (done_mask & ap->qc_active) { 1245 int i; 1246 /* clear CC bit, this will also complete the interrupt */ 1247 iowrite32(done_mask, hcr_base + CC); 1248 1249 ata_port_dbg(ap, "Status of all queues: done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1250 done_mask, ioread32(hcr_base + CA), 1251 ioread32(hcr_base + CE)); 1252 1253 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1254 if (done_mask & (1 << i)) 1255 ata_port_dbg(ap, "completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1256 i, ioread32(hcr_base + CC), 1257 ioread32(hcr_base + CA)); 1258 } 1259 ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask); 1260 return; 1261 1262 } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) { 1263 iowrite32(1, hcr_base + CC); 1264 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1265 1266 ata_port_dbg(ap, "completing non-ncq cmd, CC=0x%x\n", 1267 ioread32(hcr_base + CC)); 1268 1269 if (qc) { 1270 ata_qc_complete(qc); 1271 } 1272 } else { 1273 /* Spurious Interrupt!! */ 1274 ata_port_dbg(ap, "spurious interrupt!!, CC = 0x%x\n", 1275 ioread32(hcr_base + CC)); 1276 iowrite32(done_mask, hcr_base + CC); 1277 return; 1278 } 1279 } 1280 1281 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1282 { 1283 struct ata_host *host = dev_instance; 1284 struct sata_fsl_host_priv *host_priv = host->private_data; 1285 void __iomem *hcr_base = host_priv->hcr_base; 1286 u32 interrupt_enables; 1287 unsigned handled = 0; 1288 struct ata_port *ap; 1289 1290 /* ack. any pending IRQs for this controller/port */ 1291 interrupt_enables = ioread32(hcr_base + HSTATUS); 1292 interrupt_enables &= 0x3F; 1293 1294 if (!interrupt_enables) 1295 return IRQ_NONE; 1296 1297 spin_lock(&host->lock); 1298 1299 /* Assuming one port per host controller */ 1300 1301 ap = host->ports[0]; 1302 if (ap) { 1303 sata_fsl_host_intr(ap); 1304 } else { 1305 dev_warn(host->dev, "interrupt on disabled port 0\n"); 1306 } 1307 1308 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1309 handled = 1; 1310 1311 spin_unlock(&host->lock); 1312 1313 return IRQ_RETVAL(handled); 1314 } 1315 1316 /* 1317 * Multiple ports are represented by multiple SATA controllers with 1318 * one port per controller 1319 */ 1320 static int sata_fsl_init_controller(struct ata_host *host) 1321 { 1322 struct sata_fsl_host_priv *host_priv = host->private_data; 1323 void __iomem *hcr_base = host_priv->hcr_base; 1324 u32 temp; 1325 1326 /* 1327 * NOTE : We cannot bring the controller online before setting 1328 * the CHBA, hence main controller initialization is done as 1329 * part of the port_start() callback 1330 */ 1331 1332 /* sata controller to operate in enterprise mode */ 1333 temp = ioread32(hcr_base + HCONTROL); 1334 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); 1335 1336 /* ack. any pending IRQs for this controller/port */ 1337 temp = ioread32(hcr_base + HSTATUS); 1338 if (temp & 0x3F) 1339 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1340 1341 /* Keep interrupts disabled on the controller */ 1342 temp = ioread32(hcr_base + HCONTROL); 1343 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1344 1345 /* Disable interrupt coalescing control(icc), for the moment */ 1346 dev_dbg(host->dev, "icc = 0x%x\n", ioread32(hcr_base + ICC)); 1347 iowrite32(0x01000000, hcr_base + ICC); 1348 1349 /* clear error registers, SError is cleared by libATA */ 1350 iowrite32(0x00000FFFF, hcr_base + CE); 1351 iowrite32(0x00000FFFF, hcr_base + DE); 1352 1353 /* 1354 * reset the number of command complete bits which will cause the 1355 * interrupt to be signaled 1356 */ 1357 fsl_sata_set_irq_coalescing(host, intr_coalescing_count, 1358 intr_coalescing_ticks); 1359 1360 /* 1361 * host controller will be brought on-line, during xx_port_start() 1362 * callback, that should also initiate the OOB, COMINIT sequence 1363 */ 1364 1365 dev_dbg(host->dev, "HStatus = 0x%x HControl = 0x%x\n", 1366 ioread32(hcr_base + HSTATUS), ioread32(hcr_base + HCONTROL)); 1367 1368 return 0; 1369 } 1370 1371 static void sata_fsl_host_stop(struct ata_host *host) 1372 { 1373 struct sata_fsl_host_priv *host_priv = host->private_data; 1374 1375 iounmap(host_priv->hcr_base); 1376 kfree(host_priv); 1377 } 1378 1379 /* 1380 * scsi mid-layer and libata interface structures 1381 */ 1382 static struct scsi_host_template sata_fsl_sht = { 1383 ATA_NCQ_SHT_QD("sata_fsl", SATA_FSL_QUEUE_DEPTH), 1384 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1385 .dma_boundary = ATA_DMA_BOUNDARY, 1386 }; 1387 1388 static struct ata_port_operations sata_fsl_ops = { 1389 .inherits = &sata_pmp_port_ops, 1390 1391 .qc_defer = ata_std_qc_defer, 1392 .qc_prep = sata_fsl_qc_prep, 1393 .qc_issue = sata_fsl_qc_issue, 1394 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1395 1396 .scr_read = sata_fsl_scr_read, 1397 .scr_write = sata_fsl_scr_write, 1398 1399 .freeze = sata_fsl_freeze, 1400 .thaw = sata_fsl_thaw, 1401 .softreset = sata_fsl_softreset, 1402 .hardreset = sata_fsl_hardreset, 1403 .pmp_softreset = sata_fsl_softreset, 1404 .error_handler = sata_fsl_error_handler, 1405 .post_internal_cmd = sata_fsl_post_internal_cmd, 1406 1407 .port_start = sata_fsl_port_start, 1408 .port_stop = sata_fsl_port_stop, 1409 1410 .host_stop = sata_fsl_host_stop, 1411 1412 .pmp_attach = sata_fsl_pmp_attach, 1413 .pmp_detach = sata_fsl_pmp_detach, 1414 }; 1415 1416 static const struct ata_port_info sata_fsl_port_info[] = { 1417 { 1418 .flags = SATA_FSL_HOST_FLAGS, 1419 .pio_mask = ATA_PIO4, 1420 .udma_mask = ATA_UDMA6, 1421 .port_ops = &sata_fsl_ops, 1422 }, 1423 }; 1424 1425 static int sata_fsl_probe(struct platform_device *ofdev) 1426 { 1427 int retval = -ENXIO; 1428 void __iomem *hcr_base = NULL; 1429 void __iomem *ssr_base = NULL; 1430 void __iomem *csr_base = NULL; 1431 struct sata_fsl_host_priv *host_priv = NULL; 1432 int irq; 1433 struct ata_host *host = NULL; 1434 u32 temp; 1435 1436 struct ata_port_info pi = sata_fsl_port_info[0]; 1437 const struct ata_port_info *ppi[] = { &pi, NULL }; 1438 1439 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n"); 1440 1441 hcr_base = of_iomap(ofdev->dev.of_node, 0); 1442 if (!hcr_base) 1443 goto error_exit_with_cleanup; 1444 1445 ssr_base = hcr_base + 0x100; 1446 csr_base = hcr_base + 0x140; 1447 1448 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { 1449 temp = ioread32(csr_base + TRANSCFG); 1450 temp = temp & 0xffffffe0; 1451 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); 1452 } 1453 1454 dev_dbg(&ofdev->dev, "@reset i/o = 0x%x\n", 1455 ioread32(csr_base + TRANSCFG)); 1456 1457 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1458 if (!host_priv) 1459 goto error_exit_with_cleanup; 1460 1461 host_priv->hcr_base = hcr_base; 1462 host_priv->ssr_base = ssr_base; 1463 host_priv->csr_base = csr_base; 1464 1465 irq = platform_get_irq(ofdev, 0); 1466 if (irq < 0) { 1467 retval = irq; 1468 goto error_exit_with_cleanup; 1469 } 1470 host_priv->irq = irq; 1471 1472 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) 1473 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; 1474 else 1475 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; 1476 1477 /* allocate host structure */ 1478 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1479 if (!host) { 1480 retval = -ENOMEM; 1481 goto error_exit_with_cleanup; 1482 } 1483 1484 /* host->iomap is not used currently */ 1485 host->private_data = host_priv; 1486 1487 /* initialize host controller */ 1488 sata_fsl_init_controller(host); 1489 1490 /* 1491 * Now, register with libATA core, this will also initiate the 1492 * device discovery process, invoking our port_start() handler & 1493 * error_handler() to execute a dummy Softreset EH session 1494 */ 1495 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1496 &sata_fsl_sht); 1497 1498 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show; 1499 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store; 1500 sysfs_attr_init(&host_priv->intr_coalescing.attr); 1501 host_priv->intr_coalescing.attr.name = "intr_coalescing"; 1502 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR; 1503 retval = device_create_file(host->dev, &host_priv->intr_coalescing); 1504 if (retval) 1505 goto error_exit_with_cleanup; 1506 1507 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show; 1508 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store; 1509 sysfs_attr_init(&host_priv->rx_watermark.attr); 1510 host_priv->rx_watermark.attr.name = "rx_watermark"; 1511 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR; 1512 retval = device_create_file(host->dev, &host_priv->rx_watermark); 1513 if (retval) { 1514 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); 1515 goto error_exit_with_cleanup; 1516 } 1517 1518 return 0; 1519 1520 error_exit_with_cleanup: 1521 1522 if (host) 1523 ata_host_detach(host); 1524 1525 if (hcr_base) 1526 iounmap(hcr_base); 1527 kfree(host_priv); 1528 1529 return retval; 1530 } 1531 1532 static int sata_fsl_remove(struct platform_device *ofdev) 1533 { 1534 struct ata_host *host = platform_get_drvdata(ofdev); 1535 struct sata_fsl_host_priv *host_priv = host->private_data; 1536 1537 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); 1538 device_remove_file(&ofdev->dev, &host_priv->rx_watermark); 1539 1540 ata_host_detach(host); 1541 1542 return 0; 1543 } 1544 1545 #ifdef CONFIG_PM_SLEEP 1546 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) 1547 { 1548 struct ata_host *host = platform_get_drvdata(op); 1549 return ata_host_suspend(host, state); 1550 } 1551 1552 static int sata_fsl_resume(struct platform_device *op) 1553 { 1554 struct ata_host *host = platform_get_drvdata(op); 1555 struct sata_fsl_host_priv *host_priv = host->private_data; 1556 int ret; 1557 void __iomem *hcr_base = host_priv->hcr_base; 1558 struct ata_port *ap = host->ports[0]; 1559 struct sata_fsl_port_priv *pp = ap->private_data; 1560 1561 ret = sata_fsl_init_controller(host); 1562 if (ret) { 1563 dev_err(&op->dev, "Error initializing hardware\n"); 1564 return ret; 1565 } 1566 1567 /* Recovery the CHBA register in host controller cmd register set */ 1568 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 1569 1570 iowrite32((ioread32(hcr_base + HCONTROL) 1571 | HCONTROL_ONLINE_PHY_RST 1572 | HCONTROL_SNOOP_ENABLE 1573 | HCONTROL_PMP_ATTACHED), 1574 hcr_base + HCONTROL); 1575 1576 ata_host_resume(host); 1577 return 0; 1578 } 1579 #endif 1580 1581 static const struct of_device_id fsl_sata_match[] = { 1582 { 1583 .compatible = "fsl,pq-sata", 1584 }, 1585 { 1586 .compatible = "fsl,pq-sata-v2", 1587 }, 1588 {}, 1589 }; 1590 1591 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1592 1593 static struct platform_driver fsl_sata_driver = { 1594 .driver = { 1595 .name = "fsl-sata", 1596 .of_match_table = fsl_sata_match, 1597 }, 1598 .probe = sata_fsl_probe, 1599 .remove = sata_fsl_remove, 1600 #ifdef CONFIG_PM_SLEEP 1601 .suspend = sata_fsl_suspend, 1602 .resume = sata_fsl_resume, 1603 #endif 1604 }; 1605 1606 module_platform_driver(fsl_sata_driver); 1607 1608 MODULE_LICENSE("GPL"); 1609 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1610 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1611 MODULE_VERSION("1.10"); 1612