1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 23 #include <scsi/scsi_host.h> 24 #include <scsi/scsi_cmnd.h> 25 #include <linux/libata.h> 26 #include <asm/io.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_platform.h> 30 31 static unsigned int intr_coalescing_count; 32 module_param(intr_coalescing_count, int, S_IRUGO); 33 MODULE_PARM_DESC(intr_coalescing_count, 34 "INT coalescing count threshold (1..31)"); 35 36 static unsigned int intr_coalescing_ticks; 37 module_param(intr_coalescing_ticks, int, S_IRUGO); 38 MODULE_PARM_DESC(intr_coalescing_ticks, 39 "INT coalescing timer threshold in AHB ticks"); 40 /* Controller information */ 41 enum { 42 SATA_FSL_QUEUE_DEPTH = 16, 43 SATA_FSL_MAX_PRD = 63, 44 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 45 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 46 47 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 48 ATA_FLAG_PMP | ATA_FLAG_NCQ | 49 ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE), 50 51 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 52 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 53 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 54 55 /* 56 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 57 * chained indirect PRDEs up to a max count of 63. 58 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will 59 * be setup as an indirect descriptor, pointing to it's next 60 * (contiguous) PRDE. Though chained indirect PRDE arrays are 61 * supported,it will be more efficient to use a direct PRDT and 62 * a single chain/link to indirect PRDE array/PRDT. 63 */ 64 65 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 66 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 67 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 68 SATA_FSL_CMD_DESC_RSRVD = 16, 69 70 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 71 SATA_FSL_CMD_DESC_SFIS_SZ + 72 SATA_FSL_CMD_DESC_ACMD_SZ + 73 SATA_FSL_CMD_DESC_RSRVD + 74 SATA_FSL_MAX_PRD * 16), 75 76 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 77 (SATA_FSL_CMD_DESC_CFIS_SZ + 78 SATA_FSL_CMD_DESC_SFIS_SZ + 79 SATA_FSL_CMD_DESC_ACMD_SZ + 80 SATA_FSL_CMD_DESC_RSRVD), 81 82 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 83 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 84 SATA_FSL_CMD_DESC_AR_SZ), 85 86 /* 87 * MPC8315 has two SATA controllers, SATA1 & SATA2 88 * (one port per controller) 89 * MPC837x has 2/4 controllers, one port per controller 90 */ 91 92 SATA_FSL_MAX_PORTS = 1, 93 94 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 95 }; 96 97 /* 98 * Interrupt Coalescing Control Register bitdefs */ 99 enum { 100 ICC_MIN_INT_COUNT_THRESHOLD = 1, 101 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1), 102 ICC_MIN_INT_TICKS_THRESHOLD = 0, 103 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1), 104 ICC_SAFE_INT_TICKS = 1, 105 }; 106 107 /* 108 * Host Controller command register set - per port 109 */ 110 enum { 111 CQ = 0, 112 CA = 8, 113 CC = 0x10, 114 CE = 0x18, 115 DE = 0x20, 116 CHBA = 0x24, 117 HSTATUS = 0x28, 118 HCONTROL = 0x2C, 119 CQPMP = 0x30, 120 SIGNATURE = 0x34, 121 ICC = 0x38, 122 123 /* 124 * Host Status Register (HStatus) bitdefs 125 */ 126 ONLINE = (1 << 31), 127 GOING_OFFLINE = (1 << 30), 128 BIST_ERR = (1 << 29), 129 CLEAR_ERROR = (1 << 27), 130 131 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 132 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 133 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 134 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 135 FATAL_ERR_DATA_OVERRUN = (1 << 12), 136 FATAL_ERR_CRC_ERR_TX = (1 << 11), 137 FATAL_ERR_CRC_ERR_RX = (1 << 10), 138 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 139 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 140 141 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 142 FATAL_ERR_PARITY_ERR_TX | 143 FATAL_ERR_PARITY_ERR_RX | 144 FATAL_ERR_DATA_UNDERRUN | 145 FATAL_ERR_DATA_OVERRUN | 146 FATAL_ERR_CRC_ERR_TX | 147 FATAL_ERR_CRC_ERR_RX | 148 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 149 150 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12), 151 INT_ON_FATAL_ERR = (1 << 5), 152 INT_ON_PHYRDY_CHG = (1 << 4), 153 154 INT_ON_SIGNATURE_UPDATE = (1 << 3), 155 INT_ON_SNOTIFY_UPDATE = (1 << 2), 156 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 157 INT_ON_CMD_COMPLETE = 1, 158 159 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | 160 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 161 162 /* 163 * Host Control Register (HControl) bitdefs 164 */ 165 HCONTROL_ONLINE_PHY_RST = (1 << 31), 166 HCONTROL_FORCE_OFFLINE = (1 << 30), 167 HCONTROL_LEGACY = (1 << 28), 168 HCONTROL_PARITY_PROT_MOD = (1 << 14), 169 HCONTROL_DPATH_PARITY = (1 << 12), 170 HCONTROL_SNOOP_ENABLE = (1 << 10), 171 HCONTROL_PMP_ATTACHED = (1 << 9), 172 HCONTROL_COPYOUT_STATFIS = (1 << 8), 173 IE_ON_FATAL_ERR = (1 << 5), 174 IE_ON_PHYRDY_CHG = (1 << 4), 175 IE_ON_SIGNATURE_UPDATE = (1 << 3), 176 IE_ON_SNOTIFY_UPDATE = (1 << 2), 177 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 178 IE_ON_CMD_COMPLETE = 1, 179 180 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 181 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | 182 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 183 184 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 185 DATA_SNOOP_ENABLE_V1 = (1 << 22), 186 DATA_SNOOP_ENABLE_V2 = (1 << 28), 187 }; 188 189 /* 190 * SATA Superset Registers 191 */ 192 enum { 193 SSTATUS = 0, 194 SERROR = 4, 195 SCONTROL = 8, 196 SNOTIFY = 0xC, 197 }; 198 199 /* 200 * Control Status Register Set 201 */ 202 enum { 203 TRANSCFG = 0, 204 TRANSSTATUS = 4, 205 LINKCFG = 8, 206 LINKCFG1 = 0xC, 207 LINKCFG2 = 0x10, 208 LINKSTATUS = 0x14, 209 LINKSTATUS1 = 0x18, 210 PHYCTRLCFG = 0x1C, 211 COMMANDSTAT = 0x20, 212 }; 213 214 /* TRANSCFG (transport-layer) configuration control */ 215 enum { 216 TRANSCFG_RX_WATER_MARK = (1 << 4), 217 }; 218 219 /* PHY (link-layer) configuration control */ 220 enum { 221 PHY_BIST_ENABLE = 0x01, 222 }; 223 224 /* 225 * Command Header Table entry, i.e, command slot 226 * 4 Dwords per command slot, command header size == 64 Dwords. 227 */ 228 struct cmdhdr_tbl_entry { 229 u32 cda; 230 u32 prde_fis_len; 231 u32 ttl; 232 u32 desc_info; 233 }; 234 235 /* 236 * Description information bitdefs 237 */ 238 enum { 239 CMD_DESC_RES = (1 << 11), 240 VENDOR_SPECIFIC_BIST = (1 << 10), 241 CMD_DESC_SNOOP_ENABLE = (1 << 9), 242 FPDMA_QUEUED_CMD = (1 << 8), 243 SRST_CMD = (1 << 7), 244 BIST = (1 << 6), 245 ATAPI_CMD = (1 << 5), 246 }; 247 248 /* 249 * Command Descriptor 250 */ 251 struct command_desc { 252 u8 cfis[8 * 4]; 253 u8 sfis[8 * 4]; 254 u8 acmd[4 * 4]; 255 u8 fill[4 * 4]; 256 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 257 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 258 }; 259 260 /* 261 * Physical region table descriptor(PRD) 262 */ 263 264 struct prde { 265 u32 dba; 266 u8 fill[2 * 4]; 267 u32 ddc_and_ext; 268 }; 269 270 /* 271 * ata_port private data 272 * This is our per-port instance data. 273 */ 274 struct sata_fsl_port_priv { 275 struct cmdhdr_tbl_entry *cmdslot; 276 dma_addr_t cmdslot_paddr; 277 struct command_desc *cmdentry; 278 dma_addr_t cmdentry_paddr; 279 }; 280 281 /* 282 * ata_port->host_set private data 283 */ 284 struct sata_fsl_host_priv { 285 void __iomem *hcr_base; 286 void __iomem *ssr_base; 287 void __iomem *csr_base; 288 int irq; 289 int data_snoop; 290 struct device_attribute intr_coalescing; 291 struct device_attribute rx_watermark; 292 }; 293 294 static void fsl_sata_set_irq_coalescing(struct ata_host *host, 295 unsigned int count, unsigned int ticks) 296 { 297 struct sata_fsl_host_priv *host_priv = host->private_data; 298 void __iomem *hcr_base = host_priv->hcr_base; 299 unsigned long flags; 300 301 if (count > ICC_MAX_INT_COUNT_THRESHOLD) 302 count = ICC_MAX_INT_COUNT_THRESHOLD; 303 else if (count < ICC_MIN_INT_COUNT_THRESHOLD) 304 count = ICC_MIN_INT_COUNT_THRESHOLD; 305 306 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD) 307 ticks = ICC_MAX_INT_TICKS_THRESHOLD; 308 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) && 309 (count > ICC_MIN_INT_COUNT_THRESHOLD)) 310 ticks = ICC_SAFE_INT_TICKS; 311 312 spin_lock_irqsave(&host->lock, flags); 313 iowrite32((count << 24 | ticks), hcr_base + ICC); 314 315 intr_coalescing_count = count; 316 intr_coalescing_ticks = ticks; 317 spin_unlock_irqrestore(&host->lock, flags); 318 319 DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n", 320 intr_coalescing_count, intr_coalescing_ticks); 321 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n", 322 hcr_base, ioread32(hcr_base + ICC)); 323 } 324 325 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev, 326 struct device_attribute *attr, char *buf) 327 { 328 return sprintf(buf, "%d %d\n", 329 intr_coalescing_count, intr_coalescing_ticks); 330 } 331 332 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev, 333 struct device_attribute *attr, 334 const char *buf, size_t count) 335 { 336 unsigned int coalescing_count, coalescing_ticks; 337 338 if (sscanf(buf, "%d%d", 339 &coalescing_count, 340 &coalescing_ticks) != 2) { 341 printk(KERN_ERR "fsl-sata: wrong parameter format.\n"); 342 return -EINVAL; 343 } 344 345 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev), 346 coalescing_count, coalescing_ticks); 347 348 return strlen(buf); 349 } 350 351 static ssize_t fsl_sata_rx_watermark_show(struct device *dev, 352 struct device_attribute *attr, char *buf) 353 { 354 unsigned int rx_watermark; 355 unsigned long flags; 356 struct ata_host *host = dev_get_drvdata(dev); 357 struct sata_fsl_host_priv *host_priv = host->private_data; 358 void __iomem *csr_base = host_priv->csr_base; 359 360 spin_lock_irqsave(&host->lock, flags); 361 rx_watermark = ioread32(csr_base + TRANSCFG); 362 rx_watermark &= 0x1f; 363 364 spin_unlock_irqrestore(&host->lock, flags); 365 return sprintf(buf, "%d\n", rx_watermark); 366 } 367 368 static ssize_t fsl_sata_rx_watermark_store(struct device *dev, 369 struct device_attribute *attr, 370 const char *buf, size_t count) 371 { 372 unsigned int rx_watermark; 373 unsigned long flags; 374 struct ata_host *host = dev_get_drvdata(dev); 375 struct sata_fsl_host_priv *host_priv = host->private_data; 376 void __iomem *csr_base = host_priv->csr_base; 377 u32 temp; 378 379 if (sscanf(buf, "%d", &rx_watermark) != 1) { 380 printk(KERN_ERR "fsl-sata: wrong parameter format.\n"); 381 return -EINVAL; 382 } 383 384 spin_lock_irqsave(&host->lock, flags); 385 temp = ioread32(csr_base + TRANSCFG); 386 temp &= 0xffffffe0; 387 iowrite32(temp | rx_watermark, csr_base + TRANSCFG); 388 389 spin_unlock_irqrestore(&host->lock, flags); 390 return strlen(buf); 391 } 392 393 static inline unsigned int sata_fsl_tag(unsigned int tag, 394 void __iomem *hcr_base) 395 { 396 /* We let libATA core do actual (queue) tag allocation */ 397 398 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 399 DPRINTK("tag %d invalid : out of range\n", tag); 400 return 0; 401 } 402 403 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 404 DPRINTK("tag %d invalid : in use!!\n", tag); 405 return 0; 406 } 407 408 return tag; 409 } 410 411 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 412 unsigned int tag, u32 desc_info, 413 u32 data_xfer_len, u8 num_prde, 414 u8 fis_len) 415 { 416 dma_addr_t cmd_descriptor_address; 417 418 cmd_descriptor_address = pp->cmdentry_paddr + 419 tag * SATA_FSL_CMD_DESC_SIZE; 420 421 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 422 423 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 424 pp->cmdslot[tag].prde_fis_len = 425 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 426 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 427 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 428 429 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 430 pp->cmdslot[tag].cda, 431 pp->cmdslot[tag].prde_fis_len, 432 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 433 434 } 435 436 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 437 u32 *ttl, dma_addr_t cmd_desc_paddr, 438 int data_snoop) 439 { 440 struct scatterlist *sg; 441 unsigned int num_prde = 0; 442 u32 ttl_dwords = 0; 443 444 /* 445 * NOTE : direct & indirect prdt's are contiguously allocated 446 */ 447 struct prde *prd = (struct prde *)&((struct command_desc *) 448 cmd_desc)->prdt; 449 450 struct prde *prd_ptr_to_indirect_ext = NULL; 451 unsigned indirect_ext_segment_sz = 0; 452 dma_addr_t indirect_ext_segment_paddr; 453 unsigned int si; 454 455 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 456 457 indirect_ext_segment_paddr = cmd_desc_paddr + 458 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 459 460 for_each_sg(qc->sg, sg, qc->n_elem, si) { 461 dma_addr_t sg_addr = sg_dma_address(sg); 462 u32 sg_len = sg_dma_len(sg); 463 464 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", 465 (unsigned long long)sg_addr, sg_len); 466 467 /* warn if each s/g element is not dword aligned */ 468 if (unlikely(sg_addr & 0x03)) 469 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n", 470 (unsigned long long)sg_addr); 471 if (unlikely(sg_len & 0x03)) 472 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n", 473 sg_len); 474 475 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 476 sg_next(sg) != NULL) { 477 VPRINTK("setting indirect prde\n"); 478 prd_ptr_to_indirect_ext = prd; 479 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 480 indirect_ext_segment_sz = 0; 481 ++prd; 482 ++num_prde; 483 } 484 485 ttl_dwords += sg_len; 486 prd->dba = cpu_to_le32(sg_addr); 487 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); 488 489 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 490 ttl_dwords, prd->dba, prd->ddc_and_ext); 491 492 ++num_prde; 493 ++prd; 494 if (prd_ptr_to_indirect_ext) 495 indirect_ext_segment_sz += sg_len; 496 } 497 498 if (prd_ptr_to_indirect_ext) { 499 /* set indirect extension flag along with indirect ext. size */ 500 prd_ptr_to_indirect_ext->ddc_and_ext = 501 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 502 data_snoop | 503 (indirect_ext_segment_sz & ~0x03))); 504 } 505 506 *ttl = ttl_dwords; 507 return num_prde; 508 } 509 510 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 511 { 512 struct ata_port *ap = qc->ap; 513 struct sata_fsl_port_priv *pp = ap->private_data; 514 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 515 void __iomem *hcr_base = host_priv->hcr_base; 516 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base); 517 struct command_desc *cd; 518 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 519 u32 num_prde = 0; 520 u32 ttl_dwords = 0; 521 dma_addr_t cd_paddr; 522 523 cd = (struct command_desc *)pp->cmdentry + tag; 524 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 525 526 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 527 528 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 529 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 530 531 if (qc->tf.protocol == ATA_PROT_NCQ) { 532 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 533 cd->cfis[3], cd->cfis[11]); 534 } 535 536 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 537 if (ata_is_atapi(qc->tf.protocol)) { 538 desc_info |= ATAPI_CMD; 539 memset((void *)&cd->acmd, 0, 32); 540 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 541 } 542 543 if (qc->flags & ATA_QCFLAG_DMAMAP) 544 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 545 &ttl_dwords, cd_paddr, 546 host_priv->data_snoop); 547 548 if (qc->tf.protocol == ATA_PROT_NCQ) 549 desc_info |= FPDMA_QUEUED_CMD; 550 551 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 552 num_prde, 5); 553 554 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 555 desc_info, ttl_dwords, num_prde); 556 } 557 558 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 559 { 560 struct ata_port *ap = qc->ap; 561 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 562 void __iomem *hcr_base = host_priv->hcr_base; 563 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base); 564 565 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 566 ioread32(CQ + hcr_base), 567 ioread32(CA + hcr_base), 568 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 569 570 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 571 572 /* Simply queue command to the controller/device */ 573 iowrite32(1 << tag, CQ + hcr_base); 574 575 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 576 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 577 578 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 579 ioread32(CE + hcr_base), 580 ioread32(DE + hcr_base), 581 ioread32(CC + hcr_base), 582 ioread32(COMMANDSTAT + host_priv->csr_base)); 583 584 return 0; 585 } 586 587 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 588 { 589 struct sata_fsl_port_priv *pp = qc->ap->private_data; 590 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 591 void __iomem *hcr_base = host_priv->hcr_base; 592 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base); 593 struct command_desc *cd; 594 595 cd = pp->cmdentry + tag; 596 597 ata_tf_from_fis(cd->sfis, &qc->result_tf); 598 return true; 599 } 600 601 static int sata_fsl_scr_write(struct ata_link *link, 602 unsigned int sc_reg_in, u32 val) 603 { 604 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 605 void __iomem *ssr_base = host_priv->ssr_base; 606 unsigned int sc_reg; 607 608 switch (sc_reg_in) { 609 case SCR_STATUS: 610 case SCR_ERROR: 611 case SCR_CONTROL: 612 case SCR_ACTIVE: 613 sc_reg = sc_reg_in; 614 break; 615 default: 616 return -EINVAL; 617 } 618 619 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 620 621 iowrite32(val, ssr_base + (sc_reg * 4)); 622 return 0; 623 } 624 625 static int sata_fsl_scr_read(struct ata_link *link, 626 unsigned int sc_reg_in, u32 *val) 627 { 628 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 629 void __iomem *ssr_base = host_priv->ssr_base; 630 unsigned int sc_reg; 631 632 switch (sc_reg_in) { 633 case SCR_STATUS: 634 case SCR_ERROR: 635 case SCR_CONTROL: 636 case SCR_ACTIVE: 637 sc_reg = sc_reg_in; 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 644 645 *val = ioread32(ssr_base + (sc_reg * 4)); 646 return 0; 647 } 648 649 static void sata_fsl_freeze(struct ata_port *ap) 650 { 651 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 652 void __iomem *hcr_base = host_priv->hcr_base; 653 u32 temp; 654 655 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 656 ioread32(CQ + hcr_base), 657 ioread32(CA + hcr_base), 658 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 659 VPRINTK("CmdStat = 0x%x\n", 660 ioread32(host_priv->csr_base + COMMANDSTAT)); 661 662 /* disable interrupts on the controller/port */ 663 temp = ioread32(hcr_base + HCONTROL); 664 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 665 666 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 667 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 668 } 669 670 static void sata_fsl_thaw(struct ata_port *ap) 671 { 672 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 673 void __iomem *hcr_base = host_priv->hcr_base; 674 u32 temp; 675 676 /* ack. any pending IRQs for this controller/port */ 677 temp = ioread32(hcr_base + HSTATUS); 678 679 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 680 681 if (temp & 0x3F) 682 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 683 684 /* enable interrupts on the controller/port */ 685 temp = ioread32(hcr_base + HCONTROL); 686 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 687 688 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 689 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 690 } 691 692 static void sata_fsl_pmp_attach(struct ata_port *ap) 693 { 694 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 695 void __iomem *hcr_base = host_priv->hcr_base; 696 u32 temp; 697 698 temp = ioread32(hcr_base + HCONTROL); 699 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 700 } 701 702 static void sata_fsl_pmp_detach(struct ata_port *ap) 703 { 704 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 705 void __iomem *hcr_base = host_priv->hcr_base; 706 u32 temp; 707 708 temp = ioread32(hcr_base + HCONTROL); 709 temp &= ~HCONTROL_PMP_ATTACHED; 710 iowrite32(temp, hcr_base + HCONTROL); 711 712 /* enable interrupts on the controller/port */ 713 temp = ioread32(hcr_base + HCONTROL); 714 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 715 716 } 717 718 static int sata_fsl_port_start(struct ata_port *ap) 719 { 720 struct device *dev = ap->host->dev; 721 struct sata_fsl_port_priv *pp; 722 void *mem; 723 dma_addr_t mem_dma; 724 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 725 void __iomem *hcr_base = host_priv->hcr_base; 726 u32 temp; 727 728 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 729 if (!pp) 730 return -ENOMEM; 731 732 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 733 GFP_KERNEL); 734 if (!mem) { 735 kfree(pp); 736 return -ENOMEM; 737 } 738 739 pp->cmdslot = mem; 740 pp->cmdslot_paddr = mem_dma; 741 742 mem += SATA_FSL_CMD_SLOT_SIZE; 743 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 744 745 pp->cmdentry = mem; 746 pp->cmdentry_paddr = mem_dma; 747 748 ap->private_data = pp; 749 750 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 751 pp->cmdslot_paddr, pp->cmdentry_paddr); 752 753 /* Now, update the CHBA register in host controller cmd register set */ 754 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 755 756 /* 757 * Now, we can bring the controller on-line & also initiate 758 * the COMINIT sequence, we simply return here and the boot-probing 759 * & device discovery process is re-initiated by libATA using a 760 * Softreset EH (dummy) session. Hence, boot probing and device 761 * discovey will be part of sata_fsl_softreset() callback. 762 */ 763 764 temp = ioread32(hcr_base + HCONTROL); 765 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 766 767 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 768 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 769 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 770 771 return 0; 772 } 773 774 static void sata_fsl_port_stop(struct ata_port *ap) 775 { 776 struct device *dev = ap->host->dev; 777 struct sata_fsl_port_priv *pp = ap->private_data; 778 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 779 void __iomem *hcr_base = host_priv->hcr_base; 780 u32 temp; 781 782 /* 783 * Force host controller to go off-line, aborting current operations 784 */ 785 temp = ioread32(hcr_base + HCONTROL); 786 temp &= ~HCONTROL_ONLINE_PHY_RST; 787 temp |= HCONTROL_FORCE_OFFLINE; 788 iowrite32(temp, hcr_base + HCONTROL); 789 790 /* Poll for controller to go offline - should happen immediately */ 791 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 792 793 ap->private_data = NULL; 794 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 795 pp->cmdslot, pp->cmdslot_paddr); 796 797 kfree(pp); 798 } 799 800 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 801 { 802 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 803 void __iomem *hcr_base = host_priv->hcr_base; 804 struct ata_taskfile tf; 805 u32 temp; 806 807 temp = ioread32(hcr_base + SIGNATURE); 808 809 VPRINTK("raw sig = 0x%x\n", temp); 810 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 811 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 812 813 tf.lbah = (temp >> 24) & 0xff; 814 tf.lbam = (temp >> 16) & 0xff; 815 tf.lbal = (temp >> 8) & 0xff; 816 tf.nsect = temp & 0xff; 817 818 return ata_dev_classify(&tf); 819 } 820 821 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, 822 unsigned long deadline) 823 { 824 struct ata_port *ap = link->ap; 825 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 826 void __iomem *hcr_base = host_priv->hcr_base; 827 u32 temp; 828 int i = 0; 829 unsigned long start_jiffies; 830 831 DPRINTK("in xx_hardreset\n"); 832 833 try_offline_again: 834 /* 835 * Force host controller to go off-line, aborting current operations 836 */ 837 temp = ioread32(hcr_base + HCONTROL); 838 temp &= ~HCONTROL_ONLINE_PHY_RST; 839 iowrite32(temp, hcr_base + HCONTROL); 840 841 /* Poll for controller to go offline */ 842 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 843 1, 500); 844 845 if (temp & ONLINE) { 846 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i); 847 848 /* 849 * Try to offline controller atleast twice 850 */ 851 i++; 852 if (i == 2) 853 goto err; 854 else 855 goto try_offline_again; 856 } 857 858 DPRINTK("hardreset, controller off-lined\n"); 859 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 860 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 861 862 /* 863 * PHY reset should remain asserted for atleast 1ms 864 */ 865 ata_msleep(ap, 1); 866 867 sata_set_spd(link); 868 869 /* 870 * Now, bring the host controller online again, this can take time 871 * as PHY reset and communication establishment, 1st D2H FIS and 872 * device signature update is done, on safe side assume 500ms 873 * NOTE : Host online status may be indicated immediately!! 874 */ 875 876 temp = ioread32(hcr_base + HCONTROL); 877 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 878 temp |= HCONTROL_PMP_ATTACHED; 879 iowrite32(temp, hcr_base + HCONTROL); 880 881 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); 882 883 if (!(temp & ONLINE)) { 884 ata_port_err(ap, "Hardreset failed, not on-lined\n"); 885 goto err; 886 } 887 888 DPRINTK("hardreset, controller off-lined & on-lined\n"); 889 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 890 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 891 892 /* 893 * First, wait for the PHYRDY change to occur before waiting for 894 * the signature, and also verify if SStatus indicates device 895 * presence 896 */ 897 898 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); 899 if ((!(temp & 0x10)) || ata_link_offline(link)) { 900 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n", 901 ioread32(hcr_base + HSTATUS)); 902 *class = ATA_DEV_NONE; 903 return 0; 904 } 905 906 /* 907 * Wait for the first D2H from device,i.e,signature update notification 908 */ 909 start_jiffies = jiffies; 910 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, 911 500, jiffies_to_msecs(deadline - start_jiffies)); 912 913 if ((temp & 0xFF) != 0x18) { 914 ata_port_warn(ap, "No Signature Update\n"); 915 *class = ATA_DEV_NONE; 916 goto do_followup_srst; 917 } else { 918 ata_port_info(ap, "Signature Update detected @ %d msecs\n", 919 jiffies_to_msecs(jiffies - start_jiffies)); 920 *class = sata_fsl_dev_classify(ap); 921 return 0; 922 } 923 924 do_followup_srst: 925 /* 926 * request libATA to perform follow-up softreset 927 */ 928 return -EAGAIN; 929 930 err: 931 return -EIO; 932 } 933 934 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 935 unsigned long deadline) 936 { 937 struct ata_port *ap = link->ap; 938 struct sata_fsl_port_priv *pp = ap->private_data; 939 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 940 void __iomem *hcr_base = host_priv->hcr_base; 941 int pmp = sata_srst_pmp(link); 942 u32 temp; 943 struct ata_taskfile tf; 944 u8 *cfis; 945 u32 Serror; 946 947 DPRINTK("in xx_softreset\n"); 948 949 if (ata_link_offline(link)) { 950 DPRINTK("PHY reports no device\n"); 951 *class = ATA_DEV_NONE; 952 return 0; 953 } 954 955 /* 956 * Send a device reset (SRST) explicitly on command slot #0 957 * Check : will the command queue (reg) be cleared during offlining ?? 958 * Also we will be online only if Phy commn. has been established 959 * and device presence has been detected, therefore if we have 960 * reached here, we can send a command to the target device 961 */ 962 963 DPRINTK("Sending SRST/device reset\n"); 964 965 ata_tf_init(link->device, &tf); 966 cfis = (u8 *) &pp->cmdentry->cfis; 967 968 /* device reset/SRST is a control register update FIS, uses tag0 */ 969 sata_fsl_setup_cmd_hdr_entry(pp, 0, 970 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 971 972 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 973 ata_tf_to_fis(&tf, pmp, 0, cfis); 974 975 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 976 cfis[0], cfis[1], cfis[2], cfis[3]); 977 978 /* 979 * Queue SRST command to the controller/device, ensure that no 980 * other commands are active on the controller/device 981 */ 982 983 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 984 ioread32(CQ + hcr_base), 985 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 986 987 iowrite32(0xFFFF, CC + hcr_base); 988 if (pmp != SATA_PMP_CTRL_PORT) 989 iowrite32(pmp, CQPMP + hcr_base); 990 iowrite32(1, CQ + hcr_base); 991 992 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); 993 if (temp & 0x1) { 994 ata_port_warn(ap, "ATA_SRST issue failed\n"); 995 996 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 997 ioread32(CQ + hcr_base), 998 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 999 1000 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 1001 1002 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1003 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1004 DPRINTK("Serror = 0x%x\n", Serror); 1005 goto err; 1006 } 1007 1008 ata_msleep(ap, 1); 1009 1010 /* 1011 * SATA device enters reset state after receiving a Control register 1012 * FIS with SRST bit asserted and it awaits another H2D Control reg. 1013 * FIS with SRST bit cleared, then the device does internal diags & 1014 * initialization, followed by indicating it's initialization status 1015 * using ATA signature D2H register FIS to the host controller. 1016 */ 1017 1018 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 1019 0, 0, 5); 1020 1021 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 1022 ata_tf_to_fis(&tf, pmp, 0, cfis); 1023 1024 if (pmp != SATA_PMP_CTRL_PORT) 1025 iowrite32(pmp, CQPMP + hcr_base); 1026 iowrite32(1, CQ + hcr_base); 1027 ata_msleep(ap, 150); /* ?? */ 1028 1029 /* 1030 * The above command would have signalled an interrupt on command 1031 * complete, which needs special handling, by clearing the Nth 1032 * command bit of the CCreg 1033 */ 1034 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 1035 1036 DPRINTK("SATA FSL : Now checking device signature\n"); 1037 1038 *class = ATA_DEV_NONE; 1039 1040 /* Verify if SStatus indicates device presence */ 1041 if (ata_link_online(link)) { 1042 /* 1043 * if we are here, device presence has been detected, 1044 * 1st D2H FIS would have been received, but sfis in 1045 * command desc. is not updated, but signature register 1046 * would have been updated 1047 */ 1048 1049 *class = sata_fsl_dev_classify(ap); 1050 1051 DPRINTK("class = %d\n", *class); 1052 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 1053 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 1054 } 1055 1056 return 0; 1057 1058 err: 1059 return -EIO; 1060 } 1061 1062 static void sata_fsl_error_handler(struct ata_port *ap) 1063 { 1064 1065 DPRINTK("in xx_error_handler\n"); 1066 sata_pmp_error_handler(ap); 1067 1068 } 1069 1070 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 1071 { 1072 if (qc->flags & ATA_QCFLAG_FAILED) 1073 qc->err_mask |= AC_ERR_OTHER; 1074 1075 if (qc->err_mask) { 1076 /* make DMA engine forget about the failed command */ 1077 1078 } 1079 } 1080 1081 static void sata_fsl_error_intr(struct ata_port *ap) 1082 { 1083 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1084 void __iomem *hcr_base = host_priv->hcr_base; 1085 u32 hstatus, dereg=0, cereg = 0, SError = 0; 1086 unsigned int err_mask = 0, action = 0; 1087 int freeze = 0, abort=0; 1088 struct ata_link *link = NULL; 1089 struct ata_queued_cmd *qc = NULL; 1090 struct ata_eh_info *ehi; 1091 1092 hstatus = ioread32(hcr_base + HSTATUS); 1093 cereg = ioread32(hcr_base + CE); 1094 1095 /* first, analyze and record host port events */ 1096 link = &ap->link; 1097 ehi = &link->eh_info; 1098 ata_ehi_clear_desc(ehi); 1099 1100 /* 1101 * Handle & Clear SError 1102 */ 1103 1104 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1105 if (unlikely(SError & 0xFFFF0000)) 1106 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 1107 1108 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 1109 hstatus, cereg, ioread32(hcr_base + DE), SError); 1110 1111 /* handle fatal errors */ 1112 if (hstatus & FATAL_ERROR_DECODE) { 1113 ehi->err_mask |= AC_ERR_ATA_BUS; 1114 ehi->action |= ATA_EH_SOFTRESET; 1115 1116 freeze = 1; 1117 } 1118 1119 /* Handle SDB FIS receive & notify update */ 1120 if (hstatus & INT_ON_SNOTIFY_UPDATE) 1121 sata_async_notification(ap); 1122 1123 /* Handle PHYRDY change notification */ 1124 if (hstatus & INT_ON_PHYRDY_CHG) { 1125 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1126 1127 /* Setup a soft-reset EH action */ 1128 ata_ehi_hotplugged(ehi); 1129 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1130 freeze = 1; 1131 } 1132 1133 /* handle single device errors */ 1134 if (cereg) { 1135 /* 1136 * clear the command error, also clears queue to the device 1137 * in error, and we can (re)issue commands to this device. 1138 * When a device is in error all commands queued into the 1139 * host controller and at the device are considered aborted 1140 * and the queue for that device is stopped. Now, after 1141 * clearing the device error, we can issue commands to the 1142 * device to interrogate it to find the source of the error. 1143 */ 1144 abort = 1; 1145 1146 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 1147 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1148 1149 /* find out the offending link and qc */ 1150 if (ap->nr_pmp_links) { 1151 unsigned int dev_num; 1152 1153 dereg = ioread32(hcr_base + DE); 1154 iowrite32(dereg, hcr_base + DE); 1155 iowrite32(cereg, hcr_base + CE); 1156 1157 dev_num = ffs(dereg) - 1; 1158 if (dev_num < ap->nr_pmp_links && dereg != 0) { 1159 link = &ap->pmp_link[dev_num]; 1160 ehi = &link->eh_info; 1161 qc = ata_qc_from_tag(ap, link->active_tag); 1162 /* 1163 * We should consider this as non fatal error, 1164 * and TF must be updated as done below. 1165 */ 1166 1167 err_mask |= AC_ERR_DEV; 1168 1169 } else { 1170 err_mask |= AC_ERR_HSM; 1171 action |= ATA_EH_HARDRESET; 1172 freeze = 1; 1173 } 1174 } else { 1175 dereg = ioread32(hcr_base + DE); 1176 iowrite32(dereg, hcr_base + DE); 1177 iowrite32(cereg, hcr_base + CE); 1178 1179 qc = ata_qc_from_tag(ap, link->active_tag); 1180 /* 1181 * We should consider this as non fatal error, 1182 * and TF must be updated as done below. 1183 */ 1184 err_mask |= AC_ERR_DEV; 1185 } 1186 } 1187 1188 /* record error info */ 1189 if (qc) 1190 qc->err_mask |= err_mask; 1191 else 1192 ehi->err_mask |= err_mask; 1193 1194 ehi->action |= action; 1195 1196 /* freeze or abort */ 1197 if (freeze) 1198 ata_port_freeze(ap); 1199 else if (abort) { 1200 if (qc) 1201 ata_link_abort(qc->dev->link); 1202 else 1203 ata_port_abort(ap); 1204 } 1205 } 1206 1207 static void sata_fsl_host_intr(struct ata_port *ap) 1208 { 1209 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1210 void __iomem *hcr_base = host_priv->hcr_base; 1211 u32 hstatus, done_mask = 0; 1212 struct ata_queued_cmd *qc; 1213 u32 SError; 1214 u32 tag; 1215 u32 status_mask = INT_ON_ERROR; 1216 1217 hstatus = ioread32(hcr_base + HSTATUS); 1218 1219 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1220 1221 /* Read command completed register */ 1222 done_mask = ioread32(hcr_base + CC); 1223 1224 /* Workaround for data length mismatch errata */ 1225 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) { 1226 ata_qc_for_each_with_internal(ap, qc, tag) { 1227 if (qc && ata_is_atapi(qc->tf.protocol)) { 1228 u32 hcontrol; 1229 /* Set HControl[27] to clear error registers */ 1230 hcontrol = ioread32(hcr_base + HCONTROL); 1231 iowrite32(hcontrol | CLEAR_ERROR, 1232 hcr_base + HCONTROL); 1233 1234 /* Clear HControl[27] */ 1235 iowrite32(hcontrol & ~CLEAR_ERROR, 1236 hcr_base + HCONTROL); 1237 1238 /* Clear SError[E] bit */ 1239 sata_fsl_scr_write(&ap->link, SCR_ERROR, 1240 SError); 1241 1242 /* Ignore fatal error and device error */ 1243 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR 1244 | INT_ON_FATAL_ERR); 1245 break; 1246 } 1247 } 1248 } 1249 1250 if (unlikely(SError & 0xFFFF0000)) { 1251 DPRINTK("serror @host_intr : 0x%x\n", SError); 1252 sata_fsl_error_intr(ap); 1253 } 1254 1255 if (unlikely(hstatus & status_mask)) { 1256 DPRINTK("error interrupt!!\n"); 1257 sata_fsl_error_intr(ap); 1258 return; 1259 } 1260 1261 VPRINTK("Status of all queues :\n"); 1262 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n", 1263 done_mask, 1264 ioread32(hcr_base + CA), 1265 ioread32(hcr_base + CE), 1266 ioread32(hcr_base + CQ), 1267 ap->qc_active); 1268 1269 if (done_mask & ap->qc_active) { 1270 int i; 1271 /* clear CC bit, this will also complete the interrupt */ 1272 iowrite32(done_mask, hcr_base + CC); 1273 1274 DPRINTK("Status of all queues :\n"); 1275 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1276 done_mask, ioread32(hcr_base + CA), 1277 ioread32(hcr_base + CE)); 1278 1279 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1280 if (done_mask & (1 << i)) 1281 DPRINTK 1282 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1283 i, ioread32(hcr_base + CC), 1284 ioread32(hcr_base + CA)); 1285 } 1286 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); 1287 return; 1288 1289 } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) { 1290 iowrite32(1, hcr_base + CC); 1291 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1292 1293 DPRINTK("completing non-ncq cmd, CC=0x%x\n", 1294 ioread32(hcr_base + CC)); 1295 1296 if (qc) { 1297 ata_qc_complete(qc); 1298 } 1299 } else { 1300 /* Spurious Interrupt!! */ 1301 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1302 ioread32(hcr_base + CC)); 1303 iowrite32(done_mask, hcr_base + CC); 1304 return; 1305 } 1306 } 1307 1308 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1309 { 1310 struct ata_host *host = dev_instance; 1311 struct sata_fsl_host_priv *host_priv = host->private_data; 1312 void __iomem *hcr_base = host_priv->hcr_base; 1313 u32 interrupt_enables; 1314 unsigned handled = 0; 1315 struct ata_port *ap; 1316 1317 /* ack. any pending IRQs for this controller/port */ 1318 interrupt_enables = ioread32(hcr_base + HSTATUS); 1319 interrupt_enables &= 0x3F; 1320 1321 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1322 1323 if (!interrupt_enables) 1324 return IRQ_NONE; 1325 1326 spin_lock(&host->lock); 1327 1328 /* Assuming one port per host controller */ 1329 1330 ap = host->ports[0]; 1331 if (ap) { 1332 sata_fsl_host_intr(ap); 1333 } else { 1334 dev_warn(host->dev, "interrupt on disabled port 0\n"); 1335 } 1336 1337 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1338 handled = 1; 1339 1340 spin_unlock(&host->lock); 1341 1342 return IRQ_RETVAL(handled); 1343 } 1344 1345 /* 1346 * Multiple ports are represented by multiple SATA controllers with 1347 * one port per controller 1348 */ 1349 static int sata_fsl_init_controller(struct ata_host *host) 1350 { 1351 struct sata_fsl_host_priv *host_priv = host->private_data; 1352 void __iomem *hcr_base = host_priv->hcr_base; 1353 u32 temp; 1354 1355 /* 1356 * NOTE : We cannot bring the controller online before setting 1357 * the CHBA, hence main controller initialization is done as 1358 * part of the port_start() callback 1359 */ 1360 1361 /* sata controller to operate in enterprise mode */ 1362 temp = ioread32(hcr_base + HCONTROL); 1363 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); 1364 1365 /* ack. any pending IRQs for this controller/port */ 1366 temp = ioread32(hcr_base + HSTATUS); 1367 if (temp & 0x3F) 1368 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1369 1370 /* Keep interrupts disabled on the controller */ 1371 temp = ioread32(hcr_base + HCONTROL); 1372 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1373 1374 /* Disable interrupt coalescing control(icc), for the moment */ 1375 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1376 iowrite32(0x01000000, hcr_base + ICC); 1377 1378 /* clear error registers, SError is cleared by libATA */ 1379 iowrite32(0x00000FFFF, hcr_base + CE); 1380 iowrite32(0x00000FFFF, hcr_base + DE); 1381 1382 /* 1383 * reset the number of command complete bits which will cause the 1384 * interrupt to be signaled 1385 */ 1386 fsl_sata_set_irq_coalescing(host, intr_coalescing_count, 1387 intr_coalescing_ticks); 1388 1389 /* 1390 * host controller will be brought on-line, during xx_port_start() 1391 * callback, that should also initiate the OOB, COMINIT sequence 1392 */ 1393 1394 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1395 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1396 1397 return 0; 1398 } 1399 1400 /* 1401 * scsi mid-layer and libata interface structures 1402 */ 1403 static struct scsi_host_template sata_fsl_sht = { 1404 ATA_NCQ_SHT("sata_fsl"), 1405 .can_queue = SATA_FSL_QUEUE_DEPTH, 1406 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1407 .dma_boundary = ATA_DMA_BOUNDARY, 1408 }; 1409 1410 static struct ata_port_operations sata_fsl_ops = { 1411 .inherits = &sata_pmp_port_ops, 1412 1413 .qc_defer = ata_std_qc_defer, 1414 .qc_prep = sata_fsl_qc_prep, 1415 .qc_issue = sata_fsl_qc_issue, 1416 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1417 1418 .scr_read = sata_fsl_scr_read, 1419 .scr_write = sata_fsl_scr_write, 1420 1421 .freeze = sata_fsl_freeze, 1422 .thaw = sata_fsl_thaw, 1423 .softreset = sata_fsl_softreset, 1424 .hardreset = sata_fsl_hardreset, 1425 .pmp_softreset = sata_fsl_softreset, 1426 .error_handler = sata_fsl_error_handler, 1427 .post_internal_cmd = sata_fsl_post_internal_cmd, 1428 1429 .port_start = sata_fsl_port_start, 1430 .port_stop = sata_fsl_port_stop, 1431 1432 .pmp_attach = sata_fsl_pmp_attach, 1433 .pmp_detach = sata_fsl_pmp_detach, 1434 }; 1435 1436 static const struct ata_port_info sata_fsl_port_info[] = { 1437 { 1438 .flags = SATA_FSL_HOST_FLAGS, 1439 .pio_mask = ATA_PIO4, 1440 .udma_mask = ATA_UDMA6, 1441 .port_ops = &sata_fsl_ops, 1442 }, 1443 }; 1444 1445 static int sata_fsl_probe(struct platform_device *ofdev) 1446 { 1447 int retval = -ENXIO; 1448 void __iomem *hcr_base = NULL; 1449 void __iomem *ssr_base = NULL; 1450 void __iomem *csr_base = NULL; 1451 struct sata_fsl_host_priv *host_priv = NULL; 1452 int irq; 1453 struct ata_host *host = NULL; 1454 u32 temp; 1455 1456 struct ata_port_info pi = sata_fsl_port_info[0]; 1457 const struct ata_port_info *ppi[] = { &pi, NULL }; 1458 1459 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n"); 1460 1461 hcr_base = of_iomap(ofdev->dev.of_node, 0); 1462 if (!hcr_base) 1463 goto error_exit_with_cleanup; 1464 1465 ssr_base = hcr_base + 0x100; 1466 csr_base = hcr_base + 0x140; 1467 1468 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { 1469 temp = ioread32(csr_base + TRANSCFG); 1470 temp = temp & 0xffffffe0; 1471 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); 1472 } 1473 1474 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1475 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1476 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1477 1478 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1479 if (!host_priv) 1480 goto error_exit_with_cleanup; 1481 1482 host_priv->hcr_base = hcr_base; 1483 host_priv->ssr_base = ssr_base; 1484 host_priv->csr_base = csr_base; 1485 1486 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1487 if (!irq) { 1488 dev_err(&ofdev->dev, "invalid irq from platform\n"); 1489 goto error_exit_with_cleanup; 1490 } 1491 host_priv->irq = irq; 1492 1493 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) 1494 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; 1495 else 1496 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; 1497 1498 /* allocate host structure */ 1499 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1500 if (!host) { 1501 retval = -ENOMEM; 1502 goto error_exit_with_cleanup; 1503 } 1504 1505 /* host->iomap is not used currently */ 1506 host->private_data = host_priv; 1507 1508 /* initialize host controller */ 1509 sata_fsl_init_controller(host); 1510 1511 /* 1512 * Now, register with libATA core, this will also initiate the 1513 * device discovery process, invoking our port_start() handler & 1514 * error_handler() to execute a dummy Softreset EH session 1515 */ 1516 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1517 &sata_fsl_sht); 1518 1519 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show; 1520 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store; 1521 sysfs_attr_init(&host_priv->intr_coalescing.attr); 1522 host_priv->intr_coalescing.attr.name = "intr_coalescing"; 1523 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR; 1524 retval = device_create_file(host->dev, &host_priv->intr_coalescing); 1525 if (retval) 1526 goto error_exit_with_cleanup; 1527 1528 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show; 1529 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store; 1530 sysfs_attr_init(&host_priv->rx_watermark.attr); 1531 host_priv->rx_watermark.attr.name = "rx_watermark"; 1532 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR; 1533 retval = device_create_file(host->dev, &host_priv->rx_watermark); 1534 if (retval) { 1535 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); 1536 goto error_exit_with_cleanup; 1537 } 1538 1539 return 0; 1540 1541 error_exit_with_cleanup: 1542 1543 if (host) 1544 ata_host_detach(host); 1545 1546 if (hcr_base) 1547 iounmap(hcr_base); 1548 kfree(host_priv); 1549 1550 return retval; 1551 } 1552 1553 static int sata_fsl_remove(struct platform_device *ofdev) 1554 { 1555 struct ata_host *host = platform_get_drvdata(ofdev); 1556 struct sata_fsl_host_priv *host_priv = host->private_data; 1557 1558 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); 1559 device_remove_file(&ofdev->dev, &host_priv->rx_watermark); 1560 1561 ata_host_detach(host); 1562 1563 irq_dispose_mapping(host_priv->irq); 1564 iounmap(host_priv->hcr_base); 1565 kfree(host_priv); 1566 1567 return 0; 1568 } 1569 1570 #ifdef CONFIG_PM_SLEEP 1571 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) 1572 { 1573 struct ata_host *host = platform_get_drvdata(op); 1574 return ata_host_suspend(host, state); 1575 } 1576 1577 static int sata_fsl_resume(struct platform_device *op) 1578 { 1579 struct ata_host *host = platform_get_drvdata(op); 1580 struct sata_fsl_host_priv *host_priv = host->private_data; 1581 int ret; 1582 void __iomem *hcr_base = host_priv->hcr_base; 1583 struct ata_port *ap = host->ports[0]; 1584 struct sata_fsl_port_priv *pp = ap->private_data; 1585 1586 ret = sata_fsl_init_controller(host); 1587 if (ret) { 1588 dev_err(&op->dev, "Error initializing hardware\n"); 1589 return ret; 1590 } 1591 1592 /* Recovery the CHBA register in host controller cmd register set */ 1593 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 1594 1595 iowrite32((ioread32(hcr_base + HCONTROL) 1596 | HCONTROL_ONLINE_PHY_RST 1597 | HCONTROL_SNOOP_ENABLE 1598 | HCONTROL_PMP_ATTACHED), 1599 hcr_base + HCONTROL); 1600 1601 ata_host_resume(host); 1602 return 0; 1603 } 1604 #endif 1605 1606 static const struct of_device_id fsl_sata_match[] = { 1607 { 1608 .compatible = "fsl,pq-sata", 1609 }, 1610 { 1611 .compatible = "fsl,pq-sata-v2", 1612 }, 1613 {}, 1614 }; 1615 1616 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1617 1618 static struct platform_driver fsl_sata_driver = { 1619 .driver = { 1620 .name = "fsl-sata", 1621 .of_match_table = fsl_sata_match, 1622 }, 1623 .probe = sata_fsl_probe, 1624 .remove = sata_fsl_remove, 1625 #ifdef CONFIG_PM_SLEEP 1626 .suspend = sata_fsl_suspend, 1627 .resume = sata_fsl_resume, 1628 #endif 1629 }; 1630 1631 module_platform_driver(fsl_sata_driver); 1632 1633 MODULE_LICENSE("GPL"); 1634 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1635 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1636 MODULE_VERSION("1.10"); 1637