1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 23 #include <scsi/scsi_host.h> 24 #include <scsi/scsi_cmnd.h> 25 #include <linux/libata.h> 26 #include <asm/io.h> 27 #include <linux/of_platform.h> 28 29 /* Controller information */ 30 enum { 31 SATA_FSL_QUEUE_DEPTH = 16, 32 SATA_FSL_MAX_PRD = 63, 33 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 34 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 35 36 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 37 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 38 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN), 39 40 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 41 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 42 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 43 44 /* 45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 46 * chained indirect PRDEs upto a max count of 63. 47 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will 48 * be setup as an indirect descriptor, pointing to it's next 49 * (contiguous) PRDE. Though chained indirect PRDE arrays are 50 * supported,it will be more efficient to use a direct PRDT and 51 * a single chain/link to indirect PRDE array/PRDT. 52 */ 53 54 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 55 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 56 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 57 SATA_FSL_CMD_DESC_RSRVD = 16, 58 59 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 60 SATA_FSL_CMD_DESC_SFIS_SZ + 61 SATA_FSL_CMD_DESC_ACMD_SZ + 62 SATA_FSL_CMD_DESC_RSRVD + 63 SATA_FSL_MAX_PRD * 16), 64 65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 66 (SATA_FSL_CMD_DESC_CFIS_SZ + 67 SATA_FSL_CMD_DESC_SFIS_SZ + 68 SATA_FSL_CMD_DESC_ACMD_SZ + 69 SATA_FSL_CMD_DESC_RSRVD), 70 71 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 72 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 73 SATA_FSL_CMD_DESC_AR_SZ), 74 75 /* 76 * MPC8315 has two SATA controllers, SATA1 & SATA2 77 * (one port per controller) 78 * MPC837x has 2/4 controllers, one port per controller 79 */ 80 81 SATA_FSL_MAX_PORTS = 1, 82 83 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 84 }; 85 86 /* 87 * Host Controller command register set - per port 88 */ 89 enum { 90 CQ = 0, 91 CA = 8, 92 CC = 0x10, 93 CE = 0x18, 94 DE = 0x20, 95 CHBA = 0x24, 96 HSTATUS = 0x28, 97 HCONTROL = 0x2C, 98 CQPMP = 0x30, 99 SIGNATURE = 0x34, 100 ICC = 0x38, 101 102 /* 103 * Host Status Register (HStatus) bitdefs 104 */ 105 ONLINE = (1 << 31), 106 GOING_OFFLINE = (1 << 30), 107 BIST_ERR = (1 << 29), 108 109 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 110 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 111 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 112 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 113 FATAL_ERR_DATA_OVERRUN = (1 << 12), 114 FATAL_ERR_CRC_ERR_TX = (1 << 11), 115 FATAL_ERR_CRC_ERR_RX = (1 << 10), 116 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 117 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 118 119 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 120 FATAL_ERR_PARITY_ERR_TX | 121 FATAL_ERR_PARITY_ERR_RX | 122 FATAL_ERR_DATA_UNDERRUN | 123 FATAL_ERR_DATA_OVERRUN | 124 FATAL_ERR_CRC_ERR_TX | 125 FATAL_ERR_CRC_ERR_RX | 126 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 127 128 INT_ON_FATAL_ERR = (1 << 5), 129 INT_ON_PHYRDY_CHG = (1 << 4), 130 131 INT_ON_SIGNATURE_UPDATE = (1 << 3), 132 INT_ON_SNOTIFY_UPDATE = (1 << 2), 133 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 134 INT_ON_CMD_COMPLETE = 1, 135 136 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | 137 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 138 139 /* 140 * Host Control Register (HControl) bitdefs 141 */ 142 HCONTROL_ONLINE_PHY_RST = (1 << 31), 143 HCONTROL_FORCE_OFFLINE = (1 << 30), 144 HCONTROL_PARITY_PROT_MOD = (1 << 14), 145 HCONTROL_DPATH_PARITY = (1 << 12), 146 HCONTROL_SNOOP_ENABLE = (1 << 10), 147 HCONTROL_PMP_ATTACHED = (1 << 9), 148 HCONTROL_COPYOUT_STATFIS = (1 << 8), 149 IE_ON_FATAL_ERR = (1 << 5), 150 IE_ON_PHYRDY_CHG = (1 << 4), 151 IE_ON_SIGNATURE_UPDATE = (1 << 3), 152 IE_ON_SNOTIFY_UPDATE = (1 << 2), 153 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 154 IE_ON_CMD_COMPLETE = 1, 155 156 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 157 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | 158 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 159 160 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 161 DATA_SNOOP_ENABLE = (1 << 22), 162 }; 163 164 /* 165 * SATA Superset Registers 166 */ 167 enum { 168 SSTATUS = 0, 169 SERROR = 4, 170 SCONTROL = 8, 171 SNOTIFY = 0xC, 172 }; 173 174 /* 175 * Control Status Register Set 176 */ 177 enum { 178 TRANSCFG = 0, 179 TRANSSTATUS = 4, 180 LINKCFG = 8, 181 LINKCFG1 = 0xC, 182 LINKCFG2 = 0x10, 183 LINKSTATUS = 0x14, 184 LINKSTATUS1 = 0x18, 185 PHYCTRLCFG = 0x1C, 186 COMMANDSTAT = 0x20, 187 }; 188 189 /* PHY (link-layer) configuration control */ 190 enum { 191 PHY_BIST_ENABLE = 0x01, 192 }; 193 194 /* 195 * Command Header Table entry, i.e, command slot 196 * 4 Dwords per command slot, command header size == 64 Dwords. 197 */ 198 struct cmdhdr_tbl_entry { 199 u32 cda; 200 u32 prde_fis_len; 201 u32 ttl; 202 u32 desc_info; 203 }; 204 205 /* 206 * Description information bitdefs 207 */ 208 enum { 209 CMD_DESC_RES = (1 << 11), 210 VENDOR_SPECIFIC_BIST = (1 << 10), 211 CMD_DESC_SNOOP_ENABLE = (1 << 9), 212 FPDMA_QUEUED_CMD = (1 << 8), 213 SRST_CMD = (1 << 7), 214 BIST = (1 << 6), 215 ATAPI_CMD = (1 << 5), 216 }; 217 218 /* 219 * Command Descriptor 220 */ 221 struct command_desc { 222 u8 cfis[8 * 4]; 223 u8 sfis[8 * 4]; 224 u8 acmd[4 * 4]; 225 u8 fill[4 * 4]; 226 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 227 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 228 }; 229 230 /* 231 * Physical region table descriptor(PRD) 232 */ 233 234 struct prde { 235 u32 dba; 236 u8 fill[2 * 4]; 237 u32 ddc_and_ext; 238 }; 239 240 /* 241 * ata_port private data 242 * This is our per-port instance data. 243 */ 244 struct sata_fsl_port_priv { 245 struct cmdhdr_tbl_entry *cmdslot; 246 dma_addr_t cmdslot_paddr; 247 struct command_desc *cmdentry; 248 dma_addr_t cmdentry_paddr; 249 }; 250 251 /* 252 * ata_port->host_set private data 253 */ 254 struct sata_fsl_host_priv { 255 void __iomem *hcr_base; 256 void __iomem *ssr_base; 257 void __iomem *csr_base; 258 int irq; 259 }; 260 261 static inline unsigned int sata_fsl_tag(unsigned int tag, 262 void __iomem *hcr_base) 263 { 264 /* We let libATA core do actual (queue) tag allocation */ 265 266 /* all non NCQ/queued commands should have tag#0 */ 267 if (ata_tag_internal(tag)) { 268 DPRINTK("mapping internal cmds to tag#0\n"); 269 return 0; 270 } 271 272 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 273 DPRINTK("tag %d invalid : out of range\n", tag); 274 return 0; 275 } 276 277 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 278 DPRINTK("tag %d invalid : in use!!\n", tag); 279 return 0; 280 } 281 282 return tag; 283 } 284 285 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 286 unsigned int tag, u32 desc_info, 287 u32 data_xfer_len, u8 num_prde, 288 u8 fis_len) 289 { 290 dma_addr_t cmd_descriptor_address; 291 292 cmd_descriptor_address = pp->cmdentry_paddr + 293 tag * SATA_FSL_CMD_DESC_SIZE; 294 295 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 296 297 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 298 pp->cmdslot[tag].prde_fis_len = 299 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 300 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 301 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 302 303 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 304 pp->cmdslot[tag].cda, 305 pp->cmdslot[tag].prde_fis_len, 306 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 307 308 } 309 310 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 311 u32 *ttl, dma_addr_t cmd_desc_paddr) 312 { 313 struct scatterlist *sg; 314 unsigned int num_prde = 0; 315 u32 ttl_dwords = 0; 316 317 /* 318 * NOTE : direct & indirect prdt's are contiguously allocated 319 */ 320 struct prde *prd = (struct prde *)&((struct command_desc *) 321 cmd_desc)->prdt; 322 323 struct prde *prd_ptr_to_indirect_ext = NULL; 324 unsigned indirect_ext_segment_sz = 0; 325 dma_addr_t indirect_ext_segment_paddr; 326 unsigned int si; 327 328 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 329 330 indirect_ext_segment_paddr = cmd_desc_paddr + 331 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 332 333 for_each_sg(qc->sg, sg, qc->n_elem, si) { 334 dma_addr_t sg_addr = sg_dma_address(sg); 335 u32 sg_len = sg_dma_len(sg); 336 337 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", 338 (unsigned long long)sg_addr, sg_len); 339 340 /* warn if each s/g element is not dword aligned */ 341 if (sg_addr & 0x03) 342 ata_port_printk(qc->ap, KERN_ERR, 343 "s/g addr unaligned : 0x%llx\n", 344 (unsigned long long)sg_addr); 345 if (sg_len & 0x03) 346 ata_port_printk(qc->ap, KERN_ERR, 347 "s/g len unaligned : 0x%x\n", sg_len); 348 349 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 350 sg_next(sg) != NULL) { 351 VPRINTK("setting indirect prde\n"); 352 prd_ptr_to_indirect_ext = prd; 353 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 354 indirect_ext_segment_sz = 0; 355 ++prd; 356 ++num_prde; 357 } 358 359 ttl_dwords += sg_len; 360 prd->dba = cpu_to_le32(sg_addr); 361 prd->ddc_and_ext = 362 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); 363 364 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 365 ttl_dwords, prd->dba, prd->ddc_and_ext); 366 367 ++num_prde; 368 ++prd; 369 if (prd_ptr_to_indirect_ext) 370 indirect_ext_segment_sz += sg_len; 371 } 372 373 if (prd_ptr_to_indirect_ext) { 374 /* set indirect extension flag along with indirect ext. size */ 375 prd_ptr_to_indirect_ext->ddc_and_ext = 376 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 377 DATA_SNOOP_ENABLE | 378 (indirect_ext_segment_sz & ~0x03))); 379 } 380 381 *ttl = ttl_dwords; 382 return num_prde; 383 } 384 385 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 386 { 387 struct ata_port *ap = qc->ap; 388 struct sata_fsl_port_priv *pp = ap->private_data; 389 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 390 void __iomem *hcr_base = host_priv->hcr_base; 391 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 392 struct command_desc *cd; 393 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 394 u32 num_prde = 0; 395 u32 ttl_dwords = 0; 396 dma_addr_t cd_paddr; 397 398 cd = (struct command_desc *)pp->cmdentry + tag; 399 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 400 401 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 402 403 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 404 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 405 406 if (qc->tf.protocol == ATA_PROT_NCQ) { 407 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 408 cd->cfis[3], cd->cfis[11]); 409 } 410 411 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 412 if (ata_is_atapi(qc->tf.protocol)) { 413 desc_info |= ATAPI_CMD; 414 memset((void *)&cd->acmd, 0, 32); 415 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 416 } 417 418 if (qc->flags & ATA_QCFLAG_DMAMAP) 419 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 420 &ttl_dwords, cd_paddr); 421 422 if (qc->tf.protocol == ATA_PROT_NCQ) 423 desc_info |= FPDMA_QUEUED_CMD; 424 425 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 426 num_prde, 5); 427 428 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 429 desc_info, ttl_dwords, num_prde); 430 } 431 432 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 433 { 434 struct ata_port *ap = qc->ap; 435 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 436 void __iomem *hcr_base = host_priv->hcr_base; 437 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 438 439 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 440 ioread32(CQ + hcr_base), 441 ioread32(CA + hcr_base), 442 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 443 444 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 445 446 /* Simply queue command to the controller/device */ 447 iowrite32(1 << tag, CQ + hcr_base); 448 449 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 450 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 451 452 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 453 ioread32(CE + hcr_base), 454 ioread32(DE + hcr_base), 455 ioread32(CC + hcr_base), 456 ioread32(COMMANDSTAT + host_priv->csr_base)); 457 458 return 0; 459 } 460 461 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 462 { 463 struct sata_fsl_port_priv *pp = qc->ap->private_data; 464 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 465 void __iomem *hcr_base = host_priv->hcr_base; 466 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 467 struct command_desc *cd; 468 469 cd = pp->cmdentry + tag; 470 471 ata_tf_from_fis(cd->sfis, &qc->result_tf); 472 return true; 473 } 474 475 static int sata_fsl_scr_write(struct ata_link *link, 476 unsigned int sc_reg_in, u32 val) 477 { 478 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 479 void __iomem *ssr_base = host_priv->ssr_base; 480 unsigned int sc_reg; 481 482 switch (sc_reg_in) { 483 case SCR_STATUS: 484 case SCR_ERROR: 485 case SCR_CONTROL: 486 case SCR_ACTIVE: 487 sc_reg = sc_reg_in; 488 break; 489 default: 490 return -EINVAL; 491 } 492 493 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 494 495 iowrite32(val, ssr_base + (sc_reg * 4)); 496 return 0; 497 } 498 499 static int sata_fsl_scr_read(struct ata_link *link, 500 unsigned int sc_reg_in, u32 *val) 501 { 502 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 503 void __iomem *ssr_base = host_priv->ssr_base; 504 unsigned int sc_reg; 505 506 switch (sc_reg_in) { 507 case SCR_STATUS: 508 case SCR_ERROR: 509 case SCR_CONTROL: 510 case SCR_ACTIVE: 511 sc_reg = sc_reg_in; 512 break; 513 default: 514 return -EINVAL; 515 } 516 517 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 518 519 *val = ioread32(ssr_base + (sc_reg * 4)); 520 return 0; 521 } 522 523 static void sata_fsl_freeze(struct ata_port *ap) 524 { 525 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 526 void __iomem *hcr_base = host_priv->hcr_base; 527 u32 temp; 528 529 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 530 ioread32(CQ + hcr_base), 531 ioread32(CA + hcr_base), 532 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 533 VPRINTK("CmdStat = 0x%x\n", 534 ioread32(host_priv->csr_base + COMMANDSTAT)); 535 536 /* disable interrupts on the controller/port */ 537 temp = ioread32(hcr_base + HCONTROL); 538 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 539 540 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 541 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 542 } 543 544 static void sata_fsl_thaw(struct ata_port *ap) 545 { 546 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 547 void __iomem *hcr_base = host_priv->hcr_base; 548 u32 temp; 549 550 /* ack. any pending IRQs for this controller/port */ 551 temp = ioread32(hcr_base + HSTATUS); 552 553 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 554 555 if (temp & 0x3F) 556 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 557 558 /* enable interrupts on the controller/port */ 559 temp = ioread32(hcr_base + HCONTROL); 560 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 561 562 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 563 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 564 } 565 566 static void sata_fsl_pmp_attach(struct ata_port *ap) 567 { 568 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 569 void __iomem *hcr_base = host_priv->hcr_base; 570 u32 temp; 571 572 temp = ioread32(hcr_base + HCONTROL); 573 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 574 } 575 576 static void sata_fsl_pmp_detach(struct ata_port *ap) 577 { 578 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 579 void __iomem *hcr_base = host_priv->hcr_base; 580 u32 temp; 581 582 temp = ioread32(hcr_base + HCONTROL); 583 temp &= ~HCONTROL_PMP_ATTACHED; 584 iowrite32(temp, hcr_base + HCONTROL); 585 586 /* enable interrupts on the controller/port */ 587 temp = ioread32(hcr_base + HCONTROL); 588 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 589 590 } 591 592 static int sata_fsl_port_start(struct ata_port *ap) 593 { 594 struct device *dev = ap->host->dev; 595 struct sata_fsl_port_priv *pp; 596 void *mem; 597 dma_addr_t mem_dma; 598 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 599 void __iomem *hcr_base = host_priv->hcr_base; 600 u32 temp; 601 602 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 603 if (!pp) 604 return -ENOMEM; 605 606 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 607 GFP_KERNEL); 608 if (!mem) { 609 kfree(pp); 610 return -ENOMEM; 611 } 612 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 613 614 pp->cmdslot = mem; 615 pp->cmdslot_paddr = mem_dma; 616 617 mem += SATA_FSL_CMD_SLOT_SIZE; 618 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 619 620 pp->cmdentry = mem; 621 pp->cmdentry_paddr = mem_dma; 622 623 ap->private_data = pp; 624 625 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 626 pp->cmdslot_paddr, pp->cmdentry_paddr); 627 628 /* Now, update the CHBA register in host controller cmd register set */ 629 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 630 631 /* 632 * Now, we can bring the controller on-line & also initiate 633 * the COMINIT sequence, we simply return here and the boot-probing 634 * & device discovery process is re-initiated by libATA using a 635 * Softreset EH (dummy) session. Hence, boot probing and device 636 * discovey will be part of sata_fsl_softreset() callback. 637 */ 638 639 temp = ioread32(hcr_base + HCONTROL); 640 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 641 642 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 643 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 644 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 645 646 #ifdef CONFIG_MPC8315_DS 647 /* 648 * Workaround for 8315DS board 3gbps link-up issue, 649 * currently limit SATA port to GEN1 speed 650 */ 651 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 652 temp &= ~(0xF << 4); 653 temp |= (0x1 << 4); 654 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp); 655 656 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 657 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", 658 temp); 659 #endif 660 661 return 0; 662 } 663 664 static void sata_fsl_port_stop(struct ata_port *ap) 665 { 666 struct device *dev = ap->host->dev; 667 struct sata_fsl_port_priv *pp = ap->private_data; 668 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 669 void __iomem *hcr_base = host_priv->hcr_base; 670 u32 temp; 671 672 /* 673 * Force host controller to go off-line, aborting current operations 674 */ 675 temp = ioread32(hcr_base + HCONTROL); 676 temp &= ~HCONTROL_ONLINE_PHY_RST; 677 temp |= HCONTROL_FORCE_OFFLINE; 678 iowrite32(temp, hcr_base + HCONTROL); 679 680 /* Poll for controller to go offline - should happen immediately */ 681 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 682 683 ap->private_data = NULL; 684 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 685 pp->cmdslot, pp->cmdslot_paddr); 686 687 kfree(pp); 688 } 689 690 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 691 { 692 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 693 void __iomem *hcr_base = host_priv->hcr_base; 694 struct ata_taskfile tf; 695 u32 temp; 696 697 temp = ioread32(hcr_base + SIGNATURE); 698 699 VPRINTK("raw sig = 0x%x\n", temp); 700 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 701 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 702 703 tf.lbah = (temp >> 24) & 0xff; 704 tf.lbam = (temp >> 16) & 0xff; 705 tf.lbal = (temp >> 8) & 0xff; 706 tf.nsect = temp & 0xff; 707 708 return ata_dev_classify(&tf); 709 } 710 711 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, 712 unsigned long deadline) 713 { 714 struct ata_port *ap = link->ap; 715 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 716 void __iomem *hcr_base = host_priv->hcr_base; 717 u32 temp; 718 int i = 0; 719 unsigned long start_jiffies; 720 721 DPRINTK("in xx_hardreset\n"); 722 723 try_offline_again: 724 /* 725 * Force host controller to go off-line, aborting current operations 726 */ 727 temp = ioread32(hcr_base + HCONTROL); 728 temp &= ~HCONTROL_ONLINE_PHY_RST; 729 iowrite32(temp, hcr_base + HCONTROL); 730 731 /* Poll for controller to go offline */ 732 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); 733 734 if (temp & ONLINE) { 735 ata_port_printk(ap, KERN_ERR, 736 "Hardreset failed, not off-lined %d\n", i); 737 738 /* 739 * Try to offline controller atleast twice 740 */ 741 i++; 742 if (i == 2) 743 goto err; 744 else 745 goto try_offline_again; 746 } 747 748 DPRINTK("hardreset, controller off-lined\n"); 749 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 750 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 751 752 /* 753 * PHY reset should remain asserted for atleast 1ms 754 */ 755 msleep(1); 756 757 /* 758 * Now, bring the host controller online again, this can take time 759 * as PHY reset and communication establishment, 1st D2H FIS and 760 * device signature update is done, on safe side assume 500ms 761 * NOTE : Host online status may be indicated immediately!! 762 */ 763 764 temp = ioread32(hcr_base + HCONTROL); 765 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 766 temp |= HCONTROL_PMP_ATTACHED; 767 iowrite32(temp, hcr_base + HCONTROL); 768 769 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); 770 771 if (!(temp & ONLINE)) { 772 ata_port_printk(ap, KERN_ERR, 773 "Hardreset failed, not on-lined\n"); 774 goto err; 775 } 776 777 DPRINTK("hardreset, controller off-lined & on-lined\n"); 778 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 779 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 780 781 /* 782 * First, wait for the PHYRDY change to occur before waiting for 783 * the signature, and also verify if SStatus indicates device 784 * presence 785 */ 786 787 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); 788 if ((!(temp & 0x10)) || ata_link_offline(link)) { 789 ata_port_printk(ap, KERN_WARNING, 790 "No Device OR PHYRDY change,Hstatus = 0x%x\n", 791 ioread32(hcr_base + HSTATUS)); 792 *class = ATA_DEV_NONE; 793 return 0; 794 } 795 796 /* 797 * Wait for the first D2H from device,i.e,signature update notification 798 */ 799 start_jiffies = jiffies; 800 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, 801 500, jiffies_to_msecs(deadline - start_jiffies)); 802 803 if ((temp & 0xFF) != 0x18) { 804 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); 805 *class = ATA_DEV_NONE; 806 goto do_followup_srst; 807 } else { 808 ata_port_printk(ap, KERN_INFO, 809 "Signature Update detected @ %d msecs\n", 810 jiffies_to_msecs(jiffies - start_jiffies)); 811 *class = sata_fsl_dev_classify(ap); 812 return 0; 813 } 814 815 do_followup_srst: 816 /* 817 * request libATA to perform follow-up softreset 818 */ 819 return -EAGAIN; 820 821 err: 822 return -EIO; 823 } 824 825 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 826 unsigned long deadline) 827 { 828 struct ata_port *ap = link->ap; 829 struct sata_fsl_port_priv *pp = ap->private_data; 830 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 831 void __iomem *hcr_base = host_priv->hcr_base; 832 int pmp = sata_srst_pmp(link); 833 u32 temp; 834 struct ata_taskfile tf; 835 u8 *cfis; 836 u32 Serror; 837 838 DPRINTK("in xx_softreset\n"); 839 840 if (ata_link_offline(link)) { 841 DPRINTK("PHY reports no device\n"); 842 *class = ATA_DEV_NONE; 843 return 0; 844 } 845 846 /* 847 * Send a device reset (SRST) explicitly on command slot #0 848 * Check : will the command queue (reg) be cleared during offlining ?? 849 * Also we will be online only if Phy commn. has been established 850 * and device presence has been detected, therefore if we have 851 * reached here, we can send a command to the target device 852 */ 853 854 DPRINTK("Sending SRST/device reset\n"); 855 856 ata_tf_init(link->device, &tf); 857 cfis = (u8 *) &pp->cmdentry->cfis; 858 859 /* device reset/SRST is a control register update FIS, uses tag0 */ 860 sata_fsl_setup_cmd_hdr_entry(pp, 0, 861 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 862 863 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 864 ata_tf_to_fis(&tf, pmp, 0, cfis); 865 866 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 867 cfis[0], cfis[1], cfis[2], cfis[3]); 868 869 /* 870 * Queue SRST command to the controller/device, ensure that no 871 * other commands are active on the controller/device 872 */ 873 874 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 875 ioread32(CQ + hcr_base), 876 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 877 878 iowrite32(0xFFFF, CC + hcr_base); 879 if (pmp != SATA_PMP_CTRL_PORT) 880 iowrite32(pmp, CQPMP + hcr_base); 881 iowrite32(1, CQ + hcr_base); 882 883 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); 884 if (temp & 0x1) { 885 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); 886 887 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 888 ioread32(CQ + hcr_base), 889 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 890 891 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 892 893 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 894 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 895 DPRINTK("Serror = 0x%x\n", Serror); 896 goto err; 897 } 898 899 msleep(1); 900 901 /* 902 * SATA device enters reset state after receving a Control register 903 * FIS with SRST bit asserted and it awaits another H2D Control reg. 904 * FIS with SRST bit cleared, then the device does internal diags & 905 * initialization, followed by indicating it's initialization status 906 * using ATA signature D2H register FIS to the host controller. 907 */ 908 909 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 910 0, 0, 5); 911 912 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 913 ata_tf_to_fis(&tf, pmp, 0, cfis); 914 915 if (pmp != SATA_PMP_CTRL_PORT) 916 iowrite32(pmp, CQPMP + hcr_base); 917 iowrite32(1, CQ + hcr_base); 918 msleep(150); /* ?? */ 919 920 /* 921 * The above command would have signalled an interrupt on command 922 * complete, which needs special handling, by clearing the Nth 923 * command bit of the CCreg 924 */ 925 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 926 927 DPRINTK("SATA FSL : Now checking device signature\n"); 928 929 *class = ATA_DEV_NONE; 930 931 /* Verify if SStatus indicates device presence */ 932 if (ata_link_online(link)) { 933 /* 934 * if we are here, device presence has been detected, 935 * 1st D2H FIS would have been received, but sfis in 936 * command desc. is not updated, but signature register 937 * would have been updated 938 */ 939 940 *class = sata_fsl_dev_classify(ap); 941 942 DPRINTK("class = %d\n", *class); 943 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 944 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 945 } 946 947 return 0; 948 949 err: 950 return -EIO; 951 } 952 953 static void sata_fsl_error_handler(struct ata_port *ap) 954 { 955 956 DPRINTK("in xx_error_handler\n"); 957 sata_pmp_error_handler(ap); 958 959 } 960 961 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 962 { 963 if (qc->flags & ATA_QCFLAG_FAILED) 964 qc->err_mask |= AC_ERR_OTHER; 965 966 if (qc->err_mask) { 967 /* make DMA engine forget about the failed command */ 968 969 } 970 } 971 972 static void sata_fsl_error_intr(struct ata_port *ap) 973 { 974 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 975 void __iomem *hcr_base = host_priv->hcr_base; 976 u32 hstatus, dereg=0, cereg = 0, SError = 0; 977 unsigned int err_mask = 0, action = 0; 978 int freeze = 0, abort=0; 979 struct ata_link *link = NULL; 980 struct ata_queued_cmd *qc = NULL; 981 struct ata_eh_info *ehi; 982 983 hstatus = ioread32(hcr_base + HSTATUS); 984 cereg = ioread32(hcr_base + CE); 985 986 /* first, analyze and record host port events */ 987 link = &ap->link; 988 ehi = &link->eh_info; 989 ata_ehi_clear_desc(ehi); 990 991 /* 992 * Handle & Clear SError 993 */ 994 995 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 996 if (unlikely(SError & 0xFFFF0000)) 997 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 998 999 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 1000 hstatus, cereg, ioread32(hcr_base + DE), SError); 1001 1002 /* handle fatal errors */ 1003 if (hstatus & FATAL_ERROR_DECODE) { 1004 ehi->err_mask |= AC_ERR_ATA_BUS; 1005 ehi->action |= ATA_EH_SOFTRESET; 1006 1007 freeze = 1; 1008 } 1009 1010 /* Handle SDB FIS receive & notify update */ 1011 if (hstatus & INT_ON_SNOTIFY_UPDATE) 1012 sata_async_notification(ap); 1013 1014 /* Handle PHYRDY change notification */ 1015 if (hstatus & INT_ON_PHYRDY_CHG) { 1016 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1017 1018 /* Setup a soft-reset EH action */ 1019 ata_ehi_hotplugged(ehi); 1020 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1021 freeze = 1; 1022 } 1023 1024 /* handle single device errors */ 1025 if (cereg) { 1026 /* 1027 * clear the command error, also clears queue to the device 1028 * in error, and we can (re)issue commands to this device. 1029 * When a device is in error all commands queued into the 1030 * host controller and at the device are considered aborted 1031 * and the queue for that device is stopped. Now, after 1032 * clearing the device error, we can issue commands to the 1033 * device to interrogate it to find the source of the error. 1034 */ 1035 abort = 1; 1036 1037 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 1038 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1039 1040 /* find out the offending link and qc */ 1041 if (ap->nr_pmp_links) { 1042 dereg = ioread32(hcr_base + DE); 1043 iowrite32(dereg, hcr_base + DE); 1044 iowrite32(cereg, hcr_base + CE); 1045 1046 if (dereg < ap->nr_pmp_links) { 1047 link = &ap->pmp_link[dereg]; 1048 ehi = &link->eh_info; 1049 qc = ata_qc_from_tag(ap, link->active_tag); 1050 /* 1051 * We should consider this as non fatal error, 1052 * and TF must be updated as done below. 1053 */ 1054 1055 err_mask |= AC_ERR_DEV; 1056 1057 } else { 1058 err_mask |= AC_ERR_HSM; 1059 action |= ATA_EH_HARDRESET; 1060 freeze = 1; 1061 } 1062 } else { 1063 dereg = ioread32(hcr_base + DE); 1064 iowrite32(dereg, hcr_base + DE); 1065 iowrite32(cereg, hcr_base + CE); 1066 1067 qc = ata_qc_from_tag(ap, link->active_tag); 1068 /* 1069 * We should consider this as non fatal error, 1070 * and TF must be updated as done below. 1071 */ 1072 err_mask |= AC_ERR_DEV; 1073 } 1074 } 1075 1076 /* record error info */ 1077 if (qc) 1078 qc->err_mask |= err_mask; 1079 else 1080 ehi->err_mask |= err_mask; 1081 1082 ehi->action |= action; 1083 1084 /* freeze or abort */ 1085 if (freeze) 1086 ata_port_freeze(ap); 1087 else if (abort) { 1088 if (qc) 1089 ata_link_abort(qc->dev->link); 1090 else 1091 ata_port_abort(ap); 1092 } 1093 } 1094 1095 static void sata_fsl_host_intr(struct ata_port *ap) 1096 { 1097 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1098 void __iomem *hcr_base = host_priv->hcr_base; 1099 u32 hstatus, done_mask = 0; 1100 struct ata_queued_cmd *qc; 1101 u32 SError; 1102 1103 hstatus = ioread32(hcr_base + HSTATUS); 1104 1105 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1106 1107 if (unlikely(SError & 0xFFFF0000)) { 1108 DPRINTK("serror @host_intr : 0x%x\n", SError); 1109 sata_fsl_error_intr(ap); 1110 } 1111 1112 if (unlikely(hstatus & INT_ON_ERROR)) { 1113 DPRINTK("error interrupt!!\n"); 1114 sata_fsl_error_intr(ap); 1115 return; 1116 } 1117 1118 /* Read command completed register */ 1119 done_mask = ioread32(hcr_base + CC); 1120 1121 VPRINTK("Status of all queues :\n"); 1122 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", 1123 done_mask, 1124 ioread32(hcr_base + CA), 1125 ioread32(hcr_base + CE), 1126 ioread32(hcr_base + CQ), 1127 ap->qc_active); 1128 1129 if (done_mask & ap->qc_active) { 1130 int i; 1131 /* clear CC bit, this will also complete the interrupt */ 1132 iowrite32(done_mask, hcr_base + CC); 1133 1134 DPRINTK("Status of all queues :\n"); 1135 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1136 done_mask, ioread32(hcr_base + CA), 1137 ioread32(hcr_base + CE)); 1138 1139 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1140 if (done_mask & (1 << i)) { 1141 qc = ata_qc_from_tag(ap, i); 1142 if (qc) { 1143 ata_qc_complete(qc); 1144 } 1145 DPRINTK 1146 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1147 i, ioread32(hcr_base + CC), 1148 ioread32(hcr_base + CA)); 1149 } 1150 } 1151 return; 1152 1153 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { 1154 iowrite32(1, hcr_base + CC); 1155 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1156 1157 DPRINTK("completing non-ncq cmd, CC=0x%x\n", 1158 ioread32(hcr_base + CC)); 1159 1160 if (qc) { 1161 ata_qc_complete(qc); 1162 } 1163 } else { 1164 /* Spurious Interrupt!! */ 1165 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1166 ioread32(hcr_base + CC)); 1167 iowrite32(done_mask, hcr_base + CC); 1168 return; 1169 } 1170 } 1171 1172 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1173 { 1174 struct ata_host *host = dev_instance; 1175 struct sata_fsl_host_priv *host_priv = host->private_data; 1176 void __iomem *hcr_base = host_priv->hcr_base; 1177 u32 interrupt_enables; 1178 unsigned handled = 0; 1179 struct ata_port *ap; 1180 1181 /* ack. any pending IRQs for this controller/port */ 1182 interrupt_enables = ioread32(hcr_base + HSTATUS); 1183 interrupt_enables &= 0x3F; 1184 1185 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1186 1187 if (!interrupt_enables) 1188 return IRQ_NONE; 1189 1190 spin_lock(&host->lock); 1191 1192 /* Assuming one port per host controller */ 1193 1194 ap = host->ports[0]; 1195 if (ap) { 1196 sata_fsl_host_intr(ap); 1197 } else { 1198 dev_printk(KERN_WARNING, host->dev, 1199 "interrupt on disabled port 0\n"); 1200 } 1201 1202 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1203 handled = 1; 1204 1205 spin_unlock(&host->lock); 1206 1207 return IRQ_RETVAL(handled); 1208 } 1209 1210 /* 1211 * Multiple ports are represented by multiple SATA controllers with 1212 * one port per controller 1213 */ 1214 static int sata_fsl_init_controller(struct ata_host *host) 1215 { 1216 struct sata_fsl_host_priv *host_priv = host->private_data; 1217 void __iomem *hcr_base = host_priv->hcr_base; 1218 u32 temp; 1219 1220 /* 1221 * NOTE : We cannot bring the controller online before setting 1222 * the CHBA, hence main controller initialization is done as 1223 * part of the port_start() callback 1224 */ 1225 1226 /* ack. any pending IRQs for this controller/port */ 1227 temp = ioread32(hcr_base + HSTATUS); 1228 if (temp & 0x3F) 1229 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1230 1231 /* Keep interrupts disabled on the controller */ 1232 temp = ioread32(hcr_base + HCONTROL); 1233 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1234 1235 /* Disable interrupt coalescing control(icc), for the moment */ 1236 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1237 iowrite32(0x01000000, hcr_base + ICC); 1238 1239 /* clear error registers, SError is cleared by libATA */ 1240 iowrite32(0x00000FFFF, hcr_base + CE); 1241 iowrite32(0x00000FFFF, hcr_base + DE); 1242 1243 /* 1244 * host controller will be brought on-line, during xx_port_start() 1245 * callback, that should also initiate the OOB, COMINIT sequence 1246 */ 1247 1248 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1249 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1250 1251 return 0; 1252 } 1253 1254 /* 1255 * scsi mid-layer and libata interface structures 1256 */ 1257 static struct scsi_host_template sata_fsl_sht = { 1258 ATA_NCQ_SHT("sata_fsl"), 1259 .can_queue = SATA_FSL_QUEUE_DEPTH, 1260 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1261 .dma_boundary = ATA_DMA_BOUNDARY, 1262 }; 1263 1264 static struct ata_port_operations sata_fsl_ops = { 1265 .inherits = &sata_pmp_port_ops, 1266 1267 .qc_defer = ata_std_qc_defer, 1268 .qc_prep = sata_fsl_qc_prep, 1269 .qc_issue = sata_fsl_qc_issue, 1270 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1271 1272 .scr_read = sata_fsl_scr_read, 1273 .scr_write = sata_fsl_scr_write, 1274 1275 .freeze = sata_fsl_freeze, 1276 .thaw = sata_fsl_thaw, 1277 .softreset = sata_fsl_softreset, 1278 .hardreset = sata_fsl_hardreset, 1279 .pmp_softreset = sata_fsl_softreset, 1280 .error_handler = sata_fsl_error_handler, 1281 .post_internal_cmd = sata_fsl_post_internal_cmd, 1282 1283 .port_start = sata_fsl_port_start, 1284 .port_stop = sata_fsl_port_stop, 1285 1286 .pmp_attach = sata_fsl_pmp_attach, 1287 .pmp_detach = sata_fsl_pmp_detach, 1288 }; 1289 1290 static const struct ata_port_info sata_fsl_port_info[] = { 1291 { 1292 .flags = SATA_FSL_HOST_FLAGS, 1293 .pio_mask = ATA_PIO4, 1294 .udma_mask = ATA_UDMA6, 1295 .port_ops = &sata_fsl_ops, 1296 }, 1297 }; 1298 1299 static int sata_fsl_probe(struct platform_device *ofdev, 1300 const struct of_device_id *match) 1301 { 1302 int retval = -ENXIO; 1303 void __iomem *hcr_base = NULL; 1304 void __iomem *ssr_base = NULL; 1305 void __iomem *csr_base = NULL; 1306 struct sata_fsl_host_priv *host_priv = NULL; 1307 int irq; 1308 struct ata_host *host; 1309 1310 struct ata_port_info pi = sata_fsl_port_info[0]; 1311 const struct ata_port_info *ppi[] = { &pi, NULL }; 1312 1313 dev_printk(KERN_INFO, &ofdev->dev, 1314 "Sata FSL Platform/CSB Driver init\n"); 1315 1316 hcr_base = of_iomap(ofdev->dev.of_node, 0); 1317 if (!hcr_base) 1318 goto error_exit_with_cleanup; 1319 1320 ssr_base = hcr_base + 0x100; 1321 csr_base = hcr_base + 0x140; 1322 1323 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1324 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1325 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1326 1327 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1328 if (!host_priv) 1329 goto error_exit_with_cleanup; 1330 1331 host_priv->hcr_base = hcr_base; 1332 host_priv->ssr_base = ssr_base; 1333 host_priv->csr_base = csr_base; 1334 1335 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1336 if (irq < 0) { 1337 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); 1338 goto error_exit_with_cleanup; 1339 } 1340 host_priv->irq = irq; 1341 1342 /* allocate host structure */ 1343 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1344 1345 /* host->iomap is not used currently */ 1346 host->private_data = host_priv; 1347 1348 /* initialize host controller */ 1349 sata_fsl_init_controller(host); 1350 1351 /* 1352 * Now, register with libATA core, this will also initiate the 1353 * device discovery process, invoking our port_start() handler & 1354 * error_handler() to execute a dummy Softreset EH session 1355 */ 1356 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1357 &sata_fsl_sht); 1358 1359 dev_set_drvdata(&ofdev->dev, host); 1360 1361 return 0; 1362 1363 error_exit_with_cleanup: 1364 1365 if (hcr_base) 1366 iounmap(hcr_base); 1367 if (host_priv) 1368 kfree(host_priv); 1369 1370 return retval; 1371 } 1372 1373 static int sata_fsl_remove(struct platform_device *ofdev) 1374 { 1375 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1376 struct sata_fsl_host_priv *host_priv = host->private_data; 1377 1378 ata_host_detach(host); 1379 1380 dev_set_drvdata(&ofdev->dev, NULL); 1381 1382 irq_dispose_mapping(host_priv->irq); 1383 iounmap(host_priv->hcr_base); 1384 kfree(host_priv); 1385 1386 return 0; 1387 } 1388 1389 #ifdef CONFIG_PM 1390 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) 1391 { 1392 struct ata_host *host = dev_get_drvdata(&op->dev); 1393 return ata_host_suspend(host, state); 1394 } 1395 1396 static int sata_fsl_resume(struct platform_device *op) 1397 { 1398 struct ata_host *host = dev_get_drvdata(&op->dev); 1399 struct sata_fsl_host_priv *host_priv = host->private_data; 1400 int ret; 1401 void __iomem *hcr_base = host_priv->hcr_base; 1402 struct ata_port *ap = host->ports[0]; 1403 struct sata_fsl_port_priv *pp = ap->private_data; 1404 1405 ret = sata_fsl_init_controller(host); 1406 if (ret) { 1407 dev_printk(KERN_ERR, &op->dev, 1408 "Error initialize hardware\n"); 1409 return ret; 1410 } 1411 1412 /* Recovery the CHBA register in host controller cmd register set */ 1413 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 1414 1415 ata_host_resume(host); 1416 return 0; 1417 } 1418 #endif 1419 1420 static struct of_device_id fsl_sata_match[] = { 1421 { 1422 .compatible = "fsl,pq-sata", 1423 }, 1424 {}, 1425 }; 1426 1427 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1428 1429 static struct of_platform_driver fsl_sata_driver = { 1430 .driver = { 1431 .name = "fsl-sata", 1432 .owner = THIS_MODULE, 1433 .of_match_table = fsl_sata_match, 1434 }, 1435 .probe = sata_fsl_probe, 1436 .remove = sata_fsl_remove, 1437 #ifdef CONFIG_PM 1438 .suspend = sata_fsl_suspend, 1439 .resume = sata_fsl_resume, 1440 #endif 1441 }; 1442 1443 static int __init sata_fsl_init(void) 1444 { 1445 of_register_platform_driver(&fsl_sata_driver); 1446 return 0; 1447 } 1448 1449 static void __exit sata_fsl_exit(void) 1450 { 1451 of_unregister_platform_driver(&fsl_sata_driver); 1452 } 1453 1454 MODULE_LICENSE("GPL"); 1455 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1456 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1457 MODULE_VERSION("1.10"); 1458 1459 module_init(sata_fsl_init); 1460 module_exit(sata_fsl_exit); 1461