1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 23 #include <scsi/scsi_host.h> 24 #include <scsi/scsi_cmnd.h> 25 #include <linux/libata.h> 26 #include <asm/io.h> 27 #include <linux/of_platform.h> 28 29 static unsigned int intr_coalescing_count; 30 module_param(intr_coalescing_count, int, S_IRUGO); 31 MODULE_PARM_DESC(intr_coalescing_count, 32 "INT coalescing count threshold (1..31)"); 33 34 static unsigned int intr_coalescing_ticks; 35 module_param(intr_coalescing_ticks, int, S_IRUGO); 36 MODULE_PARM_DESC(intr_coalescing_ticks, 37 "INT coalescing timer threshold in AHB ticks"); 38 /* Controller information */ 39 enum { 40 SATA_FSL_QUEUE_DEPTH = 16, 41 SATA_FSL_MAX_PRD = 63, 42 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 43 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 44 45 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 46 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN), 47 48 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 49 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 50 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 51 52 /* 53 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 54 * chained indirect PRDEs up to a max count of 63. 55 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will 56 * be setup as an indirect descriptor, pointing to it's next 57 * (contiguous) PRDE. Though chained indirect PRDE arrays are 58 * supported,it will be more efficient to use a direct PRDT and 59 * a single chain/link to indirect PRDE array/PRDT. 60 */ 61 62 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 63 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 64 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 65 SATA_FSL_CMD_DESC_RSRVD = 16, 66 67 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 68 SATA_FSL_CMD_DESC_SFIS_SZ + 69 SATA_FSL_CMD_DESC_ACMD_SZ + 70 SATA_FSL_CMD_DESC_RSRVD + 71 SATA_FSL_MAX_PRD * 16), 72 73 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 74 (SATA_FSL_CMD_DESC_CFIS_SZ + 75 SATA_FSL_CMD_DESC_SFIS_SZ + 76 SATA_FSL_CMD_DESC_ACMD_SZ + 77 SATA_FSL_CMD_DESC_RSRVD), 78 79 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 80 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 81 SATA_FSL_CMD_DESC_AR_SZ), 82 83 /* 84 * MPC8315 has two SATA controllers, SATA1 & SATA2 85 * (one port per controller) 86 * MPC837x has 2/4 controllers, one port per controller 87 */ 88 89 SATA_FSL_MAX_PORTS = 1, 90 91 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 92 }; 93 94 /* 95 * Interrupt Coalescing Control Register bitdefs */ 96 enum { 97 ICC_MIN_INT_COUNT_THRESHOLD = 1, 98 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1), 99 ICC_MIN_INT_TICKS_THRESHOLD = 0, 100 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1), 101 ICC_SAFE_INT_TICKS = 1, 102 }; 103 104 /* 105 * Host Controller command register set - per port 106 */ 107 enum { 108 CQ = 0, 109 CA = 8, 110 CC = 0x10, 111 CE = 0x18, 112 DE = 0x20, 113 CHBA = 0x24, 114 HSTATUS = 0x28, 115 HCONTROL = 0x2C, 116 CQPMP = 0x30, 117 SIGNATURE = 0x34, 118 ICC = 0x38, 119 120 /* 121 * Host Status Register (HStatus) bitdefs 122 */ 123 ONLINE = (1 << 31), 124 GOING_OFFLINE = (1 << 30), 125 BIST_ERR = (1 << 29), 126 CLEAR_ERROR = (1 << 27), 127 128 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 129 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 130 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 131 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 132 FATAL_ERR_DATA_OVERRUN = (1 << 12), 133 FATAL_ERR_CRC_ERR_TX = (1 << 11), 134 FATAL_ERR_CRC_ERR_RX = (1 << 10), 135 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 136 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 137 138 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 139 FATAL_ERR_PARITY_ERR_TX | 140 FATAL_ERR_PARITY_ERR_RX | 141 FATAL_ERR_DATA_UNDERRUN | 142 FATAL_ERR_DATA_OVERRUN | 143 FATAL_ERR_CRC_ERR_TX | 144 FATAL_ERR_CRC_ERR_RX | 145 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 146 147 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12), 148 INT_ON_FATAL_ERR = (1 << 5), 149 INT_ON_PHYRDY_CHG = (1 << 4), 150 151 INT_ON_SIGNATURE_UPDATE = (1 << 3), 152 INT_ON_SNOTIFY_UPDATE = (1 << 2), 153 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 154 INT_ON_CMD_COMPLETE = 1, 155 156 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | 157 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 158 159 /* 160 * Host Control Register (HControl) bitdefs 161 */ 162 HCONTROL_ONLINE_PHY_RST = (1 << 31), 163 HCONTROL_FORCE_OFFLINE = (1 << 30), 164 HCONTROL_LEGACY = (1 << 28), 165 HCONTROL_PARITY_PROT_MOD = (1 << 14), 166 HCONTROL_DPATH_PARITY = (1 << 12), 167 HCONTROL_SNOOP_ENABLE = (1 << 10), 168 HCONTROL_PMP_ATTACHED = (1 << 9), 169 HCONTROL_COPYOUT_STATFIS = (1 << 8), 170 IE_ON_FATAL_ERR = (1 << 5), 171 IE_ON_PHYRDY_CHG = (1 << 4), 172 IE_ON_SIGNATURE_UPDATE = (1 << 3), 173 IE_ON_SNOTIFY_UPDATE = (1 << 2), 174 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 175 IE_ON_CMD_COMPLETE = 1, 176 177 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 178 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | 179 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 180 181 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 182 DATA_SNOOP_ENABLE_V1 = (1 << 22), 183 DATA_SNOOP_ENABLE_V2 = (1 << 28), 184 }; 185 186 /* 187 * SATA Superset Registers 188 */ 189 enum { 190 SSTATUS = 0, 191 SERROR = 4, 192 SCONTROL = 8, 193 SNOTIFY = 0xC, 194 }; 195 196 /* 197 * Control Status Register Set 198 */ 199 enum { 200 TRANSCFG = 0, 201 TRANSSTATUS = 4, 202 LINKCFG = 8, 203 LINKCFG1 = 0xC, 204 LINKCFG2 = 0x10, 205 LINKSTATUS = 0x14, 206 LINKSTATUS1 = 0x18, 207 PHYCTRLCFG = 0x1C, 208 COMMANDSTAT = 0x20, 209 }; 210 211 /* TRANSCFG (transport-layer) configuration control */ 212 enum { 213 TRANSCFG_RX_WATER_MARK = (1 << 4), 214 }; 215 216 /* PHY (link-layer) configuration control */ 217 enum { 218 PHY_BIST_ENABLE = 0x01, 219 }; 220 221 /* 222 * Command Header Table entry, i.e, command slot 223 * 4 Dwords per command slot, command header size == 64 Dwords. 224 */ 225 struct cmdhdr_tbl_entry { 226 u32 cda; 227 u32 prde_fis_len; 228 u32 ttl; 229 u32 desc_info; 230 }; 231 232 /* 233 * Description information bitdefs 234 */ 235 enum { 236 CMD_DESC_RES = (1 << 11), 237 VENDOR_SPECIFIC_BIST = (1 << 10), 238 CMD_DESC_SNOOP_ENABLE = (1 << 9), 239 FPDMA_QUEUED_CMD = (1 << 8), 240 SRST_CMD = (1 << 7), 241 BIST = (1 << 6), 242 ATAPI_CMD = (1 << 5), 243 }; 244 245 /* 246 * Command Descriptor 247 */ 248 struct command_desc { 249 u8 cfis[8 * 4]; 250 u8 sfis[8 * 4]; 251 u8 acmd[4 * 4]; 252 u8 fill[4 * 4]; 253 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 254 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 255 }; 256 257 /* 258 * Physical region table descriptor(PRD) 259 */ 260 261 struct prde { 262 u32 dba; 263 u8 fill[2 * 4]; 264 u32 ddc_and_ext; 265 }; 266 267 /* 268 * ata_port private data 269 * This is our per-port instance data. 270 */ 271 struct sata_fsl_port_priv { 272 struct cmdhdr_tbl_entry *cmdslot; 273 dma_addr_t cmdslot_paddr; 274 struct command_desc *cmdentry; 275 dma_addr_t cmdentry_paddr; 276 }; 277 278 /* 279 * ata_port->host_set private data 280 */ 281 struct sata_fsl_host_priv { 282 void __iomem *hcr_base; 283 void __iomem *ssr_base; 284 void __iomem *csr_base; 285 int irq; 286 int data_snoop; 287 struct device_attribute intr_coalescing; 288 }; 289 290 static void fsl_sata_set_irq_coalescing(struct ata_host *host, 291 unsigned int count, unsigned int ticks) 292 { 293 struct sata_fsl_host_priv *host_priv = host->private_data; 294 void __iomem *hcr_base = host_priv->hcr_base; 295 296 if (count > ICC_MAX_INT_COUNT_THRESHOLD) 297 count = ICC_MAX_INT_COUNT_THRESHOLD; 298 else if (count < ICC_MIN_INT_COUNT_THRESHOLD) 299 count = ICC_MIN_INT_COUNT_THRESHOLD; 300 301 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD) 302 ticks = ICC_MAX_INT_TICKS_THRESHOLD; 303 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) && 304 (count > ICC_MIN_INT_COUNT_THRESHOLD)) 305 ticks = ICC_SAFE_INT_TICKS; 306 307 spin_lock(&host->lock); 308 iowrite32((count << 24 | ticks), hcr_base + ICC); 309 310 intr_coalescing_count = count; 311 intr_coalescing_ticks = ticks; 312 spin_unlock(&host->lock); 313 314 DPRINTK("intrrupt coalescing, count = 0x%x, ticks = %x\n", 315 intr_coalescing_count, intr_coalescing_ticks); 316 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n", 317 hcr_base, ioread32(hcr_base + ICC)); 318 } 319 320 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev, 321 struct device_attribute *attr, char *buf) 322 { 323 return sprintf(buf, "%d %d\n", 324 intr_coalescing_count, intr_coalescing_ticks); 325 } 326 327 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev, 328 struct device_attribute *attr, 329 const char *buf, size_t count) 330 { 331 unsigned int coalescing_count, coalescing_ticks; 332 333 if (sscanf(buf, "%d%d", 334 &coalescing_count, 335 &coalescing_ticks) != 2) { 336 printk(KERN_ERR "fsl-sata: wrong parameter format.\n"); 337 return -EINVAL; 338 } 339 340 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev), 341 coalescing_count, coalescing_ticks); 342 343 return strlen(buf); 344 } 345 346 static inline unsigned int sata_fsl_tag(unsigned int tag, 347 void __iomem *hcr_base) 348 { 349 /* We let libATA core do actual (queue) tag allocation */ 350 351 /* all non NCQ/queued commands should have tag#0 */ 352 if (ata_tag_internal(tag)) { 353 DPRINTK("mapping internal cmds to tag#0\n"); 354 return 0; 355 } 356 357 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 358 DPRINTK("tag %d invalid : out of range\n", tag); 359 return 0; 360 } 361 362 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 363 DPRINTK("tag %d invalid : in use!!\n", tag); 364 return 0; 365 } 366 367 return tag; 368 } 369 370 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 371 unsigned int tag, u32 desc_info, 372 u32 data_xfer_len, u8 num_prde, 373 u8 fis_len) 374 { 375 dma_addr_t cmd_descriptor_address; 376 377 cmd_descriptor_address = pp->cmdentry_paddr + 378 tag * SATA_FSL_CMD_DESC_SIZE; 379 380 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 381 382 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 383 pp->cmdslot[tag].prde_fis_len = 384 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 385 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 386 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 387 388 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 389 pp->cmdslot[tag].cda, 390 pp->cmdslot[tag].prde_fis_len, 391 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 392 393 } 394 395 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 396 u32 *ttl, dma_addr_t cmd_desc_paddr, 397 int data_snoop) 398 { 399 struct scatterlist *sg; 400 unsigned int num_prde = 0; 401 u32 ttl_dwords = 0; 402 403 /* 404 * NOTE : direct & indirect prdt's are contiguously allocated 405 */ 406 struct prde *prd = (struct prde *)&((struct command_desc *) 407 cmd_desc)->prdt; 408 409 struct prde *prd_ptr_to_indirect_ext = NULL; 410 unsigned indirect_ext_segment_sz = 0; 411 dma_addr_t indirect_ext_segment_paddr; 412 unsigned int si; 413 414 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 415 416 indirect_ext_segment_paddr = cmd_desc_paddr + 417 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 418 419 for_each_sg(qc->sg, sg, qc->n_elem, si) { 420 dma_addr_t sg_addr = sg_dma_address(sg); 421 u32 sg_len = sg_dma_len(sg); 422 423 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", 424 (unsigned long long)sg_addr, sg_len); 425 426 /* warn if each s/g element is not dword aligned */ 427 if (unlikely(sg_addr & 0x03)) 428 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n", 429 (unsigned long long)sg_addr); 430 if (unlikely(sg_len & 0x03)) 431 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n", 432 sg_len); 433 434 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 435 sg_next(sg) != NULL) { 436 VPRINTK("setting indirect prde\n"); 437 prd_ptr_to_indirect_ext = prd; 438 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 439 indirect_ext_segment_sz = 0; 440 ++prd; 441 ++num_prde; 442 } 443 444 ttl_dwords += sg_len; 445 prd->dba = cpu_to_le32(sg_addr); 446 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); 447 448 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 449 ttl_dwords, prd->dba, prd->ddc_and_ext); 450 451 ++num_prde; 452 ++prd; 453 if (prd_ptr_to_indirect_ext) 454 indirect_ext_segment_sz += sg_len; 455 } 456 457 if (prd_ptr_to_indirect_ext) { 458 /* set indirect extension flag along with indirect ext. size */ 459 prd_ptr_to_indirect_ext->ddc_and_ext = 460 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 461 data_snoop | 462 (indirect_ext_segment_sz & ~0x03))); 463 } 464 465 *ttl = ttl_dwords; 466 return num_prde; 467 } 468 469 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 470 { 471 struct ata_port *ap = qc->ap; 472 struct sata_fsl_port_priv *pp = ap->private_data; 473 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 474 void __iomem *hcr_base = host_priv->hcr_base; 475 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 476 struct command_desc *cd; 477 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 478 u32 num_prde = 0; 479 u32 ttl_dwords = 0; 480 dma_addr_t cd_paddr; 481 482 cd = (struct command_desc *)pp->cmdentry + tag; 483 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 484 485 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 486 487 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 488 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 489 490 if (qc->tf.protocol == ATA_PROT_NCQ) { 491 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 492 cd->cfis[3], cd->cfis[11]); 493 } 494 495 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 496 if (ata_is_atapi(qc->tf.protocol)) { 497 desc_info |= ATAPI_CMD; 498 memset((void *)&cd->acmd, 0, 32); 499 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 500 } 501 502 if (qc->flags & ATA_QCFLAG_DMAMAP) 503 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 504 &ttl_dwords, cd_paddr, 505 host_priv->data_snoop); 506 507 if (qc->tf.protocol == ATA_PROT_NCQ) 508 desc_info |= FPDMA_QUEUED_CMD; 509 510 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 511 num_prde, 5); 512 513 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 514 desc_info, ttl_dwords, num_prde); 515 } 516 517 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 518 { 519 struct ata_port *ap = qc->ap; 520 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 521 void __iomem *hcr_base = host_priv->hcr_base; 522 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 523 524 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 525 ioread32(CQ + hcr_base), 526 ioread32(CA + hcr_base), 527 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 528 529 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 530 531 /* Simply queue command to the controller/device */ 532 iowrite32(1 << tag, CQ + hcr_base); 533 534 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 535 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 536 537 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 538 ioread32(CE + hcr_base), 539 ioread32(DE + hcr_base), 540 ioread32(CC + hcr_base), 541 ioread32(COMMANDSTAT + host_priv->csr_base)); 542 543 return 0; 544 } 545 546 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 547 { 548 struct sata_fsl_port_priv *pp = qc->ap->private_data; 549 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 550 void __iomem *hcr_base = host_priv->hcr_base; 551 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 552 struct command_desc *cd; 553 554 cd = pp->cmdentry + tag; 555 556 ata_tf_from_fis(cd->sfis, &qc->result_tf); 557 return true; 558 } 559 560 static int sata_fsl_scr_write(struct ata_link *link, 561 unsigned int sc_reg_in, u32 val) 562 { 563 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 564 void __iomem *ssr_base = host_priv->ssr_base; 565 unsigned int sc_reg; 566 567 switch (sc_reg_in) { 568 case SCR_STATUS: 569 case SCR_ERROR: 570 case SCR_CONTROL: 571 case SCR_ACTIVE: 572 sc_reg = sc_reg_in; 573 break; 574 default: 575 return -EINVAL; 576 } 577 578 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 579 580 iowrite32(val, ssr_base + (sc_reg * 4)); 581 return 0; 582 } 583 584 static int sata_fsl_scr_read(struct ata_link *link, 585 unsigned int sc_reg_in, u32 *val) 586 { 587 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 588 void __iomem *ssr_base = host_priv->ssr_base; 589 unsigned int sc_reg; 590 591 switch (sc_reg_in) { 592 case SCR_STATUS: 593 case SCR_ERROR: 594 case SCR_CONTROL: 595 case SCR_ACTIVE: 596 sc_reg = sc_reg_in; 597 break; 598 default: 599 return -EINVAL; 600 } 601 602 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 603 604 *val = ioread32(ssr_base + (sc_reg * 4)); 605 return 0; 606 } 607 608 static void sata_fsl_freeze(struct ata_port *ap) 609 { 610 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 611 void __iomem *hcr_base = host_priv->hcr_base; 612 u32 temp; 613 614 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 615 ioread32(CQ + hcr_base), 616 ioread32(CA + hcr_base), 617 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 618 VPRINTK("CmdStat = 0x%x\n", 619 ioread32(host_priv->csr_base + COMMANDSTAT)); 620 621 /* disable interrupts on the controller/port */ 622 temp = ioread32(hcr_base + HCONTROL); 623 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 624 625 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 626 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 627 } 628 629 static void sata_fsl_thaw(struct ata_port *ap) 630 { 631 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 632 void __iomem *hcr_base = host_priv->hcr_base; 633 u32 temp; 634 635 /* ack. any pending IRQs for this controller/port */ 636 temp = ioread32(hcr_base + HSTATUS); 637 638 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 639 640 if (temp & 0x3F) 641 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 642 643 /* enable interrupts on the controller/port */ 644 temp = ioread32(hcr_base + HCONTROL); 645 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 646 647 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 648 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 649 } 650 651 static void sata_fsl_pmp_attach(struct ata_port *ap) 652 { 653 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 654 void __iomem *hcr_base = host_priv->hcr_base; 655 u32 temp; 656 657 temp = ioread32(hcr_base + HCONTROL); 658 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 659 } 660 661 static void sata_fsl_pmp_detach(struct ata_port *ap) 662 { 663 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 664 void __iomem *hcr_base = host_priv->hcr_base; 665 u32 temp; 666 667 temp = ioread32(hcr_base + HCONTROL); 668 temp &= ~HCONTROL_PMP_ATTACHED; 669 iowrite32(temp, hcr_base + HCONTROL); 670 671 /* enable interrupts on the controller/port */ 672 temp = ioread32(hcr_base + HCONTROL); 673 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 674 675 } 676 677 static int sata_fsl_port_start(struct ata_port *ap) 678 { 679 struct device *dev = ap->host->dev; 680 struct sata_fsl_port_priv *pp; 681 void *mem; 682 dma_addr_t mem_dma; 683 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 684 void __iomem *hcr_base = host_priv->hcr_base; 685 u32 temp; 686 687 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 688 if (!pp) 689 return -ENOMEM; 690 691 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 692 GFP_KERNEL); 693 if (!mem) { 694 kfree(pp); 695 return -ENOMEM; 696 } 697 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 698 699 pp->cmdslot = mem; 700 pp->cmdslot_paddr = mem_dma; 701 702 mem += SATA_FSL_CMD_SLOT_SIZE; 703 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 704 705 pp->cmdentry = mem; 706 pp->cmdentry_paddr = mem_dma; 707 708 ap->private_data = pp; 709 710 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 711 pp->cmdslot_paddr, pp->cmdentry_paddr); 712 713 /* Now, update the CHBA register in host controller cmd register set */ 714 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 715 716 /* 717 * Now, we can bring the controller on-line & also initiate 718 * the COMINIT sequence, we simply return here and the boot-probing 719 * & device discovery process is re-initiated by libATA using a 720 * Softreset EH (dummy) session. Hence, boot probing and device 721 * discovey will be part of sata_fsl_softreset() callback. 722 */ 723 724 temp = ioread32(hcr_base + HCONTROL); 725 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 726 727 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 728 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 729 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 730 731 #ifdef CONFIG_MPC8315_DS 732 /* 733 * Workaround for 8315DS board 3gbps link-up issue, 734 * currently limit SATA port to GEN1 speed 735 */ 736 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 737 temp &= ~(0xF << 4); 738 temp |= (0x1 << 4); 739 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp); 740 741 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 742 dev_warn(dev, "scr_control, speed limited to %x\n", temp); 743 #endif 744 745 return 0; 746 } 747 748 static void sata_fsl_port_stop(struct ata_port *ap) 749 { 750 struct device *dev = ap->host->dev; 751 struct sata_fsl_port_priv *pp = ap->private_data; 752 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 753 void __iomem *hcr_base = host_priv->hcr_base; 754 u32 temp; 755 756 /* 757 * Force host controller to go off-line, aborting current operations 758 */ 759 temp = ioread32(hcr_base + HCONTROL); 760 temp &= ~HCONTROL_ONLINE_PHY_RST; 761 temp |= HCONTROL_FORCE_OFFLINE; 762 iowrite32(temp, hcr_base + HCONTROL); 763 764 /* Poll for controller to go offline - should happen immediately */ 765 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 766 767 ap->private_data = NULL; 768 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 769 pp->cmdslot, pp->cmdslot_paddr); 770 771 kfree(pp); 772 } 773 774 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 775 { 776 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 777 void __iomem *hcr_base = host_priv->hcr_base; 778 struct ata_taskfile tf; 779 u32 temp; 780 781 temp = ioread32(hcr_base + SIGNATURE); 782 783 VPRINTK("raw sig = 0x%x\n", temp); 784 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 785 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 786 787 tf.lbah = (temp >> 24) & 0xff; 788 tf.lbam = (temp >> 16) & 0xff; 789 tf.lbal = (temp >> 8) & 0xff; 790 tf.nsect = temp & 0xff; 791 792 return ata_dev_classify(&tf); 793 } 794 795 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, 796 unsigned long deadline) 797 { 798 struct ata_port *ap = link->ap; 799 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 800 void __iomem *hcr_base = host_priv->hcr_base; 801 u32 temp; 802 int i = 0; 803 unsigned long start_jiffies; 804 805 DPRINTK("in xx_hardreset\n"); 806 807 try_offline_again: 808 /* 809 * Force host controller to go off-line, aborting current operations 810 */ 811 temp = ioread32(hcr_base + HCONTROL); 812 temp &= ~HCONTROL_ONLINE_PHY_RST; 813 iowrite32(temp, hcr_base + HCONTROL); 814 815 /* Poll for controller to go offline */ 816 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 817 1, 500); 818 819 if (temp & ONLINE) { 820 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i); 821 822 /* 823 * Try to offline controller atleast twice 824 */ 825 i++; 826 if (i == 2) 827 goto err; 828 else 829 goto try_offline_again; 830 } 831 832 DPRINTK("hardreset, controller off-lined\n"); 833 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 834 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 835 836 /* 837 * PHY reset should remain asserted for atleast 1ms 838 */ 839 ata_msleep(ap, 1); 840 841 /* 842 * Now, bring the host controller online again, this can take time 843 * as PHY reset and communication establishment, 1st D2H FIS and 844 * device signature update is done, on safe side assume 500ms 845 * NOTE : Host online status may be indicated immediately!! 846 */ 847 848 temp = ioread32(hcr_base + HCONTROL); 849 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 850 temp |= HCONTROL_PMP_ATTACHED; 851 iowrite32(temp, hcr_base + HCONTROL); 852 853 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); 854 855 if (!(temp & ONLINE)) { 856 ata_port_err(ap, "Hardreset failed, not on-lined\n"); 857 goto err; 858 } 859 860 DPRINTK("hardreset, controller off-lined & on-lined\n"); 861 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 862 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 863 864 /* 865 * First, wait for the PHYRDY change to occur before waiting for 866 * the signature, and also verify if SStatus indicates device 867 * presence 868 */ 869 870 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); 871 if ((!(temp & 0x10)) || ata_link_offline(link)) { 872 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n", 873 ioread32(hcr_base + HSTATUS)); 874 *class = ATA_DEV_NONE; 875 return 0; 876 } 877 878 /* 879 * Wait for the first D2H from device,i.e,signature update notification 880 */ 881 start_jiffies = jiffies; 882 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, 883 500, jiffies_to_msecs(deadline - start_jiffies)); 884 885 if ((temp & 0xFF) != 0x18) { 886 ata_port_warn(ap, "No Signature Update\n"); 887 *class = ATA_DEV_NONE; 888 goto do_followup_srst; 889 } else { 890 ata_port_info(ap, "Signature Update detected @ %d msecs\n", 891 jiffies_to_msecs(jiffies - start_jiffies)); 892 *class = sata_fsl_dev_classify(ap); 893 return 0; 894 } 895 896 do_followup_srst: 897 /* 898 * request libATA to perform follow-up softreset 899 */ 900 return -EAGAIN; 901 902 err: 903 return -EIO; 904 } 905 906 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 907 unsigned long deadline) 908 { 909 struct ata_port *ap = link->ap; 910 struct sata_fsl_port_priv *pp = ap->private_data; 911 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 912 void __iomem *hcr_base = host_priv->hcr_base; 913 int pmp = sata_srst_pmp(link); 914 u32 temp; 915 struct ata_taskfile tf; 916 u8 *cfis; 917 u32 Serror; 918 919 DPRINTK("in xx_softreset\n"); 920 921 if (ata_link_offline(link)) { 922 DPRINTK("PHY reports no device\n"); 923 *class = ATA_DEV_NONE; 924 return 0; 925 } 926 927 /* 928 * Send a device reset (SRST) explicitly on command slot #0 929 * Check : will the command queue (reg) be cleared during offlining ?? 930 * Also we will be online only if Phy commn. has been established 931 * and device presence has been detected, therefore if we have 932 * reached here, we can send a command to the target device 933 */ 934 935 DPRINTK("Sending SRST/device reset\n"); 936 937 ata_tf_init(link->device, &tf); 938 cfis = (u8 *) &pp->cmdentry->cfis; 939 940 /* device reset/SRST is a control register update FIS, uses tag0 */ 941 sata_fsl_setup_cmd_hdr_entry(pp, 0, 942 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 943 944 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 945 ata_tf_to_fis(&tf, pmp, 0, cfis); 946 947 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 948 cfis[0], cfis[1], cfis[2], cfis[3]); 949 950 /* 951 * Queue SRST command to the controller/device, ensure that no 952 * other commands are active on the controller/device 953 */ 954 955 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 956 ioread32(CQ + hcr_base), 957 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 958 959 iowrite32(0xFFFF, CC + hcr_base); 960 if (pmp != SATA_PMP_CTRL_PORT) 961 iowrite32(pmp, CQPMP + hcr_base); 962 iowrite32(1, CQ + hcr_base); 963 964 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); 965 if (temp & 0x1) { 966 ata_port_warn(ap, "ATA_SRST issue failed\n"); 967 968 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 969 ioread32(CQ + hcr_base), 970 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 971 972 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 973 974 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 975 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 976 DPRINTK("Serror = 0x%x\n", Serror); 977 goto err; 978 } 979 980 ata_msleep(ap, 1); 981 982 /* 983 * SATA device enters reset state after receiving a Control register 984 * FIS with SRST bit asserted and it awaits another H2D Control reg. 985 * FIS with SRST bit cleared, then the device does internal diags & 986 * initialization, followed by indicating it's initialization status 987 * using ATA signature D2H register FIS to the host controller. 988 */ 989 990 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 991 0, 0, 5); 992 993 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 994 ata_tf_to_fis(&tf, pmp, 0, cfis); 995 996 if (pmp != SATA_PMP_CTRL_PORT) 997 iowrite32(pmp, CQPMP + hcr_base); 998 iowrite32(1, CQ + hcr_base); 999 ata_msleep(ap, 150); /* ?? */ 1000 1001 /* 1002 * The above command would have signalled an interrupt on command 1003 * complete, which needs special handling, by clearing the Nth 1004 * command bit of the CCreg 1005 */ 1006 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 1007 1008 DPRINTK("SATA FSL : Now checking device signature\n"); 1009 1010 *class = ATA_DEV_NONE; 1011 1012 /* Verify if SStatus indicates device presence */ 1013 if (ata_link_online(link)) { 1014 /* 1015 * if we are here, device presence has been detected, 1016 * 1st D2H FIS would have been received, but sfis in 1017 * command desc. is not updated, but signature register 1018 * would have been updated 1019 */ 1020 1021 *class = sata_fsl_dev_classify(ap); 1022 1023 DPRINTK("class = %d\n", *class); 1024 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 1025 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 1026 } 1027 1028 return 0; 1029 1030 err: 1031 return -EIO; 1032 } 1033 1034 static void sata_fsl_error_handler(struct ata_port *ap) 1035 { 1036 1037 DPRINTK("in xx_error_handler\n"); 1038 sata_pmp_error_handler(ap); 1039 1040 } 1041 1042 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 1043 { 1044 if (qc->flags & ATA_QCFLAG_FAILED) 1045 qc->err_mask |= AC_ERR_OTHER; 1046 1047 if (qc->err_mask) { 1048 /* make DMA engine forget about the failed command */ 1049 1050 } 1051 } 1052 1053 static void sata_fsl_error_intr(struct ata_port *ap) 1054 { 1055 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1056 void __iomem *hcr_base = host_priv->hcr_base; 1057 u32 hstatus, dereg=0, cereg = 0, SError = 0; 1058 unsigned int err_mask = 0, action = 0; 1059 int freeze = 0, abort=0; 1060 struct ata_link *link = NULL; 1061 struct ata_queued_cmd *qc = NULL; 1062 struct ata_eh_info *ehi; 1063 1064 hstatus = ioread32(hcr_base + HSTATUS); 1065 cereg = ioread32(hcr_base + CE); 1066 1067 /* first, analyze and record host port events */ 1068 link = &ap->link; 1069 ehi = &link->eh_info; 1070 ata_ehi_clear_desc(ehi); 1071 1072 /* 1073 * Handle & Clear SError 1074 */ 1075 1076 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1077 if (unlikely(SError & 0xFFFF0000)) 1078 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 1079 1080 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 1081 hstatus, cereg, ioread32(hcr_base + DE), SError); 1082 1083 /* handle fatal errors */ 1084 if (hstatus & FATAL_ERROR_DECODE) { 1085 ehi->err_mask |= AC_ERR_ATA_BUS; 1086 ehi->action |= ATA_EH_SOFTRESET; 1087 1088 freeze = 1; 1089 } 1090 1091 /* Handle SDB FIS receive & notify update */ 1092 if (hstatus & INT_ON_SNOTIFY_UPDATE) 1093 sata_async_notification(ap); 1094 1095 /* Handle PHYRDY change notification */ 1096 if (hstatus & INT_ON_PHYRDY_CHG) { 1097 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1098 1099 /* Setup a soft-reset EH action */ 1100 ata_ehi_hotplugged(ehi); 1101 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1102 freeze = 1; 1103 } 1104 1105 /* handle single device errors */ 1106 if (cereg) { 1107 /* 1108 * clear the command error, also clears queue to the device 1109 * in error, and we can (re)issue commands to this device. 1110 * When a device is in error all commands queued into the 1111 * host controller and at the device are considered aborted 1112 * and the queue for that device is stopped. Now, after 1113 * clearing the device error, we can issue commands to the 1114 * device to interrogate it to find the source of the error. 1115 */ 1116 abort = 1; 1117 1118 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 1119 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1120 1121 /* find out the offending link and qc */ 1122 if (ap->nr_pmp_links) { 1123 unsigned int dev_num; 1124 1125 dereg = ioread32(hcr_base + DE); 1126 iowrite32(dereg, hcr_base + DE); 1127 iowrite32(cereg, hcr_base + CE); 1128 1129 dev_num = ffs(dereg) - 1; 1130 if (dev_num < ap->nr_pmp_links && dereg != 0) { 1131 link = &ap->pmp_link[dev_num]; 1132 ehi = &link->eh_info; 1133 qc = ata_qc_from_tag(ap, link->active_tag); 1134 /* 1135 * We should consider this as non fatal error, 1136 * and TF must be updated as done below. 1137 */ 1138 1139 err_mask |= AC_ERR_DEV; 1140 1141 } else { 1142 err_mask |= AC_ERR_HSM; 1143 action |= ATA_EH_HARDRESET; 1144 freeze = 1; 1145 } 1146 } else { 1147 dereg = ioread32(hcr_base + DE); 1148 iowrite32(dereg, hcr_base + DE); 1149 iowrite32(cereg, hcr_base + CE); 1150 1151 qc = ata_qc_from_tag(ap, link->active_tag); 1152 /* 1153 * We should consider this as non fatal error, 1154 * and TF must be updated as done below. 1155 */ 1156 err_mask |= AC_ERR_DEV; 1157 } 1158 } 1159 1160 /* record error info */ 1161 if (qc) 1162 qc->err_mask |= err_mask; 1163 else 1164 ehi->err_mask |= err_mask; 1165 1166 ehi->action |= action; 1167 1168 /* freeze or abort */ 1169 if (freeze) 1170 ata_port_freeze(ap); 1171 else if (abort) { 1172 if (qc) 1173 ata_link_abort(qc->dev->link); 1174 else 1175 ata_port_abort(ap); 1176 } 1177 } 1178 1179 static void sata_fsl_host_intr(struct ata_port *ap) 1180 { 1181 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1182 void __iomem *hcr_base = host_priv->hcr_base; 1183 u32 hstatus, done_mask = 0; 1184 struct ata_queued_cmd *qc; 1185 u32 SError; 1186 u32 tag; 1187 u32 status_mask = INT_ON_ERROR; 1188 1189 hstatus = ioread32(hcr_base + HSTATUS); 1190 1191 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1192 1193 /* Read command completed register */ 1194 done_mask = ioread32(hcr_base + CC); 1195 1196 /* Workaround for data length mismatch errata */ 1197 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) { 1198 for (tag = 0; tag < ATA_MAX_QUEUE; tag++) { 1199 qc = ata_qc_from_tag(ap, tag); 1200 if (qc && ata_is_atapi(qc->tf.protocol)) { 1201 u32 hcontrol; 1202 /* Set HControl[27] to clear error registers */ 1203 hcontrol = ioread32(hcr_base + HCONTROL); 1204 iowrite32(hcontrol | CLEAR_ERROR, 1205 hcr_base + HCONTROL); 1206 1207 /* Clear HControl[27] */ 1208 iowrite32(hcontrol & ~CLEAR_ERROR, 1209 hcr_base + HCONTROL); 1210 1211 /* Clear SError[E] bit */ 1212 sata_fsl_scr_write(&ap->link, SCR_ERROR, 1213 SError); 1214 1215 /* Ignore fatal error and device error */ 1216 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR 1217 | INT_ON_FATAL_ERR); 1218 break; 1219 } 1220 } 1221 } 1222 1223 if (unlikely(SError & 0xFFFF0000)) { 1224 DPRINTK("serror @host_intr : 0x%x\n", SError); 1225 sata_fsl_error_intr(ap); 1226 } 1227 1228 if (unlikely(hstatus & status_mask)) { 1229 DPRINTK("error interrupt!!\n"); 1230 sata_fsl_error_intr(ap); 1231 return; 1232 } 1233 1234 VPRINTK("Status of all queues :\n"); 1235 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", 1236 done_mask, 1237 ioread32(hcr_base + CA), 1238 ioread32(hcr_base + CE), 1239 ioread32(hcr_base + CQ), 1240 ap->qc_active); 1241 1242 if (done_mask & ap->qc_active) { 1243 int i; 1244 /* clear CC bit, this will also complete the interrupt */ 1245 iowrite32(done_mask, hcr_base + CC); 1246 1247 DPRINTK("Status of all queues :\n"); 1248 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1249 done_mask, ioread32(hcr_base + CA), 1250 ioread32(hcr_base + CE)); 1251 1252 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1253 if (done_mask & (1 << i)) 1254 DPRINTK 1255 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1256 i, ioread32(hcr_base + CC), 1257 ioread32(hcr_base + CA)); 1258 } 1259 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); 1260 return; 1261 1262 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { 1263 iowrite32(1, hcr_base + CC); 1264 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1265 1266 DPRINTK("completing non-ncq cmd, CC=0x%x\n", 1267 ioread32(hcr_base + CC)); 1268 1269 if (qc) { 1270 ata_qc_complete(qc); 1271 } 1272 } else { 1273 /* Spurious Interrupt!! */ 1274 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1275 ioread32(hcr_base + CC)); 1276 iowrite32(done_mask, hcr_base + CC); 1277 return; 1278 } 1279 } 1280 1281 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1282 { 1283 struct ata_host *host = dev_instance; 1284 struct sata_fsl_host_priv *host_priv = host->private_data; 1285 void __iomem *hcr_base = host_priv->hcr_base; 1286 u32 interrupt_enables; 1287 unsigned handled = 0; 1288 struct ata_port *ap; 1289 1290 /* ack. any pending IRQs for this controller/port */ 1291 interrupt_enables = ioread32(hcr_base + HSTATUS); 1292 interrupt_enables &= 0x3F; 1293 1294 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1295 1296 if (!interrupt_enables) 1297 return IRQ_NONE; 1298 1299 spin_lock(&host->lock); 1300 1301 /* Assuming one port per host controller */ 1302 1303 ap = host->ports[0]; 1304 if (ap) { 1305 sata_fsl_host_intr(ap); 1306 } else { 1307 dev_warn(host->dev, "interrupt on disabled port 0\n"); 1308 } 1309 1310 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1311 handled = 1; 1312 1313 spin_unlock(&host->lock); 1314 1315 return IRQ_RETVAL(handled); 1316 } 1317 1318 /* 1319 * Multiple ports are represented by multiple SATA controllers with 1320 * one port per controller 1321 */ 1322 static int sata_fsl_init_controller(struct ata_host *host) 1323 { 1324 struct sata_fsl_host_priv *host_priv = host->private_data; 1325 void __iomem *hcr_base = host_priv->hcr_base; 1326 u32 temp; 1327 1328 /* 1329 * NOTE : We cannot bring the controller online before setting 1330 * the CHBA, hence main controller initialization is done as 1331 * part of the port_start() callback 1332 */ 1333 1334 /* sata controller to operate in enterprise mode */ 1335 temp = ioread32(hcr_base + HCONTROL); 1336 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); 1337 1338 /* ack. any pending IRQs for this controller/port */ 1339 temp = ioread32(hcr_base + HSTATUS); 1340 if (temp & 0x3F) 1341 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1342 1343 /* Keep interrupts disabled on the controller */ 1344 temp = ioread32(hcr_base + HCONTROL); 1345 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1346 1347 /* Disable interrupt coalescing control(icc), for the moment */ 1348 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1349 iowrite32(0x01000000, hcr_base + ICC); 1350 1351 /* clear error registers, SError is cleared by libATA */ 1352 iowrite32(0x00000FFFF, hcr_base + CE); 1353 iowrite32(0x00000FFFF, hcr_base + DE); 1354 1355 /* 1356 * reset the number of command complete bits which will cause the 1357 * interrupt to be signaled 1358 */ 1359 fsl_sata_set_irq_coalescing(host, intr_coalescing_count, 1360 intr_coalescing_ticks); 1361 1362 /* 1363 * host controller will be brought on-line, during xx_port_start() 1364 * callback, that should also initiate the OOB, COMINIT sequence 1365 */ 1366 1367 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1368 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1369 1370 return 0; 1371 } 1372 1373 /* 1374 * scsi mid-layer and libata interface structures 1375 */ 1376 static struct scsi_host_template sata_fsl_sht = { 1377 ATA_NCQ_SHT("sata_fsl"), 1378 .can_queue = SATA_FSL_QUEUE_DEPTH, 1379 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1380 .dma_boundary = ATA_DMA_BOUNDARY, 1381 }; 1382 1383 static struct ata_port_operations sata_fsl_ops = { 1384 .inherits = &sata_pmp_port_ops, 1385 1386 .qc_defer = ata_std_qc_defer, 1387 .qc_prep = sata_fsl_qc_prep, 1388 .qc_issue = sata_fsl_qc_issue, 1389 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1390 1391 .scr_read = sata_fsl_scr_read, 1392 .scr_write = sata_fsl_scr_write, 1393 1394 .freeze = sata_fsl_freeze, 1395 .thaw = sata_fsl_thaw, 1396 .softreset = sata_fsl_softreset, 1397 .hardreset = sata_fsl_hardreset, 1398 .pmp_softreset = sata_fsl_softreset, 1399 .error_handler = sata_fsl_error_handler, 1400 .post_internal_cmd = sata_fsl_post_internal_cmd, 1401 1402 .port_start = sata_fsl_port_start, 1403 .port_stop = sata_fsl_port_stop, 1404 1405 .pmp_attach = sata_fsl_pmp_attach, 1406 .pmp_detach = sata_fsl_pmp_detach, 1407 }; 1408 1409 static const struct ata_port_info sata_fsl_port_info[] = { 1410 { 1411 .flags = SATA_FSL_HOST_FLAGS, 1412 .pio_mask = ATA_PIO4, 1413 .udma_mask = ATA_UDMA6, 1414 .port_ops = &sata_fsl_ops, 1415 }, 1416 }; 1417 1418 static int sata_fsl_probe(struct platform_device *ofdev) 1419 { 1420 int retval = -ENXIO; 1421 void __iomem *hcr_base = NULL; 1422 void __iomem *ssr_base = NULL; 1423 void __iomem *csr_base = NULL; 1424 struct sata_fsl_host_priv *host_priv = NULL; 1425 int irq; 1426 struct ata_host *host = NULL; 1427 u32 temp; 1428 1429 struct ata_port_info pi = sata_fsl_port_info[0]; 1430 const struct ata_port_info *ppi[] = { &pi, NULL }; 1431 1432 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n"); 1433 1434 hcr_base = of_iomap(ofdev->dev.of_node, 0); 1435 if (!hcr_base) 1436 goto error_exit_with_cleanup; 1437 1438 ssr_base = hcr_base + 0x100; 1439 csr_base = hcr_base + 0x140; 1440 1441 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { 1442 temp = ioread32(csr_base + TRANSCFG); 1443 temp = temp & 0xffffffe0; 1444 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); 1445 } 1446 1447 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1448 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1449 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1450 1451 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1452 if (!host_priv) 1453 goto error_exit_with_cleanup; 1454 1455 host_priv->hcr_base = hcr_base; 1456 host_priv->ssr_base = ssr_base; 1457 host_priv->csr_base = csr_base; 1458 1459 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1460 if (irq < 0) { 1461 dev_err(&ofdev->dev, "invalid irq from platform\n"); 1462 goto error_exit_with_cleanup; 1463 } 1464 host_priv->irq = irq; 1465 1466 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) 1467 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; 1468 else 1469 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; 1470 1471 /* allocate host structure */ 1472 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1473 if (!host) { 1474 retval = -ENOMEM; 1475 goto error_exit_with_cleanup; 1476 } 1477 1478 /* host->iomap is not used currently */ 1479 host->private_data = host_priv; 1480 1481 /* initialize host controller */ 1482 sata_fsl_init_controller(host); 1483 1484 /* 1485 * Now, register with libATA core, this will also initiate the 1486 * device discovery process, invoking our port_start() handler & 1487 * error_handler() to execute a dummy Softreset EH session 1488 */ 1489 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1490 &sata_fsl_sht); 1491 1492 dev_set_drvdata(&ofdev->dev, host); 1493 1494 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show; 1495 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store; 1496 sysfs_attr_init(&host_priv->intr_coalescing.attr); 1497 host_priv->intr_coalescing.attr.name = "intr_coalescing"; 1498 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR; 1499 retval = device_create_file(host->dev, &host_priv->intr_coalescing); 1500 if (retval) 1501 goto error_exit_with_cleanup; 1502 1503 return 0; 1504 1505 error_exit_with_cleanup: 1506 1507 if (host) { 1508 dev_set_drvdata(&ofdev->dev, NULL); 1509 ata_host_detach(host); 1510 } 1511 1512 if (hcr_base) 1513 iounmap(hcr_base); 1514 if (host_priv) 1515 kfree(host_priv); 1516 1517 return retval; 1518 } 1519 1520 static int sata_fsl_remove(struct platform_device *ofdev) 1521 { 1522 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1523 struct sata_fsl_host_priv *host_priv = host->private_data; 1524 1525 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); 1526 1527 ata_host_detach(host); 1528 1529 dev_set_drvdata(&ofdev->dev, NULL); 1530 1531 irq_dispose_mapping(host_priv->irq); 1532 iounmap(host_priv->hcr_base); 1533 kfree(host_priv); 1534 1535 return 0; 1536 } 1537 1538 #ifdef CONFIG_PM 1539 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) 1540 { 1541 struct ata_host *host = dev_get_drvdata(&op->dev); 1542 return ata_host_suspend(host, state); 1543 } 1544 1545 static int sata_fsl_resume(struct platform_device *op) 1546 { 1547 struct ata_host *host = dev_get_drvdata(&op->dev); 1548 struct sata_fsl_host_priv *host_priv = host->private_data; 1549 int ret; 1550 void __iomem *hcr_base = host_priv->hcr_base; 1551 struct ata_port *ap = host->ports[0]; 1552 struct sata_fsl_port_priv *pp = ap->private_data; 1553 1554 ret = sata_fsl_init_controller(host); 1555 if (ret) { 1556 dev_err(&op->dev, "Error initializing hardware\n"); 1557 return ret; 1558 } 1559 1560 /* Recovery the CHBA register in host controller cmd register set */ 1561 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 1562 1563 iowrite32((ioread32(hcr_base + HCONTROL) 1564 | HCONTROL_ONLINE_PHY_RST 1565 | HCONTROL_SNOOP_ENABLE 1566 | HCONTROL_PMP_ATTACHED), 1567 hcr_base + HCONTROL); 1568 1569 ata_host_resume(host); 1570 return 0; 1571 } 1572 #endif 1573 1574 static struct of_device_id fsl_sata_match[] = { 1575 { 1576 .compatible = "fsl,pq-sata", 1577 }, 1578 { 1579 .compatible = "fsl,pq-sata-v2", 1580 }, 1581 {}, 1582 }; 1583 1584 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1585 1586 static struct platform_driver fsl_sata_driver = { 1587 .driver = { 1588 .name = "fsl-sata", 1589 .owner = THIS_MODULE, 1590 .of_match_table = fsl_sata_match, 1591 }, 1592 .probe = sata_fsl_probe, 1593 .remove = sata_fsl_remove, 1594 #ifdef CONFIG_PM 1595 .suspend = sata_fsl_suspend, 1596 .resume = sata_fsl_resume, 1597 #endif 1598 }; 1599 1600 module_platform_driver(fsl_sata_driver); 1601 1602 MODULE_LICENSE("GPL"); 1603 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1604 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1605 MODULE_VERSION("1.10"); 1606