1 /* 2 * drivers/ata/sata_dwc_460ex.c 3 * 4 * Synopsys DesignWare Cores (DWC) SATA host driver 5 * 6 * Author: Mark Miesfeld <mmiesfeld@amcc.com> 7 * 8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de> 9 * Copyright 2008 DENX Software Engineering 10 * 11 * Based on versions provided by AMCC and Synopsys which are: 12 * Copyright 2006 Applied Micro Circuits Corporation 13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 21 #ifdef CONFIG_SATA_DWC_DEBUG 22 #define DEBUG 23 #endif 24 25 #ifdef CONFIG_SATA_DWC_VDEBUG 26 #define VERBOSE_DEBUG 27 #define DEBUG_NCQ 28 #endif 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/init.h> 33 #include <linux/device.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/of_platform.h> 37 #include <linux/platform_device.h> 38 #include <linux/libata.h> 39 #include <linux/slab.h> 40 #include "libata.h" 41 42 #include <scsi/scsi_host.h> 43 #include <scsi/scsi_cmnd.h> 44 45 /* These two are defined in "libata.h" */ 46 #undef DRV_NAME 47 #undef DRV_VERSION 48 49 #define DRV_NAME "sata-dwc" 50 #define DRV_VERSION "1.3" 51 52 /* SATA DMA driver Globals */ 53 #define DMA_NUM_CHANS 1 54 #define DMA_NUM_CHAN_REGS 8 55 56 /* SATA DMA Register definitions */ 57 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/ 58 59 struct dmareg { 60 u32 low; /* Low bits 0-31 */ 61 u32 high; /* High bits 32-63 */ 62 }; 63 64 /* DMA Per Channel registers */ 65 struct dma_chan_regs { 66 struct dmareg sar; /* Source Address */ 67 struct dmareg dar; /* Destination address */ 68 struct dmareg llp; /* Linked List Pointer */ 69 struct dmareg ctl; /* Control */ 70 struct dmareg sstat; /* Source Status not implemented in core */ 71 struct dmareg dstat; /* Destination Status not implemented in core*/ 72 struct dmareg sstatar; /* Source Status Address not impl in core */ 73 struct dmareg dstatar; /* Destination Status Address not implemente */ 74 struct dmareg cfg; /* Config */ 75 struct dmareg sgr; /* Source Gather */ 76 struct dmareg dsr; /* Destination Scatter */ 77 }; 78 79 /* Generic Interrupt Registers */ 80 struct dma_interrupt_regs { 81 struct dmareg tfr; /* Transfer Interrupt */ 82 struct dmareg block; /* Block Interrupt */ 83 struct dmareg srctran; /* Source Transfer Interrupt */ 84 struct dmareg dsttran; /* Dest Transfer Interrupt */ 85 struct dmareg error; /* Error */ 86 }; 87 88 struct ahb_dma_regs { 89 struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS]; 90 struct dma_interrupt_regs interrupt_raw; /* Raw Interrupt */ 91 struct dma_interrupt_regs interrupt_status; /* Interrupt Status */ 92 struct dma_interrupt_regs interrupt_mask; /* Interrupt Mask */ 93 struct dma_interrupt_regs interrupt_clear; /* Interrupt Clear */ 94 struct dmareg statusInt; /* Interrupt combined*/ 95 struct dmareg rq_srcreg; /* Src Trans Req */ 96 struct dmareg rq_dstreg; /* Dst Trans Req */ 97 struct dmareg rq_sgl_srcreg; /* Sngl Src Trans Req*/ 98 struct dmareg rq_sgl_dstreg; /* Sngl Dst Trans Req*/ 99 struct dmareg rq_lst_srcreg; /* Last Src Trans Req*/ 100 struct dmareg rq_lst_dstreg; /* Last Dst Trans Req*/ 101 struct dmareg dma_cfg; /* DMA Config */ 102 struct dmareg dma_chan_en; /* DMA Channel Enable*/ 103 struct dmareg dma_id; /* DMA ID */ 104 struct dmareg dma_test; /* DMA Test */ 105 struct dmareg res1; /* reserved */ 106 struct dmareg res2; /* reserved */ 107 /* 108 * DMA Comp Params 109 * Param 6 = dma_param[0], Param 5 = dma_param[1], 110 * Param 4 = dma_param[2] ... 111 */ 112 struct dmareg dma_params[6]; 113 }; 114 115 /* Data structure for linked list item */ 116 struct lli { 117 u32 sar; /* Source Address */ 118 u32 dar; /* Destination address */ 119 u32 llp; /* Linked List Pointer */ 120 struct dmareg ctl; /* Control */ 121 struct dmareg dstat; /* Destination Status */ 122 }; 123 124 enum { 125 SATA_DWC_DMAC_LLI_SZ = (sizeof(struct lli)), 126 SATA_DWC_DMAC_LLI_NUM = 256, 127 SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \ 128 SATA_DWC_DMAC_LLI_NUM), 129 SATA_DWC_DMAC_TWIDTH_BYTES = 4, 130 SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \ 131 SATA_DWC_DMAC_TWIDTH_BYTES), 132 }; 133 134 /* DMA Register Operation Bits */ 135 enum { 136 DMA_EN = 0x00000001, /* Enable AHB DMA */ 137 DMA_CTL_LLP_SRCEN = 0x10000000, /* Blk chain enable Src */ 138 DMA_CTL_LLP_DSTEN = 0x08000000, /* Blk chain enable Dst */ 139 }; 140 141 #define DMA_CTL_BLK_TS(size) ((size) & 0x000000FFF) /* Blk Transfer size */ 142 #define DMA_CHANNEL(ch) (0x00000001 << (ch)) /* Select channel */ 143 /* Enable channel */ 144 #define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \ 145 ((0x000000001 << (ch)) << 8)) 146 /* Disable channel */ 147 #define DMA_DISABLE_CHAN(ch) (0x00000000 | ((0x000000001 << (ch)) << 8)) 148 /* Transfer Type & Flow Controller */ 149 #define DMA_CTL_TTFC(type) (((type) & 0x7) << 20) 150 #define DMA_CTL_SMS(num) (((num) & 0x3) << 25) /* Src Master Select */ 151 #define DMA_CTL_DMS(num) (((num) & 0x3) << 23)/* Dst Master Select */ 152 /* Src Burst Transaction Length */ 153 #define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14) 154 /* Dst Burst Transaction Length */ 155 #define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11) 156 /* Source Transfer Width */ 157 #define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4) 158 /* Destination Transfer Width */ 159 #define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1) 160 161 /* Assign HW handshaking interface (x) to destination / source peripheral */ 162 #define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11) 163 #define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7) 164 #define DMA_CFG_HW_CH_PRIOR(int_num) (((int_num) & 0xF) << 5) 165 #define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master)) 166 167 /* 168 * This define is used to set block chaining disabled in the control low 169 * register. It is already in little endian format so it can be &'d dirctly. 170 * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN)) 171 */ 172 enum { 173 DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7, 174 DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */ 175 DMA_CTL_TTFC_M2P_PER = 0x00000003, /* Mem to per, peripheral cntr */ 176 DMA_CTL_SINC_INC = 0x00000000, /* Source Address Increment */ 177 DMA_CTL_SINC_DEC = 0x00000200, 178 DMA_CTL_SINC_NOCHANGE = 0x00000400, 179 DMA_CTL_DINC_INC = 0x00000000, /* Destination Address Increment */ 180 DMA_CTL_DINC_DEC = 0x00000080, 181 DMA_CTL_DINC_NOCHANGE = 0x00000100, 182 DMA_CTL_INT_EN = 0x00000001, /* Interrupt Enable */ 183 184 /* Channel Configuration Register high bits */ 185 DMA_CFG_FCMOD_REQ = 0x00000001, /* Flow Control - request based */ 186 DMA_CFG_PROTCTL = (0x00000003 << 2),/* Protection Control */ 187 188 /* Channel Configuration Register low bits */ 189 DMA_CFG_RELD_DST = 0x80000000, /* Reload Dest / Src Addr */ 190 DMA_CFG_RELD_SRC = 0x40000000, 191 DMA_CFG_HS_SELSRC = 0x00000800, /* Software handshake Src/ Dest */ 192 DMA_CFG_HS_SELDST = 0x00000400, 193 DMA_CFG_FIFOEMPTY = (0x00000001 << 9), /* FIFO Empty bit */ 194 195 /* Channel Linked List Pointer Register */ 196 DMA_LLP_AHBMASTER1 = 0, /* List Master Select */ 197 DMA_LLP_AHBMASTER2 = 1, 198 199 SATA_DWC_MAX_PORTS = 1, 200 201 SATA_DWC_SCR_OFFSET = 0x24, 202 SATA_DWC_REG_OFFSET = 0x64, 203 }; 204 205 /* DWC SATA Registers */ 206 struct sata_dwc_regs { 207 u32 fptagr; /* 1st party DMA tag */ 208 u32 fpbor; /* 1st party DMA buffer offset */ 209 u32 fptcr; /* 1st party DMA Xfr count */ 210 u32 dmacr; /* DMA Control */ 211 u32 dbtsr; /* DMA Burst Transac size */ 212 u32 intpr; /* Interrupt Pending */ 213 u32 intmr; /* Interrupt Mask */ 214 u32 errmr; /* Error Mask */ 215 u32 llcr; /* Link Layer Control */ 216 u32 phycr; /* PHY Control */ 217 u32 physr; /* PHY Status */ 218 u32 rxbistpd; /* Recvd BIST pattern def register */ 219 u32 rxbistpd1; /* Recvd BIST data dword1 */ 220 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */ 221 u32 txbistpd; /* Trans BIST pattern def register */ 222 u32 txbistpd1; /* Trans BIST data dword1 */ 223 u32 txbistpd2; /* Trans BIST data dword2 */ 224 u32 bistcr; /* BIST Control Register */ 225 u32 bistfctr; /* BIST FIS Count Register */ 226 u32 bistsr; /* BIST Status Register */ 227 u32 bistdecr; /* BIST Dword Error count register */ 228 u32 res[15]; /* Reserved locations */ 229 u32 testr; /* Test Register */ 230 u32 versionr; /* Version Register */ 231 u32 idr; /* ID Register */ 232 u32 unimpl[192]; /* Unimplemented */ 233 u32 dmadr[256]; /* FIFO Locations in DMA Mode */ 234 }; 235 236 enum { 237 SCR_SCONTROL_DET_ENABLE = 0x00000001, 238 SCR_SSTATUS_DET_PRESENT = 0x00000001, 239 SCR_SERROR_DIAG_X = 0x04000000, 240 /* DWC SATA Register Operations */ 241 SATA_DWC_TXFIFO_DEPTH = 0x01FF, 242 SATA_DWC_RXFIFO_DEPTH = 0x01FF, 243 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004, 244 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN), 245 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN), 246 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN, 247 SATA_DWC_INTPR_DMAT = 0x00000001, 248 SATA_DWC_INTPR_NEWFP = 0x00000002, 249 SATA_DWC_INTPR_PMABRT = 0x00000004, 250 SATA_DWC_INTPR_ERR = 0x00000008, 251 SATA_DWC_INTPR_NEWBIST = 0x00000010, 252 SATA_DWC_INTPR_IPF = 0x10000000, 253 SATA_DWC_INTMR_DMATM = 0x00000001, 254 SATA_DWC_INTMR_NEWFPM = 0x00000002, 255 SATA_DWC_INTMR_PMABRTM = 0x00000004, 256 SATA_DWC_INTMR_ERRM = 0x00000008, 257 SATA_DWC_INTMR_NEWBISTM = 0x00000010, 258 SATA_DWC_LLCR_SCRAMEN = 0x00000001, 259 SATA_DWC_LLCR_DESCRAMEN = 0x00000002, 260 SATA_DWC_LLCR_RPDEN = 0x00000004, 261 /* This is all error bits, zero's are reserved fields. */ 262 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03 263 }; 264 265 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F) 266 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\ 267 SATA_DWC_DMACR_TMOD_TXCHEN) 268 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\ 269 SATA_DWC_DMACR_TMOD_TXCHEN) 270 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH) 271 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\ 272 << 16) 273 struct sata_dwc_device { 274 struct device *dev; /* generic device struct */ 275 struct ata_probe_ent *pe; /* ptr to probe-ent */ 276 struct ata_host *host; 277 u8 *reg_base; 278 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */ 279 int irq_dma; 280 }; 281 282 #define SATA_DWC_QCMD_MAX 32 283 284 struct sata_dwc_device_port { 285 struct sata_dwc_device *hsdev; 286 int cmd_issued[SATA_DWC_QCMD_MAX]; 287 struct lli *llit[SATA_DWC_QCMD_MAX]; /* DMA LLI table */ 288 dma_addr_t llit_dma[SATA_DWC_QCMD_MAX]; 289 u32 dma_chan[SATA_DWC_QCMD_MAX]; 290 int dma_pending[SATA_DWC_QCMD_MAX]; 291 }; 292 293 /* 294 * Commonly used DWC SATA driver Macros 295 */ 296 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\ 297 (host)->private_data) 298 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\ 299 (ap)->host->private_data) 300 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\ 301 (ap)->private_data) 302 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\ 303 (qc)->ap->host->private_data) 304 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\ 305 (hsdevp)->hsdev) 306 307 enum { 308 SATA_DWC_CMD_ISSUED_NOT = 0, 309 SATA_DWC_CMD_ISSUED_PEND = 1, 310 SATA_DWC_CMD_ISSUED_EXEC = 2, 311 SATA_DWC_CMD_ISSUED_NODATA = 3, 312 313 SATA_DWC_DMA_PENDING_NONE = 0, 314 SATA_DWC_DMA_PENDING_TX = 1, 315 SATA_DWC_DMA_PENDING_RX = 2, 316 }; 317 318 struct sata_dwc_host_priv { 319 void __iomem *scr_addr_sstatus; 320 u32 sata_dwc_sactive_issued ; 321 u32 sata_dwc_sactive_queued ; 322 u32 dma_interrupt_count; 323 struct ahb_dma_regs *sata_dma_regs; 324 struct device *dwc_dev; 325 int dma_channel; 326 }; 327 struct sata_dwc_host_priv host_pvt; 328 /* 329 * Prototypes 330 */ 331 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag); 332 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc, 333 u32 check_status); 334 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status); 335 static void sata_dwc_port_stop(struct ata_port *ap); 336 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag); 337 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq); 338 static void dma_dwc_exit(struct sata_dwc_device *hsdev); 339 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems, 340 struct lli *lli, dma_addr_t dma_lli, 341 void __iomem *addr, int dir); 342 static void dma_dwc_xfer_start(int dma_ch); 343 344 static const char *get_prot_descript(u8 protocol) 345 { 346 switch ((enum ata_tf_protocols)protocol) { 347 case ATA_PROT_NODATA: 348 return "ATA no data"; 349 case ATA_PROT_PIO: 350 return "ATA PIO"; 351 case ATA_PROT_DMA: 352 return "ATA DMA"; 353 case ATA_PROT_NCQ: 354 return "ATA NCQ"; 355 case ATAPI_PROT_NODATA: 356 return "ATAPI no data"; 357 case ATAPI_PROT_PIO: 358 return "ATAPI PIO"; 359 case ATAPI_PROT_DMA: 360 return "ATAPI DMA"; 361 default: 362 return "unknown"; 363 } 364 } 365 366 static const char *get_dma_dir_descript(int dma_dir) 367 { 368 switch ((enum dma_data_direction)dma_dir) { 369 case DMA_BIDIRECTIONAL: 370 return "bidirectional"; 371 case DMA_TO_DEVICE: 372 return "to device"; 373 case DMA_FROM_DEVICE: 374 return "from device"; 375 default: 376 return "none"; 377 } 378 } 379 380 static void sata_dwc_tf_dump(struct ata_taskfile *tf) 381 { 382 dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:" 383 "0x%lx device: %x\n", tf->command, 384 get_prot_descript(tf->protocol), tf->flags, tf->device); 385 dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x " 386 "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal, 387 tf->lbam, tf->lbah); 388 dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x " 389 "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n", 390 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam, 391 tf->hob_lbah); 392 } 393 394 /* 395 * Function: get_burst_length_encode 396 * arguments: datalength: length in bytes of data 397 * returns value to be programmed in register corresponding to data length 398 * This value is effectively the log(base 2) of the length 399 */ 400 static int get_burst_length_encode(int datalength) 401 { 402 int items = datalength >> 2; /* div by 4 to get lword count */ 403 404 if (items >= 64) 405 return 5; 406 407 if (items >= 32) 408 return 4; 409 410 if (items >= 16) 411 return 3; 412 413 if (items >= 8) 414 return 2; 415 416 if (items >= 4) 417 return 1; 418 419 return 0; 420 } 421 422 static void clear_chan_interrupts(int c) 423 { 424 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low), 425 DMA_CHANNEL(c)); 426 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low), 427 DMA_CHANNEL(c)); 428 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low), 429 DMA_CHANNEL(c)); 430 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low), 431 DMA_CHANNEL(c)); 432 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low), 433 DMA_CHANNEL(c)); 434 } 435 436 /* 437 * Function: dma_request_channel 438 * arguments: None 439 * returns channel number if available else -1 440 * This function assigns the next available DMA channel from the list to the 441 * requester 442 */ 443 static int dma_request_channel(void) 444 { 445 /* Check if the channel is not currently in use */ 446 if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) & 447 DMA_CHANNEL(host_pvt.dma_channel))) 448 return host_pvt.dma_channel; 449 dev_err(host_pvt.dwc_dev, "%s Channel %d is currently in use\n", 450 __func__, host_pvt.dma_channel); 451 return -1; 452 } 453 454 /* 455 * Function: dma_dwc_interrupt 456 * arguments: irq, dev_id, pt_regs 457 * returns channel number if available else -1 458 * Interrupt Handler for DW AHB SATA DMA 459 */ 460 static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance) 461 { 462 int chan; 463 u32 tfr_reg, err_reg; 464 unsigned long flags; 465 struct sata_dwc_device *hsdev = 466 (struct sata_dwc_device *)hsdev_instance; 467 struct ata_host *host = (struct ata_host *)hsdev->host; 468 struct ata_port *ap; 469 struct sata_dwc_device_port *hsdevp; 470 u8 tag = 0; 471 unsigned int port = 0; 472 473 spin_lock_irqsave(&host->lock, flags); 474 ap = host->ports[port]; 475 hsdevp = HSDEVP_FROM_AP(ap); 476 tag = ap->link.active_tag; 477 478 tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\ 479 .low)); 480 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\ 481 .low)); 482 483 dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n", 484 tfr_reg, err_reg, hsdevp->dma_pending[tag], port); 485 486 chan = host_pvt.dma_channel; 487 if (chan >= 0) { 488 /* Check for end-of-transfer interrupt. */ 489 if (tfr_reg & DMA_CHANNEL(chan)) { 490 /* 491 * Each DMA command produces 2 interrupts. Only 492 * complete the command after both interrupts have been 493 * seen. (See sata_dwc_isr()) 494 */ 495 host_pvt.dma_interrupt_count++; 496 sata_dwc_clear_dmacr(hsdevp, tag); 497 498 if (hsdevp->dma_pending[tag] == 499 SATA_DWC_DMA_PENDING_NONE) { 500 dev_err(ap->dev, "DMA not pending eot=0x%08x " 501 "err=0x%08x tag=0x%02x pending=%d\n", 502 tfr_reg, err_reg, tag, 503 hsdevp->dma_pending[tag]); 504 } 505 506 if ((host_pvt.dma_interrupt_count % 2) == 0) 507 sata_dwc_dma_xfer_complete(ap, 1); 508 509 /* Clear the interrupt */ 510 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\ 511 .tfr.low), 512 DMA_CHANNEL(chan)); 513 } 514 515 /* Check for error interrupt. */ 516 if (err_reg & DMA_CHANNEL(chan)) { 517 /* TODO Need error handler ! */ 518 dev_err(ap->dev, "error interrupt err_reg=0x%08x\n", 519 err_reg); 520 521 /* Clear the interrupt. */ 522 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\ 523 .error.low), 524 DMA_CHANNEL(chan)); 525 } 526 } 527 spin_unlock_irqrestore(&host->lock, flags); 528 return IRQ_HANDLED; 529 } 530 531 /* 532 * Function: dma_request_interrupts 533 * arguments: hsdev 534 * returns status 535 * This function registers ISR for a particular DMA channel interrupt 536 */ 537 static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq) 538 { 539 int retval = 0; 540 int chan = host_pvt.dma_channel; 541 542 if (chan >= 0) { 543 /* Unmask error interrupt */ 544 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low, 545 DMA_ENABLE_CHAN(chan)); 546 547 /* Unmask end-of-transfer interrupt */ 548 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low, 549 DMA_ENABLE_CHAN(chan)); 550 } 551 552 retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev); 553 if (retval) { 554 dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n", 555 __func__, irq); 556 return -ENODEV; 557 } 558 559 /* Mark this interrupt as requested */ 560 hsdev->irq_dma = irq; 561 return 0; 562 } 563 564 /* 565 * Function: map_sg_to_lli 566 * The Synopsis driver has a comment proposing that better performance 567 * is possible by only enabling interrupts on the last item in the linked list. 568 * However, it seems that could be a problem if an error happened on one of the 569 * first items. The transfer would halt, but no error interrupt would occur. 570 * Currently this function sets interrupts enabled for each linked list item: 571 * DMA_CTL_INT_EN. 572 */ 573 static int map_sg_to_lli(struct scatterlist *sg, int num_elems, 574 struct lli *lli, dma_addr_t dma_lli, 575 void __iomem *dmadr_addr, int dir) 576 { 577 int i, idx = 0; 578 int fis_len = 0; 579 dma_addr_t next_llp; 580 int bl; 581 int sms_val, dms_val; 582 583 sms_val = 0; 584 dms_val = 1 + host_pvt.dma_channel; 585 dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x" 586 " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli, 587 (u32)dmadr_addr); 588 589 bl = get_burst_length_encode(AHB_DMA_BRST_DFLT); 590 591 for (i = 0; i < num_elems; i++, sg++) { 592 u32 addr, offset; 593 u32 sg_len, len; 594 595 addr = (u32) sg_dma_address(sg); 596 sg_len = sg_dma_len(sg); 597 598 dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len" 599 "=%d\n", __func__, i, addr, sg_len); 600 601 while (sg_len) { 602 if (idx >= SATA_DWC_DMAC_LLI_NUM) { 603 /* The LLI table is not large enough. */ 604 dev_err(host_pvt.dwc_dev, "LLI table overrun " 605 "(idx=%d)\n", idx); 606 break; 607 } 608 len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ? 609 SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len; 610 611 offset = addr & 0xffff; 612 if ((offset + sg_len) > 0x10000) 613 len = 0x10000 - offset; 614 615 /* 616 * Make sure a LLI block is not created that will span 617 * 8K max FIS boundary. If the block spans such a FIS 618 * boundary, there is a chance that a DMA burst will 619 * cross that boundary -- this results in an error in 620 * the host controller. 621 */ 622 if (fis_len + len > 8192) { 623 dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len=" 624 "%d(0x%x) len=%d(0x%x)\n", fis_len, 625 fis_len, len, len); 626 len = 8192 - fis_len; 627 fis_len = 0; 628 } else { 629 fis_len += len; 630 } 631 if (fis_len == 8192) 632 fis_len = 0; 633 634 /* 635 * Set DMA addresses and lower half of control register 636 * based on direction. 637 */ 638 if (dir == DMA_FROM_DEVICE) { 639 lli[idx].dar = cpu_to_le32(addr); 640 lli[idx].sar = cpu_to_le32((u32)dmadr_addr); 641 642 lli[idx].ctl.low = cpu_to_le32( 643 DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) | 644 DMA_CTL_SMS(sms_val) | 645 DMA_CTL_DMS(dms_val) | 646 DMA_CTL_SRC_MSIZE(bl) | 647 DMA_CTL_DST_MSIZE(bl) | 648 DMA_CTL_SINC_NOCHANGE | 649 DMA_CTL_SRC_TRWID(2) | 650 DMA_CTL_DST_TRWID(2) | 651 DMA_CTL_INT_EN | 652 DMA_CTL_LLP_SRCEN | 653 DMA_CTL_LLP_DSTEN); 654 } else { /* DMA_TO_DEVICE */ 655 lli[idx].sar = cpu_to_le32(addr); 656 lli[idx].dar = cpu_to_le32((u32)dmadr_addr); 657 658 lli[idx].ctl.low = cpu_to_le32( 659 DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) | 660 DMA_CTL_SMS(dms_val) | 661 DMA_CTL_DMS(sms_val) | 662 DMA_CTL_SRC_MSIZE(bl) | 663 DMA_CTL_DST_MSIZE(bl) | 664 DMA_CTL_DINC_NOCHANGE | 665 DMA_CTL_SRC_TRWID(2) | 666 DMA_CTL_DST_TRWID(2) | 667 DMA_CTL_INT_EN | 668 DMA_CTL_LLP_SRCEN | 669 DMA_CTL_LLP_DSTEN); 670 } 671 672 dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: " 673 "0x%08x val: 0x%08x\n", __func__, 674 len, DMA_CTL_BLK_TS(len / 4)); 675 676 /* Program the LLI CTL high register */ 677 lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\ 678 (len / 4)); 679 680 /* Program the next pointer. The next pointer must be 681 * the physical address, not the virtual address. 682 */ 683 next_llp = (dma_lli + ((idx + 1) * sizeof(struct \ 684 lli))); 685 686 /* The last 2 bits encode the list master select. */ 687 next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2); 688 689 lli[idx].llp = cpu_to_le32(next_llp); 690 idx++; 691 sg_len -= len; 692 addr += len; 693 } 694 } 695 696 /* 697 * The last next ptr has to be zero and the last control low register 698 * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source 699 * and destination enable) set back to 0 (disabled.) This is what tells 700 * the core that this is the last item in the linked list. 701 */ 702 if (idx) { 703 lli[idx-1].llp = 0x00000000; 704 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32; 705 706 /* Flush cache to memory */ 707 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx), 708 DMA_BIDIRECTIONAL); 709 } 710 711 return idx; 712 } 713 714 /* 715 * Function: dma_dwc_xfer_start 716 * arguments: Channel number 717 * Return : None 718 * Enables the DMA channel 719 */ 720 static void dma_dwc_xfer_start(int dma_ch) 721 { 722 /* Enable the DMA channel */ 723 out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low), 724 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) | 725 DMA_ENABLE_CHAN(dma_ch)); 726 } 727 728 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems, 729 struct lli *lli, dma_addr_t dma_lli, 730 void __iomem *addr, int dir) 731 { 732 int dma_ch; 733 int num_lli; 734 /* Acquire DMA channel */ 735 dma_ch = dma_request_channel(); 736 if (dma_ch == -1) { 737 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n", 738 __func__); 739 return -EAGAIN; 740 } 741 742 /* Convert SG list to linked list of items (LLIs) for AHB DMA */ 743 num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir); 744 745 dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:" 746 " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems, 747 lli, (u32)dma_lli, addr, num_lli); 748 749 clear_chan_interrupts(dma_ch); 750 751 /* Program the CFG register. */ 752 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high), 753 DMA_CFG_HW_HS_SRC(dma_ch) | DMA_CFG_HW_HS_DEST(dma_ch) | 754 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ); 755 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low), 756 DMA_CFG_HW_CH_PRIOR(dma_ch)); 757 758 /* Program the address of the linked list */ 759 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low), 760 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2)); 761 762 /* Program the CTL register with src enable / dst enable */ 763 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low), 764 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN); 765 return dma_ch; 766 } 767 768 /* 769 * Function: dma_dwc_exit 770 * arguments: None 771 * returns status 772 * This function exits the SATA DMA driver 773 */ 774 static void dma_dwc_exit(struct sata_dwc_device *hsdev) 775 { 776 dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__); 777 if (host_pvt.sata_dma_regs) { 778 iounmap(host_pvt.sata_dma_regs); 779 host_pvt.sata_dma_regs = NULL; 780 } 781 782 if (hsdev->irq_dma) { 783 free_irq(hsdev->irq_dma, hsdev); 784 hsdev->irq_dma = 0; 785 } 786 } 787 788 /* 789 * Function: dma_dwc_init 790 * arguments: hsdev 791 * returns status 792 * This function initializes the SATA DMA driver 793 */ 794 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq) 795 { 796 int err; 797 798 err = dma_request_interrupts(hsdev, irq); 799 if (err) { 800 dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns" 801 " %d\n", __func__, err); 802 goto error_out; 803 } 804 805 /* Enabe DMA */ 806 out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN); 807 808 dev_notice(host_pvt.dwc_dev, "DMA initialized\n"); 809 dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\ 810 sata_dma_regs); 811 812 return 0; 813 814 error_out: 815 dma_dwc_exit(hsdev); 816 817 return err; 818 } 819 820 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val) 821 { 822 if (scr > SCR_NOTIFICATION) { 823 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n", 824 __func__, scr); 825 return -EINVAL; 826 } 827 828 *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4)); 829 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n", 830 __func__, link->ap->print_id, scr, *val); 831 832 return 0; 833 } 834 835 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val) 836 { 837 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n", 838 __func__, link->ap->print_id, scr, val); 839 if (scr > SCR_NOTIFICATION) { 840 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n", 841 __func__, scr); 842 return -EINVAL; 843 } 844 out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val); 845 846 return 0; 847 } 848 849 static u32 core_scr_read(unsigned int scr) 850 { 851 return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\ 852 (scr * 4)); 853 } 854 855 static void core_scr_write(unsigned int scr, u32 val) 856 { 857 out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4), 858 val); 859 } 860 861 static void clear_serror(void) 862 { 863 u32 val; 864 val = core_scr_read(SCR_ERROR); 865 core_scr_write(SCR_ERROR, val); 866 867 } 868 869 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit) 870 { 871 out_le32(&hsdev->sata_dwc_regs->intpr, 872 in_le32(&hsdev->sata_dwc_regs->intpr)); 873 } 874 875 static u32 qcmd_tag_to_mask(u8 tag) 876 { 877 return 0x00000001 << (tag & 0x1f); 878 } 879 880 /* See ahci.c */ 881 static void sata_dwc_error_intr(struct ata_port *ap, 882 struct sata_dwc_device *hsdev, uint intpr) 883 { 884 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); 885 struct ata_eh_info *ehi = &ap->link.eh_info; 886 unsigned int err_mask = 0, action = 0; 887 struct ata_queued_cmd *qc; 888 u32 serror; 889 u8 status, tag; 890 u32 err_reg; 891 892 ata_ehi_clear_desc(ehi); 893 894 serror = core_scr_read(SCR_ERROR); 895 status = ap->ops->sff_check_status(ap); 896 897 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\ 898 low)); 899 tag = ap->link.active_tag; 900 901 dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x " 902 "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n", 903 __func__, serror, intpr, status, host_pvt.dma_interrupt_count, 904 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg); 905 906 /* Clear error register and interrupt bit */ 907 clear_serror(); 908 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR); 909 910 /* This is the only error happening now. TODO check for exact error */ 911 912 err_mask |= AC_ERR_HOST_BUS; 913 action |= ATA_EH_RESET; 914 915 /* Pass this on to EH */ 916 ehi->serror |= serror; 917 ehi->action |= action; 918 919 qc = ata_qc_from_tag(ap, tag); 920 if (qc) 921 qc->err_mask |= err_mask; 922 else 923 ehi->err_mask |= err_mask; 924 925 ata_port_abort(ap); 926 } 927 928 /* 929 * Function : sata_dwc_isr 930 * arguments : irq, void *dev_instance, struct pt_regs *regs 931 * Return value : irqreturn_t - status of IRQ 932 * This Interrupt handler called via port ops registered function. 933 * .irq_handler = sata_dwc_isr 934 */ 935 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance) 936 { 937 struct ata_host *host = (struct ata_host *)dev_instance; 938 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host); 939 struct ata_port *ap; 940 struct ata_queued_cmd *qc; 941 unsigned long flags; 942 u8 status, tag; 943 int handled, num_processed, port = 0; 944 uint intpr, sactive, sactive2, tag_mask; 945 struct sata_dwc_device_port *hsdevp; 946 host_pvt.sata_dwc_sactive_issued = 0; 947 948 spin_lock_irqsave(&host->lock, flags); 949 950 /* Read the interrupt register */ 951 intpr = in_le32(&hsdev->sata_dwc_regs->intpr); 952 953 ap = host->ports[port]; 954 hsdevp = HSDEVP_FROM_AP(ap); 955 956 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr, 957 ap->link.active_tag); 958 959 /* Check for error interrupt */ 960 if (intpr & SATA_DWC_INTPR_ERR) { 961 sata_dwc_error_intr(ap, hsdev, intpr); 962 handled = 1; 963 goto DONE; 964 } 965 966 /* Check for DMA SETUP FIS (FP DMA) interrupt */ 967 if (intpr & SATA_DWC_INTPR_NEWFP) { 968 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP); 969 970 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr)); 971 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag); 972 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND) 973 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag); 974 975 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag); 976 977 qc = ata_qc_from_tag(ap, tag); 978 /* 979 * Start FP DMA for NCQ command. At this point the tag is the 980 * active tag. It is the tag that matches the command about to 981 * be completed. 982 */ 983 qc->ap->link.active_tag = tag; 984 sata_dwc_bmdma_start_by_tag(qc, tag); 985 986 handled = 1; 987 goto DONE; 988 } 989 sactive = core_scr_read(SCR_ACTIVE); 990 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive; 991 992 /* If no sactive issued and tag_mask is zero then this is not NCQ */ 993 if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) { 994 if (ap->link.active_tag == ATA_TAG_POISON) 995 tag = 0; 996 else 997 tag = ap->link.active_tag; 998 qc = ata_qc_from_tag(ap, tag); 999 1000 /* DEV interrupt w/ no active qc? */ 1001 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { 1002 dev_err(ap->dev, "%s interrupt with no active qc " 1003 "qc=%p\n", __func__, qc); 1004 ap->ops->sff_check_status(ap); 1005 handled = 1; 1006 goto DONE; 1007 } 1008 status = ap->ops->sff_check_status(ap); 1009 1010 qc->ap->link.active_tag = tag; 1011 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT; 1012 1013 if (status & ATA_ERR) { 1014 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status); 1015 sata_dwc_qc_complete(ap, qc, 1); 1016 handled = 1; 1017 goto DONE; 1018 } 1019 1020 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n", 1021 __func__, get_prot_descript(qc->tf.protocol)); 1022 DRVSTILLBUSY: 1023 if (ata_is_dma(qc->tf.protocol)) { 1024 /* 1025 * Each DMA transaction produces 2 interrupts. The DMAC 1026 * transfer complete interrupt and the SATA controller 1027 * operation done interrupt. The command should be 1028 * completed only after both interrupts are seen. 1029 */ 1030 host_pvt.dma_interrupt_count++; 1031 if (hsdevp->dma_pending[tag] == \ 1032 SATA_DWC_DMA_PENDING_NONE) { 1033 dev_err(ap->dev, "%s: DMA not pending " 1034 "intpr=0x%08x status=0x%08x pending" 1035 "=%d\n", __func__, intpr, status, 1036 hsdevp->dma_pending[tag]); 1037 } 1038 1039 if ((host_pvt.dma_interrupt_count % 2) == 0) 1040 sata_dwc_dma_xfer_complete(ap, 1); 1041 } else if (ata_is_pio(qc->tf.protocol)) { 1042 ata_sff_hsm_move(ap, qc, status, 0); 1043 handled = 1; 1044 goto DONE; 1045 } else { 1046 if (unlikely(sata_dwc_qc_complete(ap, qc, 1))) 1047 goto DRVSTILLBUSY; 1048 } 1049 1050 handled = 1; 1051 goto DONE; 1052 } 1053 1054 /* 1055 * This is a NCQ command. At this point we need to figure out for which 1056 * tags we have gotten a completion interrupt. One interrupt may serve 1057 * as completion for more than one operation when commands are queued 1058 * (NCQ). We need to process each completed command. 1059 */ 1060 1061 /* process completed commands */ 1062 sactive = core_scr_read(SCR_ACTIVE); 1063 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive; 1064 1065 if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \ 1066 tag_mask > 1) { 1067 dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x sactive_issued=0x%08x" 1068 "tag_mask=0x%08x\n", __func__, sactive, 1069 host_pvt.sata_dwc_sactive_issued, tag_mask); 1070 } 1071 1072 if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \ 1073 (host_pvt.sata_dwc_sactive_issued)) { 1074 dev_warn(ap->dev, "Bad tag mask? sactive=0x%08x " 1075 "(host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask" 1076 "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued, 1077 tag_mask); 1078 } 1079 1080 /* read just to clear ... not bad if currently still busy */ 1081 status = ap->ops->sff_check_status(ap); 1082 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status); 1083 1084 tag = 0; 1085 num_processed = 0; 1086 while (tag_mask) { 1087 num_processed++; 1088 while (!(tag_mask & 0x00000001)) { 1089 tag++; 1090 tag_mask <<= 1; 1091 } 1092 1093 tag_mask &= (~0x00000001); 1094 qc = ata_qc_from_tag(ap, tag); 1095 1096 /* To be picked up by completion functions */ 1097 qc->ap->link.active_tag = tag; 1098 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT; 1099 1100 /* Let libata/scsi layers handle error */ 1101 if (status & ATA_ERR) { 1102 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__, 1103 status); 1104 sata_dwc_qc_complete(ap, qc, 1); 1105 handled = 1; 1106 goto DONE; 1107 } 1108 1109 /* Process completed command */ 1110 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__, 1111 get_prot_descript(qc->tf.protocol)); 1112 if (ata_is_dma(qc->tf.protocol)) { 1113 host_pvt.dma_interrupt_count++; 1114 if (hsdevp->dma_pending[tag] == \ 1115 SATA_DWC_DMA_PENDING_NONE) 1116 dev_warn(ap->dev, "%s: DMA not pending?\n", 1117 __func__); 1118 if ((host_pvt.dma_interrupt_count % 2) == 0) 1119 sata_dwc_dma_xfer_complete(ap, 1); 1120 } else { 1121 if (unlikely(sata_dwc_qc_complete(ap, qc, 1))) 1122 goto STILLBUSY; 1123 } 1124 continue; 1125 1126 STILLBUSY: 1127 ap->stats.idle_irq++; 1128 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n", 1129 ap->print_id); 1130 } /* while tag_mask */ 1131 1132 /* 1133 * Check to see if any commands completed while we were processing our 1134 * initial set of completed commands (read status clears interrupts, 1135 * so we might miss a completed command interrupt if one came in while 1136 * we were processing --we read status as part of processing a completed 1137 * command). 1138 */ 1139 sactive2 = core_scr_read(SCR_ACTIVE); 1140 if (sactive2 != sactive) { 1141 dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2" 1142 "=0x%x\n", sactive, sactive2); 1143 } 1144 handled = 1; 1145 1146 DONE: 1147 spin_unlock_irqrestore(&host->lock, flags); 1148 return IRQ_RETVAL(handled); 1149 } 1150 1151 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag) 1152 { 1153 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp); 1154 1155 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) { 1156 out_le32(&(hsdev->sata_dwc_regs->dmacr), 1157 SATA_DWC_DMACR_RX_CLEAR( 1158 in_le32(&(hsdev->sata_dwc_regs->dmacr)))); 1159 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) { 1160 out_le32(&(hsdev->sata_dwc_regs->dmacr), 1161 SATA_DWC_DMACR_TX_CLEAR( 1162 in_le32(&(hsdev->sata_dwc_regs->dmacr)))); 1163 } else { 1164 /* 1165 * This should not happen, it indicates the driver is out of 1166 * sync. If it does happen, clear dmacr anyway. 1167 */ 1168 dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and" 1169 "TX DMA not pending tag=0x%02x pending=%d" 1170 " dmacr: 0x%08x\n", __func__, tag, 1171 hsdevp->dma_pending[tag], 1172 in_le32(&(hsdev->sata_dwc_regs->dmacr))); 1173 out_le32(&(hsdev->sata_dwc_regs->dmacr), 1174 SATA_DWC_DMACR_TXRXCH_CLEAR); 1175 } 1176 } 1177 1178 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status) 1179 { 1180 struct ata_queued_cmd *qc; 1181 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); 1182 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap); 1183 u8 tag = 0; 1184 1185 tag = ap->link.active_tag; 1186 qc = ata_qc_from_tag(ap, tag); 1187 if (!qc) { 1188 dev_err(ap->dev, "failed to get qc"); 1189 return; 1190 } 1191 1192 #ifdef DEBUG_NCQ 1193 if (tag > 0) { 1194 dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s " 1195 "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command, 1196 get_dma_dir_descript(qc->dma_dir), 1197 get_prot_descript(qc->tf.protocol), 1198 in_le32(&(hsdev->sata_dwc_regs->dmacr))); 1199 } 1200 #endif 1201 1202 if (ata_is_dma(qc->tf.protocol)) { 1203 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) { 1204 dev_err(ap->dev, "%s DMA protocol RX and TX DMA not " 1205 "pending dmacr: 0x%08x\n", __func__, 1206 in_le32(&(hsdev->sata_dwc_regs->dmacr))); 1207 } 1208 1209 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE; 1210 sata_dwc_qc_complete(ap, qc, check_status); 1211 ap->link.active_tag = ATA_TAG_POISON; 1212 } else { 1213 sata_dwc_qc_complete(ap, qc, check_status); 1214 } 1215 } 1216 1217 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc, 1218 u32 check_status) 1219 { 1220 u8 status = 0; 1221 u32 mask = 0x0; 1222 u8 tag = qc->tag; 1223 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); 1224 host_pvt.sata_dwc_sactive_queued = 0; 1225 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status); 1226 1227 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) 1228 dev_err(ap->dev, "TX DMA PENDING\n"); 1229 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) 1230 dev_err(ap->dev, "RX DMA PENDING\n"); 1231 dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:" 1232 " protocol=%d\n", qc->tf.command, status, ap->print_id, 1233 qc->tf.protocol); 1234 1235 /* clear active bit */ 1236 mask = (~(qcmd_tag_to_mask(tag))); 1237 host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \ 1238 & mask; 1239 host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \ 1240 & mask; 1241 ata_qc_complete(qc); 1242 return 0; 1243 } 1244 1245 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev) 1246 { 1247 /* Enable selective interrupts by setting the interrupt maskregister*/ 1248 out_le32(&hsdev->sata_dwc_regs->intmr, 1249 SATA_DWC_INTMR_ERRM | 1250 SATA_DWC_INTMR_NEWFPM | 1251 SATA_DWC_INTMR_PMABRTM | 1252 SATA_DWC_INTMR_DMATM); 1253 /* 1254 * Unmask the error bits that should trigger an error interrupt by 1255 * setting the error mask register. 1256 */ 1257 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS); 1258 1259 dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n", 1260 __func__, in_le32(&hsdev->sata_dwc_regs->intmr), 1261 in_le32(&hsdev->sata_dwc_regs->errmr)); 1262 } 1263 1264 static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base) 1265 { 1266 port->cmd_addr = (void *)base + 0x00; 1267 port->data_addr = (void *)base + 0x00; 1268 1269 port->error_addr = (void *)base + 0x04; 1270 port->feature_addr = (void *)base + 0x04; 1271 1272 port->nsect_addr = (void *)base + 0x08; 1273 1274 port->lbal_addr = (void *)base + 0x0c; 1275 port->lbam_addr = (void *)base + 0x10; 1276 port->lbah_addr = (void *)base + 0x14; 1277 1278 port->device_addr = (void *)base + 0x18; 1279 port->command_addr = (void *)base + 0x1c; 1280 port->status_addr = (void *)base + 0x1c; 1281 1282 port->altstatus_addr = (void *)base + 0x20; 1283 port->ctl_addr = (void *)base + 0x20; 1284 } 1285 1286 /* 1287 * Function : sata_dwc_port_start 1288 * arguments : struct ata_ioports *port 1289 * Return value : returns 0 if success, error code otherwise 1290 * This function allocates the scatter gather LLI table for AHB DMA 1291 */ 1292 static int sata_dwc_port_start(struct ata_port *ap) 1293 { 1294 int err = 0; 1295 struct sata_dwc_device *hsdev; 1296 struct sata_dwc_device_port *hsdevp = NULL; 1297 struct device *pdev; 1298 int i; 1299 1300 hsdev = HSDEV_FROM_AP(ap); 1301 1302 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no); 1303 1304 hsdev->host = ap->host; 1305 pdev = ap->host->dev; 1306 if (!pdev) { 1307 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__); 1308 err = -ENODEV; 1309 goto CLEANUP; 1310 } 1311 1312 /* Allocate Port Struct */ 1313 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL); 1314 if (!hsdevp) { 1315 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__); 1316 err = -ENOMEM; 1317 goto CLEANUP; 1318 } 1319 hsdevp->hsdev = hsdev; 1320 1321 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) 1322 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT; 1323 1324 ap->bmdma_prd = 0; /* set these so libata doesn't use them */ 1325 ap->bmdma_prd_dma = 0; 1326 1327 /* 1328 * DMA - Assign scatter gather LLI table. We can't use the libata 1329 * version since it's PRD is IDE PCI specific. 1330 */ 1331 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) { 1332 hsdevp->llit[i] = dma_alloc_coherent(pdev, 1333 SATA_DWC_DMAC_LLI_TBL_SZ, 1334 &(hsdevp->llit_dma[i]), 1335 GFP_ATOMIC); 1336 if (!hsdevp->llit[i]) { 1337 dev_err(ap->dev, "%s: dma_alloc_coherent failed\n", 1338 __func__); 1339 err = -ENOMEM; 1340 goto CLEANUP_ALLOC; 1341 } 1342 } 1343 1344 if (ap->port_no == 0) { 1345 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n", 1346 __func__); 1347 out_le32(&hsdev->sata_dwc_regs->dmacr, 1348 SATA_DWC_DMACR_TXRXCH_CLEAR); 1349 1350 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n", 1351 __func__); 1352 out_le32(&hsdev->sata_dwc_regs->dbtsr, 1353 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) | 1354 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT))); 1355 } 1356 1357 /* Clear any error bits before libata starts issuing commands */ 1358 clear_serror(); 1359 ap->private_data = hsdevp; 1360 dev_dbg(ap->dev, "%s: done\n", __func__); 1361 return 0; 1362 1363 CLEANUP_ALLOC: 1364 kfree(hsdevp); 1365 CLEANUP: 1366 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id); 1367 return err; 1368 } 1369 1370 static void sata_dwc_port_stop(struct ata_port *ap) 1371 { 1372 int i; 1373 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap); 1374 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); 1375 1376 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id); 1377 1378 if (hsdevp && hsdev) { 1379 /* deallocate LLI table */ 1380 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) { 1381 dma_free_coherent(ap->host->dev, 1382 SATA_DWC_DMAC_LLI_TBL_SZ, 1383 hsdevp->llit[i], hsdevp->llit_dma[i]); 1384 } 1385 1386 kfree(hsdevp); 1387 } 1388 ap->private_data = NULL; 1389 } 1390 1391 /* 1392 * Function : sata_dwc_exec_command_by_tag 1393 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued 1394 * Return value : None 1395 * This function keeps track of individual command tag ids and calls 1396 * ata_exec_command in libata 1397 */ 1398 static void sata_dwc_exec_command_by_tag(struct ata_port *ap, 1399 struct ata_taskfile *tf, 1400 u8 tag, u32 cmd_issued) 1401 { 1402 unsigned long flags; 1403 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); 1404 1405 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command, 1406 ata_get_cmd_descript(tf->command), tag); 1407 1408 spin_lock_irqsave(&ap->host->lock, flags); 1409 hsdevp->cmd_issued[tag] = cmd_issued; 1410 spin_unlock_irqrestore(&ap->host->lock, flags); 1411 /* 1412 * Clear SError before executing a new command. 1413 * sata_dwc_scr_write and read can not be used here. Clearing the PM 1414 * managed SError register for the disk needs to be done before the 1415 * task file is loaded. 1416 */ 1417 clear_serror(); 1418 ata_sff_exec_command(ap, tf); 1419 } 1420 1421 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag) 1422 { 1423 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag, 1424 SATA_DWC_CMD_ISSUED_PEND); 1425 } 1426 1427 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc) 1428 { 1429 u8 tag = qc->tag; 1430 1431 if (ata_is_ncq(qc->tf.protocol)) { 1432 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n", 1433 __func__, qc->ap->link.sactive, tag); 1434 } else { 1435 tag = 0; 1436 } 1437 sata_dwc_bmdma_setup_by_tag(qc, tag); 1438 } 1439 1440 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag) 1441 { 1442 int start_dma; 1443 u32 reg, dma_chan; 1444 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc); 1445 struct ata_port *ap = qc->ap; 1446 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); 1447 int dir = qc->dma_dir; 1448 dma_chan = hsdevp->dma_chan[tag]; 1449 1450 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) { 1451 start_dma = 1; 1452 if (dir == DMA_TO_DEVICE) 1453 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX; 1454 else 1455 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX; 1456 } else { 1457 dev_err(ap->dev, "%s: Command not pending cmd_issued=%d " 1458 "(tag=%d) DMA NOT started\n", __func__, 1459 hsdevp->cmd_issued[tag], tag); 1460 start_dma = 0; 1461 } 1462 1463 dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s " 1464 "start_dma? %x\n", __func__, qc, tag, qc->tf.command, 1465 get_dma_dir_descript(qc->dma_dir), start_dma); 1466 sata_dwc_tf_dump(&(qc->tf)); 1467 1468 if (start_dma) { 1469 reg = core_scr_read(SCR_ERROR); 1470 if (reg & SATA_DWC_SERROR_ERR_BITS) { 1471 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n", 1472 __func__, reg); 1473 } 1474 1475 if (dir == DMA_TO_DEVICE) 1476 out_le32(&hsdev->sata_dwc_regs->dmacr, 1477 SATA_DWC_DMACR_TXCHEN); 1478 else 1479 out_le32(&hsdev->sata_dwc_regs->dmacr, 1480 SATA_DWC_DMACR_RXCHEN); 1481 1482 /* Enable AHB DMA transfer on the specified channel */ 1483 dma_dwc_xfer_start(dma_chan); 1484 } 1485 } 1486 1487 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc) 1488 { 1489 u8 tag = qc->tag; 1490 1491 if (ata_is_ncq(qc->tf.protocol)) { 1492 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n", 1493 __func__, qc->ap->link.sactive, tag); 1494 } else { 1495 tag = 0; 1496 } 1497 dev_dbg(qc->ap->dev, "%s\n", __func__); 1498 sata_dwc_bmdma_start_by_tag(qc, tag); 1499 } 1500 1501 /* 1502 * Function : sata_dwc_qc_prep_by_tag 1503 * arguments : ata_queued_cmd *qc, u8 tag 1504 * Return value : None 1505 * qc_prep for a particular queued command based on tag 1506 */ 1507 static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag) 1508 { 1509 struct scatterlist *sg = qc->sg; 1510 struct ata_port *ap = qc->ap; 1511 int dma_chan; 1512 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap); 1513 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); 1514 1515 dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n", 1516 __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir), 1517 qc->n_elem); 1518 1519 dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag], 1520 hsdevp->llit_dma[tag], 1521 (void *__iomem)(&hsdev->sata_dwc_regs->\ 1522 dmadr), qc->dma_dir); 1523 if (dma_chan < 0) { 1524 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n", 1525 __func__, dma_chan); 1526 return; 1527 } 1528 hsdevp->dma_chan[tag] = dma_chan; 1529 } 1530 1531 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc) 1532 { 1533 u32 sactive; 1534 u8 tag = qc->tag; 1535 struct ata_port *ap = qc->ap; 1536 1537 #ifdef DEBUG_NCQ 1538 if (qc->tag > 0 || ap->link.sactive > 1) 1539 dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d " 1540 "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n", 1541 __func__, ap->print_id, qc->tf.command, 1542 ata_get_cmd_descript(qc->tf.command), 1543 qc->tag, get_prot_descript(qc->tf.protocol), 1544 ap->link.active_tag, ap->link.sactive); 1545 #endif 1546 1547 if (!ata_is_ncq(qc->tf.protocol)) 1548 tag = 0; 1549 sata_dwc_qc_prep_by_tag(qc, tag); 1550 1551 if (ata_is_ncq(qc->tf.protocol)) { 1552 sactive = core_scr_read(SCR_ACTIVE); 1553 sactive |= (0x00000001 << tag); 1554 core_scr_write(SCR_ACTIVE, sactive); 1555 1556 dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x " 1557 "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive, 1558 sactive); 1559 1560 ap->ops->sff_tf_load(ap, &qc->tf); 1561 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag, 1562 SATA_DWC_CMD_ISSUED_PEND); 1563 } else { 1564 ata_sff_qc_issue(qc); 1565 } 1566 return 0; 1567 } 1568 1569 /* 1570 * Function : sata_dwc_qc_prep 1571 * arguments : ata_queued_cmd *qc 1572 * Return value : None 1573 * qc_prep for a particular queued command 1574 */ 1575 1576 static void sata_dwc_qc_prep(struct ata_queued_cmd *qc) 1577 { 1578 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO)) 1579 return; 1580 1581 #ifdef DEBUG_NCQ 1582 if (qc->tag > 0) 1583 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n", 1584 __func__, qc->tag, qc->ap->link.active_tag); 1585 1586 return ; 1587 #endif 1588 } 1589 1590 static void sata_dwc_error_handler(struct ata_port *ap) 1591 { 1592 ata_sff_error_handler(ap); 1593 } 1594 1595 int sata_dwc_hardreset(struct ata_link *link, unsigned int *class, 1596 unsigned long deadline) 1597 { 1598 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap); 1599 int ret; 1600 1601 ret = sata_sff_hardreset(link, class, deadline); 1602 1603 sata_dwc_enable_interrupts(hsdev); 1604 1605 /* Reconfigure the DMA control register */ 1606 out_le32(&hsdev->sata_dwc_regs->dmacr, 1607 SATA_DWC_DMACR_TXRXCH_CLEAR); 1608 1609 /* Reconfigure the DMA Burst Transaction Size register */ 1610 out_le32(&hsdev->sata_dwc_regs->dbtsr, 1611 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) | 1612 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)); 1613 1614 return ret; 1615 } 1616 1617 /* 1618 * scsi mid-layer and libata interface structures 1619 */ 1620 static struct scsi_host_template sata_dwc_sht = { 1621 ATA_NCQ_SHT(DRV_NAME), 1622 /* 1623 * test-only: Currently this driver doesn't handle NCQ 1624 * correctly. We enable NCQ but set the queue depth to a 1625 * max of 1. This will get fixed in in a future release. 1626 */ 1627 .sg_tablesize = LIBATA_MAX_PRD, 1628 .can_queue = ATA_DEF_QUEUE, /* ATA_MAX_QUEUE */ 1629 .dma_boundary = ATA_DMA_BOUNDARY, 1630 }; 1631 1632 static struct ata_port_operations sata_dwc_ops = { 1633 .inherits = &ata_sff_port_ops, 1634 1635 .error_handler = sata_dwc_error_handler, 1636 .hardreset = sata_dwc_hardreset, 1637 1638 .qc_prep = sata_dwc_qc_prep, 1639 .qc_issue = sata_dwc_qc_issue, 1640 1641 .scr_read = sata_dwc_scr_read, 1642 .scr_write = sata_dwc_scr_write, 1643 1644 .port_start = sata_dwc_port_start, 1645 .port_stop = sata_dwc_port_stop, 1646 1647 .bmdma_setup = sata_dwc_bmdma_setup, 1648 .bmdma_start = sata_dwc_bmdma_start, 1649 }; 1650 1651 static const struct ata_port_info sata_dwc_port_info[] = { 1652 { 1653 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ, 1654 .pio_mask = ATA_PIO4, 1655 .udma_mask = ATA_UDMA6, 1656 .port_ops = &sata_dwc_ops, 1657 }, 1658 }; 1659 1660 static int sata_dwc_probe(struct platform_device *ofdev) 1661 { 1662 struct sata_dwc_device *hsdev; 1663 u32 idr, versionr; 1664 char *ver = (char *)&versionr; 1665 u8 *base = NULL; 1666 int err = 0; 1667 int irq, rc; 1668 struct ata_host *host; 1669 struct ata_port_info pi = sata_dwc_port_info[0]; 1670 const struct ata_port_info *ppi[] = { &pi, NULL }; 1671 struct device_node *np = ofdev->dev.of_node; 1672 u32 dma_chan; 1673 1674 /* Allocate DWC SATA device */ 1675 hsdev = kzalloc(sizeof(*hsdev), GFP_KERNEL); 1676 if (hsdev == NULL) { 1677 dev_err(&ofdev->dev, "kmalloc failed for hsdev\n"); 1678 err = -ENOMEM; 1679 goto error; 1680 } 1681 1682 if (of_property_read_u32(np, "dma-channel", &dma_chan)) { 1683 dev_warn(&ofdev->dev, "no dma-channel property set." 1684 " Use channel 0\n"); 1685 dma_chan = 0; 1686 } 1687 host_pvt.dma_channel = dma_chan; 1688 1689 /* Ioremap SATA registers */ 1690 base = of_iomap(ofdev->dev.of_node, 0); 1691 if (!base) { 1692 dev_err(&ofdev->dev, "ioremap failed for SATA register" 1693 " address\n"); 1694 err = -ENODEV; 1695 goto error_kmalloc; 1696 } 1697 hsdev->reg_base = base; 1698 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n"); 1699 1700 /* Synopsys DWC SATA specific Registers */ 1701 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET); 1702 1703 /* Allocate and fill host */ 1704 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS); 1705 if (!host) { 1706 dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n"); 1707 err = -ENOMEM; 1708 goto error_iomap; 1709 } 1710 1711 host->private_data = hsdev; 1712 1713 /* Setup port */ 1714 host->ports[0]->ioaddr.cmd_addr = base; 1715 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET; 1716 host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET; 1717 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base); 1718 1719 /* Read the ID and Version Registers */ 1720 idr = in_le32(&hsdev->sata_dwc_regs->idr); 1721 versionr = in_le32(&hsdev->sata_dwc_regs->versionr); 1722 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n", 1723 idr, ver[0], ver[1], ver[2]); 1724 1725 /* Get SATA DMA interrupt number */ 1726 irq = irq_of_parse_and_map(ofdev->dev.of_node, 1); 1727 if (irq == NO_IRQ) { 1728 dev_err(&ofdev->dev, "no SATA DMA irq\n"); 1729 err = -ENODEV; 1730 goto error_out; 1731 } 1732 1733 /* Get physical SATA DMA register base address */ 1734 host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1); 1735 if (!(host_pvt.sata_dma_regs)) { 1736 dev_err(&ofdev->dev, "ioremap failed for AHBDMA register" 1737 " address\n"); 1738 err = -ENODEV; 1739 goto error_out; 1740 } 1741 1742 /* Save dev for later use in dev_xxx() routines */ 1743 host_pvt.dwc_dev = &ofdev->dev; 1744 1745 /* Initialize AHB DMAC */ 1746 dma_dwc_init(hsdev, irq); 1747 1748 /* Enable SATA Interrupts */ 1749 sata_dwc_enable_interrupts(hsdev); 1750 1751 /* Get SATA interrupt number */ 1752 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1753 if (irq == NO_IRQ) { 1754 dev_err(&ofdev->dev, "no SATA DMA irq\n"); 1755 err = -ENODEV; 1756 goto error_out; 1757 } 1758 1759 /* 1760 * Now, register with libATA core, this will also initiate the 1761 * device discovery process, invoking our port_start() handler & 1762 * error_handler() to execute a dummy Softreset EH session 1763 */ 1764 rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht); 1765 1766 if (rc != 0) 1767 dev_err(&ofdev->dev, "failed to activate host"); 1768 1769 dev_set_drvdata(&ofdev->dev, host); 1770 return 0; 1771 1772 error_out: 1773 /* Free SATA DMA resources */ 1774 dma_dwc_exit(hsdev); 1775 1776 error_iomap: 1777 iounmap(base); 1778 error_kmalloc: 1779 kfree(hsdev); 1780 error: 1781 return err; 1782 } 1783 1784 static int sata_dwc_remove(struct platform_device *ofdev) 1785 { 1786 struct device *dev = &ofdev->dev; 1787 struct ata_host *host = dev_get_drvdata(dev); 1788 struct sata_dwc_device *hsdev = host->private_data; 1789 1790 ata_host_detach(host); 1791 dev_set_drvdata(dev, NULL); 1792 1793 /* Free SATA DMA resources */ 1794 dma_dwc_exit(hsdev); 1795 1796 iounmap(hsdev->reg_base); 1797 kfree(hsdev); 1798 kfree(host); 1799 dev_dbg(&ofdev->dev, "done\n"); 1800 return 0; 1801 } 1802 1803 static const struct of_device_id sata_dwc_match[] = { 1804 { .compatible = "amcc,sata-460ex", }, 1805 {} 1806 }; 1807 MODULE_DEVICE_TABLE(of, sata_dwc_match); 1808 1809 static struct platform_driver sata_dwc_driver = { 1810 .driver = { 1811 .name = DRV_NAME, 1812 .owner = THIS_MODULE, 1813 .of_match_table = sata_dwc_match, 1814 }, 1815 .probe = sata_dwc_probe, 1816 .remove = sata_dwc_remove, 1817 }; 1818 1819 module_platform_driver(sata_dwc_driver); 1820 1821 MODULE_LICENSE("GPL"); 1822 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>"); 1823 MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver"); 1824 MODULE_VERSION(DRV_VERSION); 1825