1 /* 2 * pdc_adma.c - Pacific Digital Corporation ADMA 3 * 4 * Maintained by: Mark Lord <mlord@pobox.com> 5 * 6 * Copyright 2005 Mark Lord 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * 23 * libata documentation is available via 'make {ps|pdf}docs', 24 * as Documentation/DocBook/libata.* 25 * 26 * 27 * Supports ATA disks in single-packet ADMA mode. 28 * Uses PIO for everything else. 29 * 30 * TODO: Use ADMA transfers for ATAPI devices, when possible. 31 * This requires careful attention to a number of quirks of the chip. 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/gfp.h> 38 #include <linux/pci.h> 39 #include <linux/init.h> 40 #include <linux/blkdev.h> 41 #include <linux/delay.h> 42 #include <linux/interrupt.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <linux/libata.h> 46 47 #define DRV_NAME "pdc_adma" 48 #define DRV_VERSION "1.0" 49 50 /* macro to calculate base address for ATA regs */ 51 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40)) 52 53 /* macro to calculate base address for ADMA regs */ 54 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20)) 55 56 /* macro to obtain addresses from ata_port */ 57 #define ADMA_PORT_REGS(ap) \ 58 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no) 59 60 enum { 61 ADMA_MMIO_BAR = 4, 62 63 ADMA_PORTS = 2, 64 ADMA_CPB_BYTES = 40, 65 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, 66 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, 67 68 ADMA_DMA_BOUNDARY = 0xffffffff, 69 70 /* global register offsets */ 71 ADMA_MODE_LOCK = 0x00c7, 72 73 /* per-channel register offsets */ 74 ADMA_CONTROL = 0x0000, /* ADMA control */ 75 ADMA_STATUS = 0x0002, /* ADMA status */ 76 ADMA_CPB_COUNT = 0x0004, /* CPB count */ 77 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ 78 ADMA_CPB_NEXT = 0x000c, /* next CPB address */ 79 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ 80 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ 81 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ 82 83 /* ADMA_CONTROL register bits */ 84 aNIEN = (1 << 8), /* irq mask: 1==masked */ 85 aGO = (1 << 7), /* packet trigger ("Go!") */ 86 aRSTADM = (1 << 5), /* ADMA logic reset */ 87 aPIOMD4 = 0x0003, /* PIO mode 4 */ 88 89 /* ADMA_STATUS register bits */ 90 aPSD = (1 << 6), 91 aUIRQ = (1 << 4), 92 aPERR = (1 << 0), 93 94 /* CPB bits */ 95 cDONE = (1 << 0), 96 cATERR = (1 << 3), 97 98 cVLD = (1 << 0), 99 cDAT = (1 << 2), 100 cIEN = (1 << 3), 101 102 /* PRD bits */ 103 pORD = (1 << 4), 104 pDIRO = (1 << 5), 105 pEND = (1 << 7), 106 107 /* ATA register flags */ 108 rIGN = (1 << 5), 109 rEND = (1 << 7), 110 111 /* ATA register addresses */ 112 ADMA_REGS_CONTROL = 0x0e, 113 ADMA_REGS_SECTOR_COUNT = 0x12, 114 ADMA_REGS_LBA_LOW = 0x13, 115 ADMA_REGS_LBA_MID = 0x14, 116 ADMA_REGS_LBA_HIGH = 0x15, 117 ADMA_REGS_DEVICE = 0x16, 118 ADMA_REGS_COMMAND = 0x17, 119 120 /* PCI device IDs */ 121 board_1841_idx = 0, /* ADMA 2-port controller */ 122 }; 123 124 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; 125 126 struct adma_port_priv { 127 u8 *pkt; 128 dma_addr_t pkt_dma; 129 adma_state_t state; 130 }; 131 132 static int adma_ata_init_one(struct pci_dev *pdev, 133 const struct pci_device_id *ent); 134 static int adma_port_start(struct ata_port *ap); 135 static void adma_port_stop(struct ata_port *ap); 136 static void adma_qc_prep(struct ata_queued_cmd *qc); 137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); 138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc); 139 static void adma_freeze(struct ata_port *ap); 140 static void adma_thaw(struct ata_port *ap); 141 static int adma_prereset(struct ata_link *link, unsigned long deadline); 142 143 static struct scsi_host_template adma_ata_sht = { 144 ATA_BASE_SHT(DRV_NAME), 145 .sg_tablesize = LIBATA_MAX_PRD, 146 .dma_boundary = ADMA_DMA_BOUNDARY, 147 }; 148 149 static struct ata_port_operations adma_ata_ops = { 150 .inherits = &ata_sff_port_ops, 151 152 .lost_interrupt = ATA_OP_NULL, 153 154 .check_atapi_dma = adma_check_atapi_dma, 155 .qc_prep = adma_qc_prep, 156 .qc_issue = adma_qc_issue, 157 158 .freeze = adma_freeze, 159 .thaw = adma_thaw, 160 .prereset = adma_prereset, 161 162 .port_start = adma_port_start, 163 .port_stop = adma_port_stop, 164 }; 165 166 static struct ata_port_info adma_port_info[] = { 167 /* board_1841_idx */ 168 { 169 .flags = ATA_FLAG_SLAVE_POSS | 170 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | 171 ATA_FLAG_PIO_POLLING, 172 .pio_mask = ATA_PIO4_ONLY, 173 .udma_mask = ATA_UDMA4, 174 .port_ops = &adma_ata_ops, 175 }, 176 }; 177 178 static const struct pci_device_id adma_ata_pci_tbl[] = { 179 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx }, 180 181 { } /* terminate list */ 182 }; 183 184 static struct pci_driver adma_ata_pci_driver = { 185 .name = DRV_NAME, 186 .id_table = adma_ata_pci_tbl, 187 .probe = adma_ata_init_one, 188 .remove = ata_pci_remove_one, 189 }; 190 191 static int adma_check_atapi_dma(struct ata_queued_cmd *qc) 192 { 193 return 1; /* ATAPI DMA not yet supported */ 194 } 195 196 static void adma_reset_engine(struct ata_port *ap) 197 { 198 void __iomem *chan = ADMA_PORT_REGS(ap); 199 200 /* reset ADMA to idle state */ 201 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); 202 udelay(2); 203 writew(aPIOMD4, chan + ADMA_CONTROL); 204 udelay(2); 205 } 206 207 static void adma_reinit_engine(struct ata_port *ap) 208 { 209 struct adma_port_priv *pp = ap->private_data; 210 void __iomem *chan = ADMA_PORT_REGS(ap); 211 212 /* mask/clear ATA interrupts */ 213 writeb(ATA_NIEN, ap->ioaddr.ctl_addr); 214 ata_sff_check_status(ap); 215 216 /* reset the ADMA engine */ 217 adma_reset_engine(ap); 218 219 /* set in-FIFO threshold to 0x100 */ 220 writew(0x100, chan + ADMA_FIFO_IN); 221 222 /* set CPB pointer */ 223 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); 224 225 /* set out-FIFO threshold to 0x100 */ 226 writew(0x100, chan + ADMA_FIFO_OUT); 227 228 /* set CPB count */ 229 writew(1, chan + ADMA_CPB_COUNT); 230 231 /* read/discard ADMA status */ 232 readb(chan + ADMA_STATUS); 233 } 234 235 static inline void adma_enter_reg_mode(struct ata_port *ap) 236 { 237 void __iomem *chan = ADMA_PORT_REGS(ap); 238 239 writew(aPIOMD4, chan + ADMA_CONTROL); 240 readb(chan + ADMA_STATUS); /* flush */ 241 } 242 243 static void adma_freeze(struct ata_port *ap) 244 { 245 void __iomem *chan = ADMA_PORT_REGS(ap); 246 247 /* mask/clear ATA interrupts */ 248 writeb(ATA_NIEN, ap->ioaddr.ctl_addr); 249 ata_sff_check_status(ap); 250 251 /* reset ADMA to idle state */ 252 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); 253 udelay(2); 254 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL); 255 udelay(2); 256 } 257 258 static void adma_thaw(struct ata_port *ap) 259 { 260 adma_reinit_engine(ap); 261 } 262 263 static int adma_prereset(struct ata_link *link, unsigned long deadline) 264 { 265 struct ata_port *ap = link->ap; 266 struct adma_port_priv *pp = ap->private_data; 267 268 if (pp->state != adma_state_idle) /* healthy paranoia */ 269 pp->state = adma_state_mmio; 270 adma_reinit_engine(ap); 271 272 return ata_sff_prereset(link, deadline); 273 } 274 275 static int adma_fill_sg(struct ata_queued_cmd *qc) 276 { 277 struct scatterlist *sg; 278 struct ata_port *ap = qc->ap; 279 struct adma_port_priv *pp = ap->private_data; 280 u8 *buf = pp->pkt, *last_buf = NULL; 281 int i = (2 + buf[3]) * 8; 282 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); 283 unsigned int si; 284 285 for_each_sg(qc->sg, sg, qc->n_elem, si) { 286 u32 addr; 287 u32 len; 288 289 addr = (u32)sg_dma_address(sg); 290 *(__le32 *)(buf + i) = cpu_to_le32(addr); 291 i += 4; 292 293 len = sg_dma_len(sg) >> 3; 294 *(__le32 *)(buf + i) = cpu_to_le32(len); 295 i += 4; 296 297 last_buf = &buf[i]; 298 buf[i++] = pFLAGS; 299 buf[i++] = qc->dev->dma_mode & 0xf; 300 buf[i++] = 0; /* pPKLW */ 301 buf[i++] = 0; /* reserved */ 302 303 *(__le32 *)(buf + i) = 304 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); 305 i += 4; 306 307 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, 308 (unsigned long)addr, len); 309 } 310 311 if (likely(last_buf)) 312 *last_buf |= pEND; 313 314 return i; 315 } 316 317 static void adma_qc_prep(struct ata_queued_cmd *qc) 318 { 319 struct adma_port_priv *pp = qc->ap->private_data; 320 u8 *buf = pp->pkt; 321 u32 pkt_dma = (u32)pp->pkt_dma; 322 int i = 0; 323 324 VPRINTK("ENTER\n"); 325 326 adma_enter_reg_mode(qc->ap); 327 if (qc->tf.protocol != ATA_PROT_DMA) 328 return; 329 330 buf[i++] = 0; /* Response flags */ 331 buf[i++] = 0; /* reserved */ 332 buf[i++] = cVLD | cDAT | cIEN; 333 i++; /* cLEN, gets filled in below */ 334 335 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ 336 i += 4; /* cNCPB */ 337 i += 4; /* cPRD, gets filled in below */ 338 339 buf[i++] = 0; /* reserved */ 340 buf[i++] = 0; /* reserved */ 341 buf[i++] = 0; /* reserved */ 342 buf[i++] = 0; /* reserved */ 343 344 /* ATA registers; must be a multiple of 4 */ 345 buf[i++] = qc->tf.device; 346 buf[i++] = ADMA_REGS_DEVICE; 347 if ((qc->tf.flags & ATA_TFLAG_LBA48)) { 348 buf[i++] = qc->tf.hob_nsect; 349 buf[i++] = ADMA_REGS_SECTOR_COUNT; 350 buf[i++] = qc->tf.hob_lbal; 351 buf[i++] = ADMA_REGS_LBA_LOW; 352 buf[i++] = qc->tf.hob_lbam; 353 buf[i++] = ADMA_REGS_LBA_MID; 354 buf[i++] = qc->tf.hob_lbah; 355 buf[i++] = ADMA_REGS_LBA_HIGH; 356 } 357 buf[i++] = qc->tf.nsect; 358 buf[i++] = ADMA_REGS_SECTOR_COUNT; 359 buf[i++] = qc->tf.lbal; 360 buf[i++] = ADMA_REGS_LBA_LOW; 361 buf[i++] = qc->tf.lbam; 362 buf[i++] = ADMA_REGS_LBA_MID; 363 buf[i++] = qc->tf.lbah; 364 buf[i++] = ADMA_REGS_LBA_HIGH; 365 buf[i++] = 0; 366 buf[i++] = ADMA_REGS_CONTROL; 367 buf[i++] = rIGN; 368 buf[i++] = 0; 369 buf[i++] = qc->tf.command; 370 buf[i++] = ADMA_REGS_COMMAND | rEND; 371 372 buf[3] = (i >> 3) - 2; /* cLEN */ 373 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ 374 375 i = adma_fill_sg(qc); 376 wmb(); /* flush PRDs and pkt to memory */ 377 #if 0 378 /* dump out CPB + PRDs for debug */ 379 { 380 int j, len = 0; 381 static char obuf[2048]; 382 for (j = 0; j < i; ++j) { 383 len += sprintf(obuf+len, "%02x ", buf[j]); 384 if ((j & 7) == 7) { 385 printk("%s\n", obuf); 386 len = 0; 387 } 388 } 389 if (len) 390 printk("%s\n", obuf); 391 } 392 #endif 393 } 394 395 static inline void adma_packet_start(struct ata_queued_cmd *qc) 396 { 397 struct ata_port *ap = qc->ap; 398 void __iomem *chan = ADMA_PORT_REGS(ap); 399 400 VPRINTK("ENTER, ap %p\n", ap); 401 402 /* fire up the ADMA engine */ 403 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); 404 } 405 406 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) 407 { 408 struct adma_port_priv *pp = qc->ap->private_data; 409 410 switch (qc->tf.protocol) { 411 case ATA_PROT_DMA: 412 pp->state = adma_state_pkt; 413 adma_packet_start(qc); 414 return 0; 415 416 case ATAPI_PROT_DMA: 417 BUG(); 418 break; 419 420 default: 421 break; 422 } 423 424 pp->state = adma_state_mmio; 425 return ata_sff_qc_issue(qc); 426 } 427 428 static inline unsigned int adma_intr_pkt(struct ata_host *host) 429 { 430 unsigned int handled = 0, port_no; 431 432 for (port_no = 0; port_no < host->n_ports; ++port_no) { 433 struct ata_port *ap = host->ports[port_no]; 434 struct adma_port_priv *pp; 435 struct ata_queued_cmd *qc; 436 void __iomem *chan = ADMA_PORT_REGS(ap); 437 u8 status = readb(chan + ADMA_STATUS); 438 439 if (status == 0) 440 continue; 441 handled = 1; 442 adma_enter_reg_mode(ap); 443 pp = ap->private_data; 444 if (!pp || pp->state != adma_state_pkt) 445 continue; 446 qc = ata_qc_from_tag(ap, ap->link.active_tag); 447 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 448 if (status & aPERR) 449 qc->err_mask |= AC_ERR_HOST_BUS; 450 else if ((status & (aPSD | aUIRQ))) 451 qc->err_mask |= AC_ERR_OTHER; 452 453 if (pp->pkt[0] & cATERR) 454 qc->err_mask |= AC_ERR_DEV; 455 else if (pp->pkt[0] != cDONE) 456 qc->err_mask |= AC_ERR_OTHER; 457 458 if (!qc->err_mask) 459 ata_qc_complete(qc); 460 else { 461 struct ata_eh_info *ehi = &ap->link.eh_info; 462 ata_ehi_clear_desc(ehi); 463 ata_ehi_push_desc(ehi, 464 "ADMA-status 0x%02X", status); 465 ata_ehi_push_desc(ehi, 466 "pkt[0] 0x%02X", pp->pkt[0]); 467 468 if (qc->err_mask == AC_ERR_DEV) 469 ata_port_abort(ap); 470 else 471 ata_port_freeze(ap); 472 } 473 } 474 } 475 return handled; 476 } 477 478 static inline unsigned int adma_intr_mmio(struct ata_host *host) 479 { 480 unsigned int handled = 0, port_no; 481 482 for (port_no = 0; port_no < host->n_ports; ++port_no) { 483 struct ata_port *ap = host->ports[port_no]; 484 struct adma_port_priv *pp = ap->private_data; 485 struct ata_queued_cmd *qc; 486 487 if (!pp || pp->state != adma_state_mmio) 488 continue; 489 qc = ata_qc_from_tag(ap, ap->link.active_tag); 490 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 491 492 /* check main status, clearing INTRQ */ 493 u8 status = ata_sff_check_status(ap); 494 if ((status & ATA_BUSY)) 495 continue; 496 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", 497 ap->print_id, qc->tf.protocol, status); 498 499 /* complete taskfile transaction */ 500 pp->state = adma_state_idle; 501 qc->err_mask |= ac_err_mask(status); 502 if (!qc->err_mask) 503 ata_qc_complete(qc); 504 else { 505 struct ata_eh_info *ehi = &ap->link.eh_info; 506 ata_ehi_clear_desc(ehi); 507 ata_ehi_push_desc(ehi, "status 0x%02X", status); 508 509 if (qc->err_mask == AC_ERR_DEV) 510 ata_port_abort(ap); 511 else 512 ata_port_freeze(ap); 513 } 514 handled = 1; 515 } 516 } 517 return handled; 518 } 519 520 static irqreturn_t adma_intr(int irq, void *dev_instance) 521 { 522 struct ata_host *host = dev_instance; 523 unsigned int handled = 0; 524 525 VPRINTK("ENTER\n"); 526 527 spin_lock(&host->lock); 528 handled = adma_intr_pkt(host) | adma_intr_mmio(host); 529 spin_unlock(&host->lock); 530 531 VPRINTK("EXIT\n"); 532 533 return IRQ_RETVAL(handled); 534 } 535 536 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) 537 { 538 port->cmd_addr = 539 port->data_addr = base + 0x000; 540 port->error_addr = 541 port->feature_addr = base + 0x004; 542 port->nsect_addr = base + 0x008; 543 port->lbal_addr = base + 0x00c; 544 port->lbam_addr = base + 0x010; 545 port->lbah_addr = base + 0x014; 546 port->device_addr = base + 0x018; 547 port->status_addr = 548 port->command_addr = base + 0x01c; 549 port->altstatus_addr = 550 port->ctl_addr = base + 0x038; 551 } 552 553 static int adma_port_start(struct ata_port *ap) 554 { 555 struct device *dev = ap->host->dev; 556 struct adma_port_priv *pp; 557 558 adma_enter_reg_mode(ap); 559 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 560 if (!pp) 561 return -ENOMEM; 562 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, 563 GFP_KERNEL); 564 if (!pp->pkt) 565 return -ENOMEM; 566 /* paranoia? */ 567 if ((pp->pkt_dma & 7) != 0) { 568 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n", 569 (u32)pp->pkt_dma); 570 return -ENOMEM; 571 } 572 memset(pp->pkt, 0, ADMA_PKT_BYTES); 573 ap->private_data = pp; 574 adma_reinit_engine(ap); 575 return 0; 576 } 577 578 static void adma_port_stop(struct ata_port *ap) 579 { 580 adma_reset_engine(ap); 581 } 582 583 static void adma_host_init(struct ata_host *host, unsigned int chip_id) 584 { 585 unsigned int port_no; 586 587 /* enable/lock aGO operation */ 588 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK); 589 590 /* reset the ADMA logic */ 591 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) 592 adma_reset_engine(host->ports[port_no]); 593 } 594 595 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) 596 { 597 int rc; 598 599 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 600 if (rc) { 601 dev_printk(KERN_ERR, &pdev->dev, 602 "32-bit DMA enable failed\n"); 603 return rc; 604 } 605 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 606 if (rc) { 607 dev_printk(KERN_ERR, &pdev->dev, 608 "32-bit consistent DMA enable failed\n"); 609 return rc; 610 } 611 return 0; 612 } 613 614 static int adma_ata_init_one(struct pci_dev *pdev, 615 const struct pci_device_id *ent) 616 { 617 static int printed_version; 618 unsigned int board_idx = (unsigned int) ent->driver_data; 619 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL }; 620 struct ata_host *host; 621 void __iomem *mmio_base; 622 int rc, port_no; 623 624 if (!printed_version++) 625 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 626 627 /* alloc host */ 628 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS); 629 if (!host) 630 return -ENOMEM; 631 632 /* acquire resources and fill host */ 633 rc = pcim_enable_device(pdev); 634 if (rc) 635 return rc; 636 637 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) 638 return -ENODEV; 639 640 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME); 641 if (rc) 642 return rc; 643 host->iomap = pcim_iomap_table(pdev); 644 mmio_base = host->iomap[ADMA_MMIO_BAR]; 645 646 rc = adma_set_dma_masks(pdev, mmio_base); 647 if (rc) 648 return rc; 649 650 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) { 651 struct ata_port *ap = host->ports[port_no]; 652 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no); 653 unsigned int offset = port_base - mmio_base; 654 655 adma_ata_setup_port(&ap->ioaddr, port_base); 656 657 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio"); 658 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port"); 659 } 660 661 /* initialize adapter */ 662 adma_host_init(host, board_idx); 663 664 pci_set_master(pdev); 665 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED, 666 &adma_ata_sht); 667 } 668 669 static int __init adma_ata_init(void) 670 { 671 return pci_register_driver(&adma_ata_pci_driver); 672 } 673 674 static void __exit adma_ata_exit(void) 675 { 676 pci_unregister_driver(&adma_ata_pci_driver); 677 } 678 679 MODULE_AUTHOR("Mark Lord"); 680 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); 681 MODULE_LICENSE("GPL"); 682 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); 683 MODULE_VERSION(DRV_VERSION); 684 685 module_init(adma_ata_init); 686 module_exit(adma_ata_exit); 687