1 /* 2 * pata_via.c - VIA PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * 5 * Documentation 6 * Most chipset documentation available under NDA only 7 * 8 * VIA version guide 9 * VIA VT82C561 - early design, uses ata_generic currently 10 * VIA VT82C576 - MWDMA, 33Mhz 11 * VIA VT82C586 - MWDMA, 33Mhz 12 * VIA VT82C586a - Added UDMA to 33Mhz 13 * VIA VT82C586b - UDMA33 14 * VIA VT82C596a - Nonfunctional UDMA66 15 * VIA VT82C596b - Working UDMA66 16 * VIA VT82C686 - Nonfunctional UDMA66 17 * VIA VT82C686a - Working UDMA66 18 * VIA VT82C686b - Updated to UDMA100 19 * VIA VT8231 - UDMA100 20 * VIA VT8233 - UDMA100 21 * VIA VT8233a - UDMA133 22 * VIA VT8233c - UDMA100 23 * VIA VT8235 - UDMA133 24 * VIA VT8237 - UDMA133 25 * VIA VT8237S - UDMA133 26 * VIA VT8251 - UDMA133 27 * 28 * Most registers remain compatible across chips. Others start reserved 29 * and acquire sensible semantics if set to 1 (eg cable detect). A few 30 * exceptions exist, notably around the FIFO settings. 31 * 32 * One additional quirk of the VIA design is that like ALi they use few 33 * PCI IDs for a lot of chips. 34 * 35 * Based heavily on: 36 * 37 * Version 3.38 38 * 39 * VIA IDE driver for Linux. Supported southbridges: 40 * 41 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, 42 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, 43 * vt8235, vt8237 44 * 45 * Copyright (c) 2000-2002 Vojtech Pavlik 46 * 47 * Based on the work of: 48 * Michel Aubry 49 * Jeff Garzik 50 * Andre Hedrick 51 52 */ 53 54 #include <linux/kernel.h> 55 #include <linux/module.h> 56 #include <linux/pci.h> 57 #include <linux/init.h> 58 #include <linux/blkdev.h> 59 #include <linux/delay.h> 60 #include <scsi/scsi_host.h> 61 #include <linux/libata.h> 62 #include <linux/dmi.h> 63 64 #define DRV_NAME "pata_via" 65 #define DRV_VERSION "0.3.4" 66 67 /* 68 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx 69 * driver. 70 */ 71 72 enum { 73 VIA_UDMA = 0x007, 74 VIA_UDMA_NONE = 0x000, 75 VIA_UDMA_33 = 0x001, 76 VIA_UDMA_66 = 0x002, 77 VIA_UDMA_100 = 0x003, 78 VIA_UDMA_133 = 0x004, 79 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */ 80 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */ 81 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */ 82 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */ 83 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */ 84 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */ 85 VIA_NO_ENABLES = 0x400, /* Has no enablebits */ 86 VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */ 87 }; 88 89 enum { 90 VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */ 91 }; 92 93 /* 94 * VIA SouthBridge chips. 95 */ 96 97 static const struct via_isa_bridge { 98 const char *name; 99 u16 id; 100 u8 rev_min; 101 u8 rev_max; 102 u16 flags; 103 } via_isa_bridges[] = { 104 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, 105 VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 106 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 | 107 VIA_BAD_AST | VIA_SATA_PATA }, 108 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, 109 VIA_UDMA_133 | VIA_BAD_AST }, 110 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 111 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 112 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 113 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES }, 114 { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES }, 115 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 116 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 117 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 118 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 119 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, 120 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, 121 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, 122 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, 123 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, 124 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 125 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, 126 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 127 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, 128 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, 129 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, 130 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, 131 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, 132 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, 133 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 134 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, 135 VIA_UDMA_133 | VIA_BAD_AST }, 136 { NULL } 137 }; 138 139 struct via_port { 140 u8 cached_device; 141 }; 142 143 /* 144 * Cable special cases 145 */ 146 147 static const struct dmi_system_id cable_dmi_table[] = { 148 { 149 .ident = "Acer Ferrari 3400", 150 .matches = { 151 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), 152 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), 153 }, 154 }, 155 { } 156 }; 157 158 static int via_cable_override(struct pci_dev *pdev) 159 { 160 /* Systems by DMI */ 161 if (dmi_check_system(cable_dmi_table)) 162 return 1; 163 /* Arima W730-K8/Targa Visionary 811/... */ 164 if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032) 165 return 1; 166 return 0; 167 } 168 169 170 /** 171 * via_cable_detect - cable detection 172 * @ap: ATA port 173 * 174 * Perform cable detection. Actually for the VIA case the BIOS 175 * already did this for us. We read the values provided by the 176 * BIOS. If you are using an 8235 in a non-PC configuration you 177 * may need to update this code. 178 * 179 * Hotplug also impacts on this. 180 */ 181 182 static int via_cable_detect(struct ata_port *ap) { 183 const struct via_isa_bridge *config = ap->host->private_data; 184 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 185 u32 ata66; 186 187 if (via_cable_override(pdev)) 188 return ATA_CBL_PATA40_SHORT; 189 190 if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0) 191 return ATA_CBL_SATA; 192 193 /* Early chips are 40 wire */ 194 if ((config->flags & VIA_UDMA) < VIA_UDMA_66) 195 return ATA_CBL_PATA40; 196 /* UDMA 66 chips have only drive side logic */ 197 else if ((config->flags & VIA_UDMA) < VIA_UDMA_100) 198 return ATA_CBL_PATA_UNK; 199 /* UDMA 100 or later */ 200 pci_read_config_dword(pdev, 0x50, &ata66); 201 /* Check both the drive cable reporting bits, we might not have 202 two drives */ 203 if (ata66 & (0x10100000 >> (16 * ap->port_no))) 204 return ATA_CBL_PATA80; 205 /* Check with ACPI so we can spot BIOS reported SATA bridges */ 206 if (ata_acpi_init_gtm(ap) && 207 ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap))) 208 return ATA_CBL_PATA80; 209 return ATA_CBL_PATA40; 210 } 211 212 static int via_pre_reset(struct ata_link *link, unsigned long deadline) 213 { 214 struct ata_port *ap = link->ap; 215 const struct via_isa_bridge *config = ap->host->private_data; 216 217 if (!(config->flags & VIA_NO_ENABLES)) { 218 static const struct pci_bits via_enable_bits[] = { 219 { 0x40, 1, 0x02, 0x02 }, 220 { 0x40, 1, 0x01, 0x01 } 221 }; 222 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 223 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) 224 return -ENOENT; 225 } 226 227 return ata_sff_prereset(link, deadline); 228 } 229 230 231 /** 232 * via_do_set_mode - set initial PIO mode data 233 * @ap: ATA interface 234 * @adev: ATA device 235 * @mode: ATA mode being programmed 236 * @tdiv: Clocks per PCI clock 237 * @set_ast: Set to program address setup 238 * @udma_type: UDMA mode/format of registers 239 * 240 * Program the VIA registers for DMA and PIO modes. Uses the ata timing 241 * support in order to compute modes. 242 * 243 * FIXME: Hotplug will require we serialize multiple mode changes 244 * on the two channels. 245 */ 246 247 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type) 248 { 249 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 250 struct ata_device *peer = ata_dev_pair(adev); 251 struct ata_timing t, p; 252 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */ 253 unsigned long T = 1000000000 / via_clock; 254 unsigned long UT = T/tdiv; 255 int ut; 256 int offset = 3 - (2*ap->port_no) - adev->devno; 257 258 /* Calculate the timing values we require */ 259 ata_timing_compute(adev, mode, &t, T, UT); 260 261 /* We share 8bit timing so we must merge the constraints */ 262 if (peer) { 263 if (peer->pio_mode) { 264 ata_timing_compute(peer, peer->pio_mode, &p, T, UT); 265 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); 266 } 267 } 268 269 /* Address setup is programmable but breaks on UDMA133 setups */ 270 if (set_ast) { 271 u8 setup; /* 2 bits per drive */ 272 int shift = 2 * offset; 273 274 pci_read_config_byte(pdev, 0x4C, &setup); 275 setup &= ~(3 << shift); 276 setup |= clamp_val(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */ 277 pci_write_config_byte(pdev, 0x4C, setup); 278 } 279 280 /* Load the PIO mode bits */ 281 pci_write_config_byte(pdev, 0x4F - ap->port_no, 282 ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1)); 283 pci_write_config_byte(pdev, 0x48 + offset, 284 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1)); 285 286 /* Load the UDMA bits according to type */ 287 switch(udma_type) { 288 default: 289 /* BUG() ? */ 290 /* fall through */ 291 case 33: 292 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; 293 break; 294 case 66: 295 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; 296 break; 297 case 100: 298 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 299 break; 300 case 133: 301 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 302 break; 303 } 304 305 /* Set UDMA unless device is not UDMA capable */ 306 if (udma_type) { 307 u8 udma_etc; 308 309 pci_read_config_byte(pdev, 0x50 + offset, &udma_etc); 310 311 /* clear transfer mode bit */ 312 udma_etc &= ~0x20; 313 314 if (t.udma) { 315 /* preserve 80-wire cable detection bit */ 316 udma_etc &= 0x10; 317 udma_etc |= ut; 318 } 319 320 pci_write_config_byte(pdev, 0x50 + offset, udma_etc); 321 } 322 } 323 324 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) 325 { 326 const struct via_isa_bridge *config = ap->host->private_data; 327 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 328 int mode = config->flags & VIA_UDMA; 329 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 330 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 331 332 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]); 333 } 334 335 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) 336 { 337 const struct via_isa_bridge *config = ap->host->private_data; 338 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 339 int mode = config->flags & VIA_UDMA; 340 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 341 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 342 343 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]); 344 } 345 346 /** 347 * via_mode_filter - filter buggy device/mode pairs 348 * @dev: ATA device 349 * @mask: Mode bitmask 350 * 351 * We need to apply some minimal filtering for old controllers and at least 352 * one breed of Transcend SSD. Return the updated mask. 353 */ 354 355 static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask) 356 { 357 struct ata_host *host = dev->link->ap->host; 358 const struct via_isa_bridge *config = host->private_data; 359 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 360 361 if (config->id == PCI_DEVICE_ID_VIA_82C586_0) { 362 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 363 if (strcmp(model_num, "TS64GSSD25-M") == 0) { 364 ata_dev_printk(dev, KERN_WARNING, 365 "disabling UDMA mode due to reported lockups with this device.\n"); 366 mask &= ~ ATA_MASK_UDMA; 367 } 368 } 369 return ata_bmdma_mode_filter(dev, mask); 370 } 371 372 /** 373 * via_tf_load - send taskfile registers to host controller 374 * @ap: Port to which output is sent 375 * @tf: ATA taskfile register set 376 * 377 * Outputs ATA taskfile to standard ATA host controller. 378 * 379 * Note: This is to fix the internal bug of via chipsets, which 380 * will reset the device register after changing the IEN bit on 381 * ctl register 382 */ 383 static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 384 { 385 struct ata_ioports *ioaddr = &ap->ioaddr; 386 struct via_port *vp = ap->private_data; 387 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 388 int newctl = 0; 389 390 if (tf->ctl != ap->last_ctl) { 391 iowrite8(tf->ctl, ioaddr->ctl_addr); 392 ap->last_ctl = tf->ctl; 393 ata_wait_idle(ap); 394 newctl = 1; 395 } 396 397 if (tf->flags & ATA_TFLAG_DEVICE) { 398 iowrite8(tf->device, ioaddr->device_addr); 399 vp->cached_device = tf->device; 400 } else if (newctl) 401 iowrite8(vp->cached_device, ioaddr->device_addr); 402 403 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 404 WARN_ON_ONCE(!ioaddr->ctl_addr); 405 iowrite8(tf->hob_feature, ioaddr->feature_addr); 406 iowrite8(tf->hob_nsect, ioaddr->nsect_addr); 407 iowrite8(tf->hob_lbal, ioaddr->lbal_addr); 408 iowrite8(tf->hob_lbam, ioaddr->lbam_addr); 409 iowrite8(tf->hob_lbah, ioaddr->lbah_addr); 410 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 411 tf->hob_feature, 412 tf->hob_nsect, 413 tf->hob_lbal, 414 tf->hob_lbam, 415 tf->hob_lbah); 416 } 417 418 if (is_addr) { 419 iowrite8(tf->feature, ioaddr->feature_addr); 420 iowrite8(tf->nsect, ioaddr->nsect_addr); 421 iowrite8(tf->lbal, ioaddr->lbal_addr); 422 iowrite8(tf->lbam, ioaddr->lbam_addr); 423 iowrite8(tf->lbah, ioaddr->lbah_addr); 424 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 425 tf->feature, 426 tf->nsect, 427 tf->lbal, 428 tf->lbam, 429 tf->lbah); 430 } 431 432 ata_wait_idle(ap); 433 } 434 435 static int via_port_start(struct ata_port *ap) 436 { 437 struct via_port *vp; 438 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 439 440 int ret = ata_sff_port_start(ap); 441 if (ret < 0) 442 return ret; 443 444 vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL); 445 if (vp == NULL) 446 return -ENOMEM; 447 ap->private_data = vp; 448 return 0; 449 } 450 451 static struct scsi_host_template via_sht = { 452 ATA_BMDMA_SHT(DRV_NAME), 453 }; 454 455 static struct ata_port_operations via_port_ops = { 456 .inherits = &ata_bmdma_port_ops, 457 .cable_detect = via_cable_detect, 458 .set_piomode = via_set_piomode, 459 .set_dmamode = via_set_dmamode, 460 .prereset = via_pre_reset, 461 .sff_tf_load = via_tf_load, 462 .port_start = via_port_start, 463 .mode_filter = via_mode_filter, 464 }; 465 466 static struct ata_port_operations via_port_ops_noirq = { 467 .inherits = &via_port_ops, 468 .sff_data_xfer = ata_sff_data_xfer_noirq, 469 }; 470 471 /** 472 * via_config_fifo - set up the FIFO 473 * @pdev: PCI device 474 * @flags: configuration flags 475 * 476 * Set the FIFO properties for this device if necessary. Used both on 477 * set up and on and the resume path 478 */ 479 480 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) 481 { 482 u8 enable; 483 484 /* 0x40 low bits indicate enabled channels */ 485 pci_read_config_byte(pdev, 0x40 , &enable); 486 enable &= 3; 487 488 if (flags & VIA_SET_FIFO) { 489 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; 490 u8 fifo; 491 492 pci_read_config_byte(pdev, 0x43, &fifo); 493 494 /* Clear PREQ# until DDACK# for errata */ 495 if (flags & VIA_BAD_PREQ) 496 fifo &= 0x7F; 497 else 498 fifo &= 0x9f; 499 /* Turn on FIFO for enabled channels */ 500 fifo |= fifo_setting[enable]; 501 pci_write_config_byte(pdev, 0x43, fifo); 502 } 503 } 504 505 /** 506 * via_init_one - discovery callback 507 * @pdev: PCI device 508 * @id: PCI table info 509 * 510 * A VIA IDE interface has been discovered. Figure out what revision 511 * and perform configuration work before handing it to the ATA layer 512 */ 513 514 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 515 { 516 /* Early VIA without UDMA support */ 517 static const struct ata_port_info via_mwdma_info = { 518 .flags = ATA_FLAG_SLAVE_POSS, 519 .pio_mask = ATA_PIO4, 520 .mwdma_mask = ATA_MWDMA2, 521 .port_ops = &via_port_ops 522 }; 523 /* Ditto with IRQ masking required */ 524 static const struct ata_port_info via_mwdma_info_borked = { 525 .flags = ATA_FLAG_SLAVE_POSS, 526 .pio_mask = ATA_PIO4, 527 .mwdma_mask = ATA_MWDMA2, 528 .port_ops = &via_port_ops_noirq, 529 }; 530 /* VIA UDMA 33 devices (and borked 66) */ 531 static const struct ata_port_info via_udma33_info = { 532 .flags = ATA_FLAG_SLAVE_POSS, 533 .pio_mask = ATA_PIO4, 534 .mwdma_mask = ATA_MWDMA2, 535 .udma_mask = ATA_UDMA2, 536 .port_ops = &via_port_ops 537 }; 538 /* VIA UDMA 66 devices */ 539 static const struct ata_port_info via_udma66_info = { 540 .flags = ATA_FLAG_SLAVE_POSS, 541 .pio_mask = ATA_PIO4, 542 .mwdma_mask = ATA_MWDMA2, 543 .udma_mask = ATA_UDMA4, 544 .port_ops = &via_port_ops 545 }; 546 /* VIA UDMA 100 devices */ 547 static const struct ata_port_info via_udma100_info = { 548 .flags = ATA_FLAG_SLAVE_POSS, 549 .pio_mask = ATA_PIO4, 550 .mwdma_mask = ATA_MWDMA2, 551 .udma_mask = ATA_UDMA5, 552 .port_ops = &via_port_ops 553 }; 554 /* UDMA133 with bad AST (All current 133) */ 555 static const struct ata_port_info via_udma133_info = { 556 .flags = ATA_FLAG_SLAVE_POSS, 557 .pio_mask = ATA_PIO4, 558 .mwdma_mask = ATA_MWDMA2, 559 .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */ 560 .port_ops = &via_port_ops 561 }; 562 const struct ata_port_info *ppi[] = { NULL, NULL }; 563 struct pci_dev *isa; 564 const struct via_isa_bridge *config; 565 static int printed_version; 566 u8 enable; 567 u32 timing; 568 unsigned long flags = id->driver_data; 569 int rc; 570 571 if (!printed_version++) 572 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 573 574 rc = pcim_enable_device(pdev); 575 if (rc) 576 return rc; 577 578 if (flags & VIA_IDFLAG_SINGLE) 579 ppi[1] = &ata_dummy_port_info; 580 581 /* To find out how the IDE will behave and what features we 582 actually have to look at the bridge not the IDE controller */ 583 for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON; 584 config++) 585 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + 586 !!(config->flags & VIA_BAD_ID), 587 config->id, NULL))) { 588 u8 rev = isa->revision; 589 pci_dev_put(isa); 590 591 if (rev >= config->rev_min && rev <= config->rev_max) 592 break; 593 } 594 595 if (!(config->flags & VIA_NO_ENABLES)) { 596 /* 0x40 low bits indicate enabled channels */ 597 pci_read_config_byte(pdev, 0x40 , &enable); 598 enable &= 3; 599 if (enable == 0) 600 return -ENODEV; 601 } 602 603 /* Initialise the FIFO for the enabled channels. */ 604 via_config_fifo(pdev, config->flags); 605 606 /* Clock set up */ 607 switch(config->flags & VIA_UDMA) { 608 case VIA_UDMA_NONE: 609 if (config->flags & VIA_NO_UNMASK) 610 ppi[0] = &via_mwdma_info_borked; 611 else 612 ppi[0] = &via_mwdma_info; 613 break; 614 case VIA_UDMA_33: 615 ppi[0] = &via_udma33_info; 616 break; 617 case VIA_UDMA_66: 618 ppi[0] = &via_udma66_info; 619 /* The 66 MHz devices require we enable the clock */ 620 pci_read_config_dword(pdev, 0x50, &timing); 621 timing |= 0x80008; 622 pci_write_config_dword(pdev, 0x50, timing); 623 break; 624 case VIA_UDMA_100: 625 ppi[0] = &via_udma100_info; 626 break; 627 case VIA_UDMA_133: 628 ppi[0] = &via_udma133_info; 629 break; 630 default: 631 WARN_ON(1); 632 return -ENODEV; 633 } 634 635 if (config->flags & VIA_BAD_CLK66) { 636 /* Disable the 66MHz clock on problem devices */ 637 pci_read_config_dword(pdev, 0x50, &timing); 638 timing &= ~0x80008; 639 pci_write_config_dword(pdev, 0x50, timing); 640 } 641 642 /* We have established the device type, now fire it up */ 643 return ata_pci_sff_init_one(pdev, ppi, &via_sht, (void *)config); 644 } 645 646 #ifdef CONFIG_PM 647 /** 648 * via_reinit_one - reinit after resume 649 * @pdev; PCI device 650 * 651 * Called when the VIA PATA device is resumed. We must then 652 * reconfigure the fifo and other setup we may have altered. In 653 * addition the kernel needs to have the resume methods on PCI 654 * quirk supported. 655 */ 656 657 static int via_reinit_one(struct pci_dev *pdev) 658 { 659 u32 timing; 660 struct ata_host *host = dev_get_drvdata(&pdev->dev); 661 const struct via_isa_bridge *config = host->private_data; 662 int rc; 663 664 rc = ata_pci_device_do_resume(pdev); 665 if (rc) 666 return rc; 667 668 via_config_fifo(pdev, config->flags); 669 670 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) { 671 /* The 66 MHz devices require we enable the clock */ 672 pci_read_config_dword(pdev, 0x50, &timing); 673 timing |= 0x80008; 674 pci_write_config_dword(pdev, 0x50, timing); 675 } 676 if (config->flags & VIA_BAD_CLK66) { 677 /* Disable the 66MHz clock on problem devices */ 678 pci_read_config_dword(pdev, 0x50, &timing); 679 timing &= ~0x80008; 680 pci_write_config_dword(pdev, 0x50, timing); 681 } 682 683 ata_host_resume(host); 684 return 0; 685 } 686 #endif 687 688 static const struct pci_device_id via[] = { 689 { PCI_VDEVICE(VIA, 0x0415), }, 690 { PCI_VDEVICE(VIA, 0x0571), }, 691 { PCI_VDEVICE(VIA, 0x0581), }, 692 { PCI_VDEVICE(VIA, 0x1571), }, 693 { PCI_VDEVICE(VIA, 0x3164), }, 694 { PCI_VDEVICE(VIA, 0x5324), }, 695 { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE }, 696 697 { }, 698 }; 699 700 static struct pci_driver via_pci_driver = { 701 .name = DRV_NAME, 702 .id_table = via, 703 .probe = via_init_one, 704 .remove = ata_pci_remove_one, 705 #ifdef CONFIG_PM 706 .suspend = ata_pci_device_suspend, 707 .resume = via_reinit_one, 708 #endif 709 }; 710 711 static int __init via_init(void) 712 { 713 return pci_register_driver(&via_pci_driver); 714 } 715 716 static void __exit via_exit(void) 717 { 718 pci_unregister_driver(&via_pci_driver); 719 } 720 721 MODULE_AUTHOR("Alan Cox"); 722 MODULE_DESCRIPTION("low-level driver for VIA PATA"); 723 MODULE_LICENSE("GPL"); 724 MODULE_DEVICE_TABLE(pci, via); 725 MODULE_VERSION(DRV_VERSION); 726 727 module_init(via_init); 728 module_exit(via_exit); 729