1 /* 2 * pata_sl82c105.c - SL82C105 PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * 5 * Based in part on linux/drivers/ide/pci/sl82c105.c 6 * SL82C105/Winbond 553 IDE driver 7 * 8 * and in part on the documentation and errata sheet 9 * 10 * 11 * Note: The controller like many controllers has shared timings for 12 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back 13 * in the dma_stop function. Thus we actually don't need a set_dmamode 14 * method as the PIO method is always called and will set the right PIO 15 * timing parameters. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <scsi/scsi_host.h> 25 #include <linux/libata.h> 26 27 #define DRV_NAME "pata_sl82c105" 28 #define DRV_VERSION "0.3.3" 29 30 enum { 31 /* 32 * SL82C105 PCI config register 0x40 bits. 33 */ 34 CTRL_IDE_IRQB = (1 << 30), 35 CTRL_IDE_IRQA = (1 << 28), 36 CTRL_LEGIRQ = (1 << 11), 37 CTRL_P1F16 = (1 << 5), 38 CTRL_P1EN = (1 << 4), 39 CTRL_P0F16 = (1 << 1), 40 CTRL_P0EN = (1 << 0) 41 }; 42 43 /** 44 * sl82c105_pre_reset - probe begin 45 * @link: ATA link 46 * @deadline: deadline jiffies for the operation 47 * 48 * Set up cable type and use generic probe init 49 */ 50 51 static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline) 52 { 53 static const struct pci_bits sl82c105_enable_bits[] = { 54 { 0x40, 1, 0x01, 0x01 }, 55 { 0x40, 1, 0x10, 0x10 } 56 }; 57 struct ata_port *ap = link->ap; 58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 59 60 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) 61 return -ENOENT; 62 return ata_sff_prereset(link, deadline); 63 } 64 65 66 /** 67 * sl82c105_configure_piomode - set chip PIO timing 68 * @ap: ATA interface 69 * @adev: ATA device 70 * @pio: PIO mode 71 * 72 * Called to do the PIO mode setup. Our timing registers are shared 73 * so a configure_dmamode call will undo any work we do here and vice 74 * versa 75 */ 76 77 static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) 78 { 79 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 80 static u16 pio_timing[5] = { 81 0x50D, 0x407, 0x304, 0x242, 0x240 82 }; 83 u16 dummy; 84 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); 85 86 pci_write_config_word(pdev, timing, pio_timing[pio]); 87 /* Can we lose this oddity of the old driver */ 88 pci_read_config_word(pdev, timing, &dummy); 89 } 90 91 /** 92 * sl82c105_set_piomode - set initial PIO mode data 93 * @ap: ATA interface 94 * @adev: ATA device 95 * 96 * Called to do the PIO mode setup. Our timing registers are shared 97 * but we want to set the PIO timing by default. 98 */ 99 100 static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev) 101 { 102 sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 103 } 104 105 /** 106 * sl82c105_configure_dmamode - set DMA mode in chip 107 * @ap: ATA interface 108 * @adev: ATA device 109 * 110 * Load DMA cycle times into the chip ready for a DMA transfer 111 * to occur. 112 */ 113 114 static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev) 115 { 116 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 117 static u16 dma_timing[3] = { 118 0x707, 0x201, 0x200 119 }; 120 u16 dummy; 121 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); 122 int dma = adev->dma_mode - XFER_MW_DMA_0; 123 124 pci_write_config_word(pdev, timing, dma_timing[dma]); 125 /* Can we lose this oddity of the old driver */ 126 pci_read_config_word(pdev, timing, &dummy); 127 } 128 129 /** 130 * sl82c105_reset_engine - Reset the DMA engine 131 * @ap: ATA interface 132 * 133 * The sl82c105 has some serious problems with the DMA engine 134 * when transfers don't run as expected or ATAPI is used. The 135 * recommended fix is to reset the engine each use using a chip 136 * test register. 137 */ 138 139 static void sl82c105_reset_engine(struct ata_port *ap) 140 { 141 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 142 u16 val; 143 144 pci_read_config_word(pdev, 0x7E, &val); 145 pci_write_config_word(pdev, 0x7E, val | 4); 146 pci_write_config_word(pdev, 0x7E, val & ~4); 147 } 148 149 /** 150 * sl82c105_bmdma_start - DMA engine begin 151 * @qc: ATA command 152 * 153 * Reset the DMA engine each use as recommended by the errata 154 * document. 155 * 156 * FIXME: if we switch clock at BMDMA start/end we might get better 157 * PIO performance on DMA capable devices. 158 */ 159 160 static void sl82c105_bmdma_start(struct ata_queued_cmd *qc) 161 { 162 struct ata_port *ap = qc->ap; 163 164 udelay(100); 165 sl82c105_reset_engine(ap); 166 udelay(100); 167 168 /* Set the clocks for DMA */ 169 sl82c105_configure_dmamode(ap, qc->dev); 170 /* Activate DMA */ 171 ata_bmdma_start(qc); 172 } 173 174 /** 175 * sl82c105_bmdma_end - DMA engine stop 176 * @qc: ATA command 177 * 178 * Reset the DMA engine each use as recommended by the errata 179 * document. 180 * 181 * This function is also called to turn off DMA when a timeout occurs 182 * during DMA operation. In both cases we need to reset the engine, 183 * so no actual eng_timeout handler is required. 184 * 185 * We assume bmdma_stop is always called if bmdma_start as called. If 186 * not then we may need to wrap qc_issue. 187 */ 188 189 static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc) 190 { 191 struct ata_port *ap = qc->ap; 192 193 ata_bmdma_stop(qc); 194 sl82c105_reset_engine(ap); 195 udelay(100); 196 197 /* This will redo the initial setup of the DMA device to matching 198 PIO timings */ 199 sl82c105_set_piomode(ap, qc->dev); 200 } 201 202 /** 203 * sl82c105_qc_defer - implement serialization 204 * @qc: command 205 * 206 * We must issue one command per host not per channel because 207 * of the reset bug. 208 * 209 * Q: is the scsi host lock sufficient ? 210 */ 211 212 static int sl82c105_qc_defer(struct ata_queued_cmd *qc) 213 { 214 struct ata_host *host = qc->ap->host; 215 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; 216 int rc; 217 218 /* First apply the usual rules */ 219 rc = ata_std_qc_defer(qc); 220 if (rc != 0) 221 return rc; 222 223 /* Now apply serialization rules. Only allow a command if the 224 other channel state machine is idle */ 225 if (alt && alt->qc_active) 226 return ATA_DEFER_PORT; 227 return 0; 228 } 229 230 static struct scsi_host_template sl82c105_sht = { 231 ATA_BMDMA_SHT(DRV_NAME), 232 }; 233 234 static struct ata_port_operations sl82c105_port_ops = { 235 .inherits = &ata_bmdma_port_ops, 236 .qc_defer = sl82c105_qc_defer, 237 .bmdma_start = sl82c105_bmdma_start, 238 .bmdma_stop = sl82c105_bmdma_stop, 239 .cable_detect = ata_cable_40wire, 240 .set_piomode = sl82c105_set_piomode, 241 .prereset = sl82c105_pre_reset, 242 }; 243 244 /** 245 * sl82c105_bridge_revision - find bridge version 246 * @pdev: PCI device for the ATA function 247 * 248 * Locates the PCI bridge associated with the ATA function and 249 * providing it is a Winbond 553 reports the revision. If it cannot 250 * find a revision or the right device it returns -1 251 */ 252 253 static int sl82c105_bridge_revision(struct pci_dev *pdev) 254 { 255 struct pci_dev *bridge; 256 257 /* 258 * The bridge should be part of the same device, but function 0. 259 */ 260 bridge = pci_get_slot(pdev->bus, 261 PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); 262 if (!bridge) 263 return -1; 264 265 /* 266 * Make sure it is a Winbond 553 and is an ISA bridge. 267 */ 268 if (bridge->vendor != PCI_VENDOR_ID_WINBOND || 269 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || 270 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { 271 pci_dev_put(bridge); 272 return -1; 273 } 274 /* 275 * We need to find function 0's revision, not function 1 276 */ 277 pci_dev_put(bridge); 278 return bridge->revision; 279 } 280 281 282 static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) 283 { 284 static const struct ata_port_info info_dma = { 285 .flags = ATA_FLAG_SLAVE_POSS, 286 .pio_mask = ATA_PIO4, 287 .mwdma_mask = ATA_MWDMA2, 288 .port_ops = &sl82c105_port_ops 289 }; 290 static const struct ata_port_info info_early = { 291 .flags = ATA_FLAG_SLAVE_POSS, 292 .pio_mask = ATA_PIO4, 293 .port_ops = &sl82c105_port_ops 294 }; 295 /* for now use only the first port */ 296 const struct ata_port_info *ppi[] = { &info_early, 297 NULL }; 298 u32 val; 299 int rev; 300 int rc; 301 302 rc = pcim_enable_device(dev); 303 if (rc) 304 return rc; 305 306 rev = sl82c105_bridge_revision(dev); 307 308 if (rev == -1) 309 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n"); 310 else if (rev <= 5) 311 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n"); 312 else 313 ppi[0] = &info_dma; 314 315 pci_read_config_dword(dev, 0x40, &val); 316 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; 317 pci_write_config_dword(dev, 0x40, val); 318 319 return ata_pci_sff_init_one(dev, ppi, &sl82c105_sht, NULL, 0); 320 } 321 322 static const struct pci_device_id sl82c105[] = { 323 { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), }, 324 325 { }, 326 }; 327 328 static struct pci_driver sl82c105_pci_driver = { 329 .name = DRV_NAME, 330 .id_table = sl82c105, 331 .probe = sl82c105_init_one, 332 .remove = ata_pci_remove_one 333 }; 334 335 static int __init sl82c105_init(void) 336 { 337 return pci_register_driver(&sl82c105_pci_driver); 338 } 339 340 static void __exit sl82c105_exit(void) 341 { 342 pci_unregister_driver(&sl82c105_pci_driver); 343 } 344 345 MODULE_AUTHOR("Alan Cox"); 346 MODULE_DESCRIPTION("low-level driver for Sl82c105"); 347 MODULE_LICENSE("GPL"); 348 MODULE_DEVICE_TABLE(pci, sl82c105); 349 MODULE_VERSION(DRV_VERSION); 350 351 module_init(sl82c105_init); 352 module_exit(sl82c105_exit); 353