1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * pata_sl82c105.c - SL82C105 PATA for new ATA layer 4 * (C) 2005 Red Hat Inc 5 * (C) 2011 Bartlomiej Zolnierkiewicz 6 * 7 * Based in part on linux/drivers/ide/pci/sl82c105.c 8 * SL82C105/Winbond 553 IDE driver 9 * 10 * and in part on the documentation and errata sheet 11 * 12 * 13 * Note: The controller like many controllers has shared timings for 14 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back 15 * in the dma_stop function. Thus we actually don't need a set_dmamode 16 * method as the PIO method is always called and will set the right PIO 17 * timing parameters. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <scsi/scsi_host.h> 26 #include <linux/libata.h> 27 28 #define DRV_NAME "pata_sl82c105" 29 #define DRV_VERSION "0.3.3" 30 31 enum { 32 /* 33 * SL82C105 PCI config register 0x40 bits. 34 */ 35 CTRL_IDE_IRQB = (1 << 30), 36 CTRL_IDE_IRQA = (1 << 28), 37 CTRL_LEGIRQ = (1 << 11), 38 CTRL_P1F16 = (1 << 5), 39 CTRL_P1EN = (1 << 4), 40 CTRL_P0F16 = (1 << 1), 41 CTRL_P0EN = (1 << 0) 42 }; 43 44 /** 45 * sl82c105_pre_reset - probe begin 46 * @link: ATA link 47 * @deadline: deadline jiffies for the operation 48 * 49 * Set up cable type and use generic probe init 50 */ 51 52 static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline) 53 { 54 static const struct pci_bits sl82c105_enable_bits[] = { 55 { 0x40, 1, 0x01, 0x01 }, 56 { 0x40, 1, 0x10, 0x10 } 57 }; 58 struct ata_port *ap = link->ap; 59 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 60 61 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) 62 return -ENOENT; 63 return ata_sff_prereset(link, deadline); 64 } 65 66 67 /** 68 * sl82c105_configure_piomode - set chip PIO timing 69 * @ap: ATA interface 70 * @adev: ATA device 71 * @pio: PIO mode 72 * 73 * Called to do the PIO mode setup. Our timing registers are shared 74 * so a configure_dmamode call will undo any work we do here and vice 75 * versa 76 */ 77 78 static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) 79 { 80 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 81 static u16 pio_timing[5] = { 82 0x50D, 0x407, 0x304, 0x242, 0x240 83 }; 84 u16 dummy; 85 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); 86 87 pci_write_config_word(pdev, timing, pio_timing[pio]); 88 /* Can we lose this oddity of the old driver */ 89 pci_read_config_word(pdev, timing, &dummy); 90 } 91 92 /** 93 * sl82c105_set_piomode - set initial PIO mode data 94 * @ap: ATA interface 95 * @adev: ATA device 96 * 97 * Called to do the PIO mode setup. Our timing registers are shared 98 * but we want to set the PIO timing by default. 99 */ 100 101 static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev) 102 { 103 sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 104 } 105 106 /** 107 * sl82c105_configure_dmamode - set DMA mode in chip 108 * @ap: ATA interface 109 * @adev: ATA device 110 * 111 * Load DMA cycle times into the chip ready for a DMA transfer 112 * to occur. 113 */ 114 115 static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev) 116 { 117 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 118 static u16 dma_timing[3] = { 119 0x707, 0x201, 0x200 120 }; 121 u16 dummy; 122 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); 123 int dma = adev->dma_mode - XFER_MW_DMA_0; 124 125 pci_write_config_word(pdev, timing, dma_timing[dma]); 126 /* Can we lose this oddity of the old driver */ 127 pci_read_config_word(pdev, timing, &dummy); 128 } 129 130 /** 131 * sl82c105_reset_engine - Reset the DMA engine 132 * @ap: ATA interface 133 * 134 * The sl82c105 has some serious problems with the DMA engine 135 * when transfers don't run as expected or ATAPI is used. The 136 * recommended fix is to reset the engine each use using a chip 137 * test register. 138 */ 139 140 static void sl82c105_reset_engine(struct ata_port *ap) 141 { 142 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 143 u16 val; 144 145 pci_read_config_word(pdev, 0x7E, &val); 146 pci_write_config_word(pdev, 0x7E, val | 4); 147 pci_write_config_word(pdev, 0x7E, val & ~4); 148 } 149 150 /** 151 * sl82c105_bmdma_start - DMA engine begin 152 * @qc: ATA command 153 * 154 * Reset the DMA engine each use as recommended by the errata 155 * document. 156 * 157 * FIXME: if we switch clock at BMDMA start/end we might get better 158 * PIO performance on DMA capable devices. 159 */ 160 161 static void sl82c105_bmdma_start(struct ata_queued_cmd *qc) 162 { 163 struct ata_port *ap = qc->ap; 164 165 udelay(100); 166 sl82c105_reset_engine(ap); 167 udelay(100); 168 169 /* Set the clocks for DMA */ 170 sl82c105_configure_dmamode(ap, qc->dev); 171 /* Activate DMA */ 172 ata_bmdma_start(qc); 173 } 174 175 /** 176 * sl82c105_bmdma_stop - DMA engine stop 177 * @qc: ATA command 178 * 179 * Reset the DMA engine each use as recommended by the errata 180 * document. 181 * 182 * This function is also called to turn off DMA when a timeout occurs 183 * during DMA operation. In both cases we need to reset the engine. 184 * 185 * We assume bmdma_stop is always called if bmdma_start as called. If 186 * not then we may need to wrap qc_issue. 187 */ 188 189 static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc) 190 { 191 struct ata_port *ap = qc->ap; 192 193 ata_bmdma_stop(qc); 194 sl82c105_reset_engine(ap); 195 udelay(100); 196 197 /* This will redo the initial setup of the DMA device to matching 198 PIO timings */ 199 sl82c105_set_piomode(ap, qc->dev); 200 } 201 202 /** 203 * sl82c105_qc_defer - implement serialization 204 * @qc: command 205 * 206 * We must issue one command per host not per channel because 207 * of the reset bug. 208 * 209 * Q: is the scsi host lock sufficient ? 210 */ 211 212 static int sl82c105_qc_defer(struct ata_queued_cmd *qc) 213 { 214 struct ata_host *host = qc->ap->host; 215 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; 216 int rc; 217 218 /* First apply the usual rules */ 219 rc = ata_std_qc_defer(qc); 220 if (rc != 0) 221 return rc; 222 223 /* Now apply serialization rules. Only allow a command if the 224 other channel state machine is idle */ 225 if (alt && alt->qc_active) 226 return ATA_DEFER_PORT; 227 return 0; 228 } 229 230 static bool sl82c105_sff_irq_check(struct ata_port *ap) 231 { 232 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 233 u32 val, mask = ap->port_no ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; 234 235 pci_read_config_dword(pdev, 0x40, &val); 236 237 return val & mask; 238 } 239 240 static const struct scsi_host_template sl82c105_sht = { 241 ATA_BMDMA_SHT(DRV_NAME), 242 }; 243 244 static struct ata_port_operations sl82c105_port_ops = { 245 .inherits = &ata_bmdma_port_ops, 246 .qc_defer = sl82c105_qc_defer, 247 .bmdma_start = sl82c105_bmdma_start, 248 .bmdma_stop = sl82c105_bmdma_stop, 249 .cable_detect = ata_cable_40wire, 250 .set_piomode = sl82c105_set_piomode, 251 .prereset = sl82c105_pre_reset, 252 .sff_irq_check = sl82c105_sff_irq_check, 253 }; 254 255 /** 256 * sl82c105_bridge_revision - find bridge version 257 * @pdev: PCI device for the ATA function 258 * 259 * Locates the PCI bridge associated with the ATA function and 260 * providing it is a Winbond 553 reports the revision. If it cannot 261 * find a revision or the right device it returns -1 262 */ 263 264 static int sl82c105_bridge_revision(struct pci_dev *pdev) 265 { 266 struct pci_dev *bridge; 267 268 /* 269 * The bridge should be part of the same device, but function 0. 270 */ 271 bridge = pci_get_slot(pdev->bus, 272 PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); 273 if (!bridge) 274 return -1; 275 276 /* 277 * Make sure it is a Winbond 553 and is an ISA bridge. 278 */ 279 if (bridge->vendor != PCI_VENDOR_ID_WINBOND || 280 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || 281 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { 282 pci_dev_put(bridge); 283 return -1; 284 } 285 /* 286 * We need to find function 0's revision, not function 1 287 */ 288 pci_dev_put(bridge); 289 return bridge->revision; 290 } 291 292 static void sl82c105_fixup(struct pci_dev *pdev) 293 { 294 u32 val; 295 296 pci_read_config_dword(pdev, 0x40, &val); 297 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; 298 pci_write_config_dword(pdev, 0x40, val); 299 } 300 301 static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) 302 { 303 static const struct ata_port_info info_dma = { 304 .flags = ATA_FLAG_SLAVE_POSS, 305 .pio_mask = ATA_PIO4, 306 .mwdma_mask = ATA_MWDMA2, 307 .port_ops = &sl82c105_port_ops 308 }; 309 static const struct ata_port_info info_early = { 310 .flags = ATA_FLAG_SLAVE_POSS, 311 .pio_mask = ATA_PIO4, 312 .port_ops = &sl82c105_port_ops 313 }; 314 /* for now use only the first port */ 315 const struct ata_port_info *ppi[] = { &info_early, 316 NULL }; 317 int rev; 318 int rc; 319 320 rc = pcim_enable_device(dev); 321 if (rc) 322 return rc; 323 324 rev = sl82c105_bridge_revision(dev); 325 326 if (rev == -1) 327 dev_warn(&dev->dev, 328 "pata_sl82c105: Unable to find bridge, disabling DMA\n"); 329 else if (rev <= 5) 330 dev_warn(&dev->dev, 331 "pata_sl82c105: Early bridge revision, no DMA available\n"); 332 else 333 ppi[0] = &info_dma; 334 335 sl82c105_fixup(dev); 336 337 return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0); 338 } 339 340 #ifdef CONFIG_PM_SLEEP 341 static int sl82c105_reinit_one(struct pci_dev *pdev) 342 { 343 struct ata_host *host = pci_get_drvdata(pdev); 344 int rc; 345 346 rc = ata_pci_device_do_resume(pdev); 347 if (rc) 348 return rc; 349 350 sl82c105_fixup(pdev); 351 352 ata_host_resume(host); 353 return 0; 354 } 355 #endif 356 357 static const struct pci_device_id sl82c105[] = { 358 { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), }, 359 360 { }, 361 }; 362 363 static struct pci_driver sl82c105_pci_driver = { 364 .name = DRV_NAME, 365 .id_table = sl82c105, 366 .probe = sl82c105_init_one, 367 .remove = ata_pci_remove_one, 368 #ifdef CONFIG_PM_SLEEP 369 .suspend = ata_pci_device_suspend, 370 .resume = sl82c105_reinit_one, 371 #endif 372 }; 373 374 module_pci_driver(sl82c105_pci_driver); 375 376 MODULE_AUTHOR("Alan Cox"); 377 MODULE_DESCRIPTION("low-level driver for Sl82c105"); 378 MODULE_LICENSE("GPL"); 379 MODULE_DEVICE_TABLE(pci, sl82c105); 380 MODULE_VERSION(DRV_VERSION); 381