1 /* 2 * pata_sis.c - SiS ATA driver 3 * 4 * (C) 2005 Red Hat 5 * (C) 2007,2009 Bartlomiej Zolnierkiewicz 6 * 7 * Based upon linux/drivers/ide/pci/sis5513.c 8 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 9 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 10 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 11 * SiS Taiwan : for direct support and hardware. 12 * Daniela Engert : for initial ATA100 advices and numerous others. 13 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 14 * for checking code correctness, providing patches. 15 * Original tests and design on the SiS620 chipset. 16 * ATA100 tests and design on the SiS735 chipset. 17 * ATA16/33 support from specs 18 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 19 * 20 * 21 * TODO 22 * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 23 * More Testing 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/init.h> 30 #include <linux/blkdev.h> 31 #include <linux/delay.h> 32 #include <linux/device.h> 33 #include <scsi/scsi_host.h> 34 #include <linux/libata.h> 35 #include <linux/ata.h> 36 #include "sis.h" 37 38 #define DRV_NAME "pata_sis" 39 #define DRV_VERSION "0.5.2" 40 41 struct sis_chipset { 42 u16 device; /* PCI host ID */ 43 const struct ata_port_info *info; /* Info block */ 44 /* Probably add family, cable detect type etc here to clean 45 up code later */ 46 }; 47 48 struct sis_laptop { 49 u16 device; 50 u16 subvendor; 51 u16 subdevice; 52 }; 53 54 static const struct sis_laptop sis_laptop[] = { 55 /* devid, subvendor, subdev */ 56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ 58 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ 59 /* end marker */ 60 { 0, } 61 }; 62 63 static int sis_short_ata40(struct pci_dev *dev) 64 { 65 const struct sis_laptop *lap = &sis_laptop[0]; 66 67 while (lap->device) { 68 if (lap->device == dev->device && 69 lap->subvendor == dev->subsystem_vendor && 70 lap->subdevice == dev->subsystem_device) 71 return 1; 72 lap++; 73 } 74 75 return 0; 76 } 77 78 /** 79 * sis_old_port_base - return PCI configuration base for dev 80 * @adev: device 81 * 82 * Returns the base of the PCI configuration registers for this port 83 * number. 84 */ 85 86 static int sis_old_port_base(struct ata_device *adev) 87 { 88 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); 89 } 90 91 /** 92 * sis_133_cable_detect - check for 40/80 pin 93 * @ap: Port 94 * @deadline: deadline jiffies for the operation 95 * 96 * Perform cable detection for the later UDMA133 capable 97 * SiS chipset. 98 */ 99 100 static int sis_133_cable_detect(struct ata_port *ap) 101 { 102 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 103 u16 tmp; 104 105 /* The top bit of this register is the cable detect bit */ 106 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 107 if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 108 return ATA_CBL_PATA40; 109 return ATA_CBL_PATA80; 110 } 111 112 /** 113 * sis_66_cable_detect - check for 40/80 pin 114 * @ap: Port 115 * 116 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 117 * SiS IDE controllers. 118 */ 119 120 static int sis_66_cable_detect(struct ata_port *ap) 121 { 122 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 123 u8 tmp; 124 125 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 126 pci_read_config_byte(pdev, 0x48, &tmp); 127 tmp >>= ap->port_no; 128 if ((tmp & 0x10) && !sis_short_ata40(pdev)) 129 return ATA_CBL_PATA40; 130 return ATA_CBL_PATA80; 131 } 132 133 134 /** 135 * sis_pre_reset - probe begin 136 * @link: ATA link 137 * @deadline: deadline jiffies for the operation 138 * 139 * Set up cable type and use generic probe init 140 */ 141 142 static int sis_pre_reset(struct ata_link *link, unsigned long deadline) 143 { 144 static const struct pci_bits sis_enable_bits[] = { 145 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 146 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 147 }; 148 149 struct ata_port *ap = link->ap; 150 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 151 152 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 153 return -ENOENT; 154 155 /* Clear the FIFO settings. We can't enable the FIFO until 156 we know we are poking at a disk */ 157 pci_write_config_byte(pdev, 0x4B, 0); 158 return ata_sff_prereset(link, deadline); 159 } 160 161 162 /** 163 * sis_set_fifo - Set RWP fifo bits for this device 164 * @ap: Port 165 * @adev: Device 166 * 167 * SIS chipsets implement prefetch/postwrite bits for each device 168 * on both channels. This functionality is not ATAPI compatible and 169 * must be configured according to the class of device present 170 */ 171 172 static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 173 { 174 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 175 u8 fifoctrl; 176 u8 mask = 0x11; 177 178 mask <<= (2 * ap->port_no); 179 mask <<= adev->devno; 180 181 /* This holds various bits including the FIFO control */ 182 pci_read_config_byte(pdev, 0x4B, &fifoctrl); 183 fifoctrl &= ~mask; 184 185 /* Enable for ATA (disk) only */ 186 if (adev->class == ATA_DEV_ATA) 187 fifoctrl |= mask; 188 pci_write_config_byte(pdev, 0x4B, fifoctrl); 189 } 190 191 /** 192 * sis_old_set_piomode - Initialize host controller PATA PIO timings 193 * @ap: Port whose timings we are configuring 194 * @adev: Device we are configuring for. 195 * 196 * Set PIO mode for device, in host controller PCI config space. This 197 * function handles PIO set up for all chips that are pre ATA100 and 198 * also early ATA100 devices. 199 * 200 * LOCKING: 201 * None (inherited from caller). 202 */ 203 204 static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 205 { 206 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 207 int port = sis_old_port_base(adev); 208 u8 t1, t2; 209 int speed = adev->pio_mode - XFER_PIO_0; 210 211 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 212 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 213 214 sis_set_fifo(ap, adev); 215 216 pci_read_config_byte(pdev, port, &t1); 217 pci_read_config_byte(pdev, port + 1, &t2); 218 219 t1 &= ~0x0F; /* Clear active/recovery timings */ 220 t2 &= ~0x07; 221 222 t1 |= active[speed]; 223 t2 |= recovery[speed]; 224 225 pci_write_config_byte(pdev, port, t1); 226 pci_write_config_byte(pdev, port + 1, t2); 227 } 228 229 /** 230 * sis_100_set_piomode - Initialize host controller PATA PIO timings 231 * @ap: Port whose timings we are configuring 232 * @adev: Device we are configuring for. 233 * 234 * Set PIO mode for device, in host controller PCI config space. This 235 * function handles PIO set up for ATA100 devices and early ATA133. 236 * 237 * LOCKING: 238 * None (inherited from caller). 239 */ 240 241 static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 242 { 243 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 244 int port = sis_old_port_base(adev); 245 int speed = adev->pio_mode - XFER_PIO_0; 246 247 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 248 249 sis_set_fifo(ap, adev); 250 251 pci_write_config_byte(pdev, port, actrec[speed]); 252 } 253 254 /** 255 * sis_133_set_piomode - Initialize host controller PATA PIO timings 256 * @ap: Port whose timings we are configuring 257 * @adev: Device we are configuring for. 258 * 259 * Set PIO mode for device, in host controller PCI config space. This 260 * function handles PIO set up for the later ATA133 devices. 261 * 262 * LOCKING: 263 * None (inherited from caller). 264 */ 265 266 static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 267 { 268 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 269 int port = 0x40; 270 u32 t1; 271 u32 reg54; 272 int speed = adev->pio_mode - XFER_PIO_0; 273 274 const u32 timing133[] = { 275 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 276 0x0C266000, 277 0x04263000, 278 0x0C0A3000, 279 0x05093000 280 }; 281 const u32 timing100[] = { 282 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 283 0x091C4000, 284 0x031C2000, 285 0x09072000, 286 0x04062000 287 }; 288 289 sis_set_fifo(ap, adev); 290 291 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 292 pci_read_config_dword(pdev, 0x54, ®54); 293 if (reg54 & 0x40000000) 294 port = 0x70; 295 port += 8 * ap->port_no + 4 * adev->devno; 296 297 pci_read_config_dword(pdev, port, &t1); 298 t1 &= 0xC0C00FFF; /* Mask out timing */ 299 300 if (t1 & 0x08) /* 100 or 133 ? */ 301 t1 |= timing133[speed]; 302 else 303 t1 |= timing100[speed]; 304 pci_write_config_byte(pdev, port, t1); 305 } 306 307 /** 308 * sis_old_set_dmamode - Initialize host controller PATA DMA timings 309 * @ap: Port whose timings we are configuring 310 * @adev: Device to program 311 * 312 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 313 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 314 * the old ide/pci driver. 315 * 316 * LOCKING: 317 * None (inherited from caller). 318 */ 319 320 static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 321 { 322 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 323 int speed = adev->dma_mode - XFER_MW_DMA_0; 324 int drive_pci = sis_old_port_base(adev); 325 u16 timing; 326 327 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 328 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 329 330 pci_read_config_word(pdev, drive_pci, &timing); 331 332 if (adev->dma_mode < XFER_UDMA_0) { 333 /* bits 3-0 hold recovery timing bits 8-10 active timing and 334 the higher bits are dependant on the device */ 335 timing &= ~0x870F; 336 timing |= mwdma_bits[speed]; 337 } else { 338 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 339 speed = adev->dma_mode - XFER_UDMA_0; 340 timing &= ~0x6000; 341 timing |= udma_bits[speed]; 342 } 343 pci_write_config_word(pdev, drive_pci, timing); 344 } 345 346 /** 347 * sis_66_set_dmamode - Initialize host controller PATA DMA timings 348 * @ap: Port whose timings we are configuring 349 * @adev: Device to program 350 * 351 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 352 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 353 * the old ide/pci driver. 354 * 355 * LOCKING: 356 * None (inherited from caller). 357 */ 358 359 static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 360 { 361 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 362 int speed = adev->dma_mode - XFER_MW_DMA_0; 363 int drive_pci = sis_old_port_base(adev); 364 u16 timing; 365 366 /* MWDMA 0-2 and UDMA 0-5 */ 367 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 368 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; 369 370 pci_read_config_word(pdev, drive_pci, &timing); 371 372 if (adev->dma_mode < XFER_UDMA_0) { 373 /* bits 3-0 hold recovery timing bits 8-10 active timing and 374 the higher bits are dependant on the device, bit 15 udma */ 375 timing &= ~0x870F; 376 timing |= mwdma_bits[speed]; 377 } else { 378 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 379 speed = adev->dma_mode - XFER_UDMA_0; 380 timing &= ~0xF000; 381 timing |= udma_bits[speed]; 382 } 383 pci_write_config_word(pdev, drive_pci, timing); 384 } 385 386 /** 387 * sis_100_set_dmamode - Initialize host controller PATA DMA timings 388 * @ap: Port whose timings we are configuring 389 * @adev: Device to program 390 * 391 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 392 * Handles UDMA66 and early UDMA100 devices. 393 * 394 * LOCKING: 395 * None (inherited from caller). 396 */ 397 398 static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 399 { 400 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 401 int speed = adev->dma_mode - XFER_MW_DMA_0; 402 int drive_pci = sis_old_port_base(adev); 403 u8 timing; 404 405 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 406 407 pci_read_config_byte(pdev, drive_pci + 1, &timing); 408 409 if (adev->dma_mode < XFER_UDMA_0) { 410 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 411 } else { 412 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 413 speed = adev->dma_mode - XFER_UDMA_0; 414 timing &= ~0x8F; 415 timing |= udma_bits[speed]; 416 } 417 pci_write_config_byte(pdev, drive_pci + 1, timing); 418 } 419 420 /** 421 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 422 * @ap: Port whose timings we are configuring 423 * @adev: Device to program 424 * 425 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 426 * Handles early SiS 961 bridges. 427 * 428 * LOCKING: 429 * None (inherited from caller). 430 */ 431 432 static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 433 { 434 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 435 int speed = adev->dma_mode - XFER_MW_DMA_0; 436 int drive_pci = sis_old_port_base(adev); 437 u8 timing; 438 /* Low 4 bits are timing */ 439 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 440 441 pci_read_config_byte(pdev, drive_pci + 1, &timing); 442 443 if (adev->dma_mode < XFER_UDMA_0) { 444 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 445 } else { 446 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 447 speed = adev->dma_mode - XFER_UDMA_0; 448 timing &= ~0x8F; 449 timing |= udma_bits[speed]; 450 } 451 pci_write_config_byte(pdev, drive_pci + 1, timing); 452 } 453 454 /** 455 * sis_133_set_dmamode - Initialize host controller PATA DMA timings 456 * @ap: Port whose timings we are configuring 457 * @adev: Device to program 458 * 459 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 460 * 461 * LOCKING: 462 * None (inherited from caller). 463 */ 464 465 static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 466 { 467 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 468 int speed = adev->dma_mode - XFER_MW_DMA_0; 469 int port = 0x40; 470 u32 t1; 471 u32 reg54; 472 473 /* bits 4- cycle time 8 - cvs time */ 474 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 475 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 476 477 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 478 pci_read_config_dword(pdev, 0x54, ®54); 479 if (reg54 & 0x40000000) 480 port = 0x70; 481 port += (8 * ap->port_no) + (4 * adev->devno); 482 483 pci_read_config_dword(pdev, port, &t1); 484 485 if (adev->dma_mode < XFER_UDMA_0) { 486 t1 &= ~0x00000004; 487 /* FIXME: need data sheet to add MWDMA here. Also lacking on 488 ide/pci driver */ 489 } else { 490 speed = adev->dma_mode - XFER_UDMA_0; 491 /* if & 8 no UDMA133 - need info for ... */ 492 t1 &= ~0x00000FF0; 493 t1 |= 0x00000004; 494 if (t1 & 0x08) 495 t1 |= timing_u133[speed]; 496 else 497 t1 |= timing_u100[speed]; 498 } 499 pci_write_config_dword(pdev, port, t1); 500 } 501 502 static struct scsi_host_template sis_sht = { 503 ATA_BMDMA_SHT(DRV_NAME), 504 }; 505 506 static struct ata_port_operations sis_133_for_sata_ops = { 507 .inherits = &ata_bmdma_port_ops, 508 .set_piomode = sis_133_set_piomode, 509 .set_dmamode = sis_133_set_dmamode, 510 .cable_detect = sis_133_cable_detect, 511 }; 512 513 static struct ata_port_operations sis_base_ops = { 514 .inherits = &ata_bmdma_port_ops, 515 .prereset = sis_pre_reset, 516 }; 517 518 static struct ata_port_operations sis_133_ops = { 519 .inherits = &sis_base_ops, 520 .set_piomode = sis_133_set_piomode, 521 .set_dmamode = sis_133_set_dmamode, 522 .cable_detect = sis_133_cable_detect, 523 }; 524 525 static struct ata_port_operations sis_133_early_ops = { 526 .inherits = &sis_base_ops, 527 .set_piomode = sis_100_set_piomode, 528 .set_dmamode = sis_133_early_set_dmamode, 529 .cable_detect = sis_66_cable_detect, 530 }; 531 532 static struct ata_port_operations sis_100_ops = { 533 .inherits = &sis_base_ops, 534 .set_piomode = sis_100_set_piomode, 535 .set_dmamode = sis_100_set_dmamode, 536 .cable_detect = sis_66_cable_detect, 537 }; 538 539 static struct ata_port_operations sis_66_ops = { 540 .inherits = &sis_base_ops, 541 .set_piomode = sis_old_set_piomode, 542 .set_dmamode = sis_66_set_dmamode, 543 .cable_detect = sis_66_cable_detect, 544 }; 545 546 static struct ata_port_operations sis_old_ops = { 547 .inherits = &sis_base_ops, 548 .set_piomode = sis_old_set_piomode, 549 .set_dmamode = sis_old_set_dmamode, 550 .cable_detect = ata_cable_40wire, 551 }; 552 553 static const struct ata_port_info sis_info = { 554 .flags = ATA_FLAG_SLAVE_POSS, 555 .pio_mask = ATA_PIO4, 556 .mwdma_mask = ATA_MWDMA2, 557 /* No UDMA */ 558 .port_ops = &sis_old_ops, 559 }; 560 static const struct ata_port_info sis_info33 = { 561 .flags = ATA_FLAG_SLAVE_POSS, 562 .pio_mask = ATA_PIO4, 563 .mwdma_mask = ATA_MWDMA2, 564 .udma_mask = ATA_UDMA2, 565 .port_ops = &sis_old_ops, 566 }; 567 static const struct ata_port_info sis_info66 = { 568 .flags = ATA_FLAG_SLAVE_POSS, 569 .pio_mask = ATA_PIO4, 570 /* No MWDMA */ 571 .udma_mask = ATA_UDMA4, 572 .port_ops = &sis_66_ops, 573 }; 574 static const struct ata_port_info sis_info100 = { 575 .flags = ATA_FLAG_SLAVE_POSS, 576 .pio_mask = ATA_PIO4, 577 /* No MWDMA */ 578 .udma_mask = ATA_UDMA5, 579 .port_ops = &sis_100_ops, 580 }; 581 static const struct ata_port_info sis_info100_early = { 582 .flags = ATA_FLAG_SLAVE_POSS, 583 .pio_mask = ATA_PIO4, 584 /* No MWDMA */ 585 .udma_mask = ATA_UDMA5, 586 .port_ops = &sis_66_ops, 587 }; 588 static const struct ata_port_info sis_info133 = { 589 .flags = ATA_FLAG_SLAVE_POSS, 590 .pio_mask = ATA_PIO4, 591 /* No MWDMA */ 592 .udma_mask = ATA_UDMA6, 593 .port_ops = &sis_133_ops, 594 }; 595 const struct ata_port_info sis_info133_for_sata = { 596 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 597 .pio_mask = ATA_PIO4, 598 /* No MWDMA */ 599 .udma_mask = ATA_UDMA6, 600 .port_ops = &sis_133_for_sata_ops, 601 }; 602 static const struct ata_port_info sis_info133_early = { 603 .flags = ATA_FLAG_SLAVE_POSS, 604 .pio_mask = ATA_PIO4, 605 /* No MWDMA */ 606 .udma_mask = ATA_UDMA6, 607 .port_ops = &sis_133_early_ops, 608 }; 609 610 /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 611 EXPORT_SYMBOL_GPL(sis_info133_for_sata); 612 613 static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 614 { 615 u16 regw; 616 u8 reg; 617 618 if (sis->info == &sis_info133) { 619 pci_read_config_word(pdev, 0x50, ®w); 620 if (regw & 0x08) 621 pci_write_config_word(pdev, 0x50, regw & ~0x08); 622 pci_read_config_word(pdev, 0x52, ®w); 623 if (regw & 0x08) 624 pci_write_config_word(pdev, 0x52, regw & ~0x08); 625 return; 626 } 627 628 if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 629 /* Fix up latency */ 630 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 631 /* Set compatibility bit */ 632 pci_read_config_byte(pdev, 0x49, ®); 633 if (!(reg & 0x01)) 634 pci_write_config_byte(pdev, 0x49, reg | 0x01); 635 return; 636 } 637 638 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 639 /* Fix up latency */ 640 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 641 /* Set compatibility bit */ 642 pci_read_config_byte(pdev, 0x52, ®); 643 if (!(reg & 0x04)) 644 pci_write_config_byte(pdev, 0x52, reg | 0x04); 645 return; 646 } 647 648 if (sis->info == &sis_info33) { 649 pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 650 if (( reg & 0x0F ) != 0x00) 651 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 652 /* Fall through to ATA16 fixup below */ 653 } 654 655 if (sis->info == &sis_info || sis->info == &sis_info33) { 656 /* force per drive recovery and active timings 657 needed on ATA_33 and below chips */ 658 pci_read_config_byte(pdev, 0x52, ®); 659 if (!(reg & 0x08)) 660 pci_write_config_byte(pdev, 0x52, reg|0x08); 661 return; 662 } 663 664 BUG(); 665 } 666 667 /** 668 * sis_init_one - Register SiS ATA PCI device with kernel services 669 * @pdev: PCI device to register 670 * @ent: Entry in sis_pci_tbl matching with @pdev 671 * 672 * Called from kernel PCI layer. We probe for combined mode (sigh), 673 * and then hand over control to libata, for it to do the rest. 674 * 675 * LOCKING: 676 * Inherited from PCI layer (may sleep). 677 * 678 * RETURNS: 679 * Zero on success, or -ERRNO value. 680 */ 681 682 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 683 { 684 static int printed_version; 685 const struct ata_port_info *ppi[] = { NULL, NULL }; 686 struct pci_dev *host = NULL; 687 struct sis_chipset *chipset = NULL; 688 struct sis_chipset *sets; 689 int rc; 690 691 static struct sis_chipset sis_chipsets[] = { 692 693 { 0x0968, &sis_info133 }, 694 { 0x0966, &sis_info133 }, 695 { 0x0965, &sis_info133 }, 696 { 0x0745, &sis_info100 }, 697 { 0x0735, &sis_info100 }, 698 { 0x0733, &sis_info100 }, 699 { 0x0635, &sis_info100 }, 700 { 0x0633, &sis_info100 }, 701 702 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 703 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 704 705 { 0x0640, &sis_info66 }, 706 { 0x0630, &sis_info66 }, 707 { 0x0620, &sis_info66 }, 708 { 0x0540, &sis_info66 }, 709 { 0x0530, &sis_info66 }, 710 711 { 0x5600, &sis_info33 }, 712 { 0x5598, &sis_info33 }, 713 { 0x5597, &sis_info33 }, 714 { 0x5591, &sis_info33 }, 715 { 0x5582, &sis_info33 }, 716 { 0x5581, &sis_info33 }, 717 718 { 0x5596, &sis_info }, 719 { 0x5571, &sis_info }, 720 { 0x5517, &sis_info }, 721 { 0x5511, &sis_info }, 722 723 {0} 724 }; 725 static struct sis_chipset sis133_early = { 726 0x0, &sis_info133_early 727 }; 728 static struct sis_chipset sis133 = { 729 0x0, &sis_info133 730 }; 731 static struct sis_chipset sis100_early = { 732 0x0, &sis_info100_early 733 }; 734 static struct sis_chipset sis100 = { 735 0x0, &sis_info100 736 }; 737 738 if (!printed_version++) 739 dev_printk(KERN_DEBUG, &pdev->dev, 740 "version " DRV_VERSION "\n"); 741 742 rc = pcim_enable_device(pdev); 743 if (rc) 744 return rc; 745 746 /* We have to find the bridge first */ 747 for (sets = &sis_chipsets[0]; sets->device; sets++) { 748 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 749 if (host != NULL) { 750 chipset = sets; /* Match found */ 751 if (sets->device == 0x630) { /* SIS630 */ 752 if (host->revision >= 0x30) /* 630 ET */ 753 chipset = &sis100_early; 754 } 755 break; 756 } 757 } 758 759 /* Look for concealed bridges */ 760 if (chipset == NULL) { 761 /* Second check */ 762 u32 idemisc; 763 u16 trueid; 764 765 /* Disable ID masking and register remapping then 766 see what the real ID is */ 767 768 pci_read_config_dword(pdev, 0x54, &idemisc); 769 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 770 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 771 pci_write_config_dword(pdev, 0x54, idemisc); 772 773 switch(trueid) { 774 case 0x5518: /* SIS 962/963 */ 775 chipset = &sis133; 776 if ((idemisc & 0x40000000) == 0) { 777 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 778 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); 779 } 780 break; 781 case 0x0180: /* SIS 965/965L */ 782 chipset = &sis133; 783 break; 784 case 0x1180: /* SIS 966/966L */ 785 chipset = &sis133; 786 break; 787 } 788 } 789 790 /* Further check */ 791 if (chipset == NULL) { 792 struct pci_dev *lpc_bridge; 793 u16 trueid; 794 u8 prefctl; 795 u8 idecfg; 796 797 /* Try the second unmasking technique */ 798 pci_read_config_byte(pdev, 0x4a, &idecfg); 799 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 800 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 801 pci_write_config_byte(pdev, 0x4a, idecfg); 802 803 switch(trueid) { 804 case 0x5517: 805 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 806 if (lpc_bridge == NULL) 807 break; 808 pci_read_config_byte(pdev, 0x49, &prefctl); 809 pci_dev_put(lpc_bridge); 810 811 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { 812 chipset = &sis133_early; 813 break; 814 } 815 chipset = &sis100; 816 break; 817 } 818 } 819 pci_dev_put(host); 820 821 /* No chipset info, no support */ 822 if (chipset == NULL) 823 return -ENODEV; 824 825 ppi[0] = chipset->info; 826 827 sis_fixup(pdev, chipset); 828 829 return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0); 830 } 831 832 #ifdef CONFIG_PM 833 static int sis_reinit_one(struct pci_dev *pdev) 834 { 835 struct ata_host *host = dev_get_drvdata(&pdev->dev); 836 int rc; 837 838 rc = ata_pci_device_do_resume(pdev); 839 if (rc) 840 return rc; 841 842 sis_fixup(pdev, host->private_data); 843 844 ata_host_resume(host); 845 return 0; 846 } 847 #endif 848 849 static const struct pci_device_id sis_pci_tbl[] = { 850 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 851 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 852 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 853 854 { } 855 }; 856 857 static struct pci_driver sis_pci_driver = { 858 .name = DRV_NAME, 859 .id_table = sis_pci_tbl, 860 .probe = sis_init_one, 861 .remove = ata_pci_remove_one, 862 #ifdef CONFIG_PM 863 .suspend = ata_pci_device_suspend, 864 .resume = sis_reinit_one, 865 #endif 866 }; 867 868 static int __init sis_init(void) 869 { 870 return pci_register_driver(&sis_pci_driver); 871 } 872 873 static void __exit sis_exit(void) 874 { 875 pci_unregister_driver(&sis_pci_driver); 876 } 877 878 module_init(sis_init); 879 module_exit(sis_exit); 880 881 MODULE_AUTHOR("Alan Cox"); 882 MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 883 MODULE_LICENSE("GPL"); 884 MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 885 MODULE_VERSION(DRV_VERSION); 886 887