1 /* 2 * pata_sis.c - SiS ATA driver 3 * 4 * (C) 2005 Red Hat <alan@redhat.com> 5 * 6 * Based upon linux/drivers/ide/pci/sis5513.c 7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 10 * SiS Taiwan : for direct support and hardware. 11 * Daniela Engert : for initial ATA100 advices and numerous others. 12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 13 * for checking code correctness, providing patches. 14 * Original tests and design on the SiS620 chipset. 15 * ATA100 tests and design on the SiS735 chipset. 16 * ATA16/33 support from specs 17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 18 * 19 * 20 * TODO 21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 22 * More Testing 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include <linux/init.h> 29 #include <linux/blkdev.h> 30 #include <linux/delay.h> 31 #include <linux/device.h> 32 #include <scsi/scsi_host.h> 33 #include <linux/libata.h> 34 #include <linux/ata.h> 35 #include "sis.h" 36 37 #define DRV_NAME "pata_sis" 38 #define DRV_VERSION "0.5.1" 39 40 struct sis_chipset { 41 u16 device; /* PCI host ID */ 42 const struct ata_port_info *info; /* Info block */ 43 /* Probably add family, cable detect type etc here to clean 44 up code later */ 45 }; 46 47 struct sis_laptop { 48 u16 device; 49 u16 subvendor; 50 u16 subdevice; 51 }; 52 53 static const struct sis_laptop sis_laptop[] = { 54 /* devid, subvendor, subdev */ 55 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 56 /* end marker */ 57 { 0, } 58 }; 59 60 static int sis_short_ata40(struct pci_dev *dev) 61 { 62 const struct sis_laptop *lap = &sis_laptop[0]; 63 64 while (lap->device) { 65 if (lap->device == dev->device && 66 lap->subvendor == dev->subsystem_vendor && 67 lap->subdevice == dev->subsystem_device) 68 return 1; 69 lap++; 70 } 71 72 return 0; 73 } 74 75 /** 76 * sis_old_port_base - return PCI configuration base for dev 77 * @adev: device 78 * 79 * Returns the base of the PCI configuration registers for this port 80 * number. 81 */ 82 83 static int sis_old_port_base(struct ata_device *adev) 84 { 85 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno); 86 } 87 88 /** 89 * sis_133_cable_detect - check for 40/80 pin 90 * @ap: Port 91 * @deadline: deadline jiffies for the operation 92 * 93 * Perform cable detection for the later UDMA133 capable 94 * SiS chipset. 95 */ 96 97 static int sis_133_cable_detect(struct ata_port *ap) 98 { 99 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 100 u16 tmp; 101 102 /* The top bit of this register is the cable detect bit */ 103 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 104 if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 105 return ATA_CBL_PATA40; 106 return ATA_CBL_PATA80; 107 } 108 109 /** 110 * sis_66_cable_detect - check for 40/80 pin 111 * @ap: Port 112 * @deadline: deadline jiffies for the operation 113 * 114 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 115 * SiS IDE controllers. 116 */ 117 118 static int sis_66_cable_detect(struct ata_port *ap) 119 { 120 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 121 u8 tmp; 122 123 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 124 pci_read_config_byte(pdev, 0x48, &tmp); 125 tmp >>= ap->port_no; 126 if ((tmp & 0x10) && !sis_short_ata40(pdev)) 127 return ATA_CBL_PATA40; 128 return ATA_CBL_PATA80; 129 } 130 131 132 /** 133 * sis_pre_reset - probe begin 134 * @ap: ATA port 135 * @deadline: deadline jiffies for the operation 136 * 137 * Set up cable type and use generic probe init 138 */ 139 140 static int sis_pre_reset(struct ata_port *ap, unsigned long deadline) 141 { 142 static const struct pci_bits sis_enable_bits[] = { 143 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 144 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 145 }; 146 147 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 148 149 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 150 return -ENOENT; 151 152 return ata_std_prereset(ap, deadline); 153 } 154 155 156 /** 157 * sis_error_handler - Probe specified port on PATA host controller 158 * @ap: Port to probe 159 * 160 * LOCKING: 161 * None (inherited from caller). 162 */ 163 164 static void sis_error_handler(struct ata_port *ap) 165 { 166 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 167 } 168 169 /** 170 * sis_set_fifo - Set RWP fifo bits for this device 171 * @ap: Port 172 * @adev: Device 173 * 174 * SIS chipsets implement prefetch/postwrite bits for each device 175 * on both channels. This functionality is not ATAPI compatible and 176 * must be configured according to the class of device present 177 */ 178 179 static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 180 { 181 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 182 u8 fifoctrl; 183 u8 mask = 0x11; 184 185 mask <<= (2 * ap->port_no); 186 mask <<= adev->devno; 187 188 /* This holds various bits including the FIFO control */ 189 pci_read_config_byte(pdev, 0x4B, &fifoctrl); 190 fifoctrl &= ~mask; 191 192 /* Enable for ATA (disk) only */ 193 if (adev->class == ATA_DEV_ATA) 194 fifoctrl |= mask; 195 pci_write_config_byte(pdev, 0x4B, fifoctrl); 196 } 197 198 /** 199 * sis_old_set_piomode - Initialize host controller PATA PIO timings 200 * @ap: Port whose timings we are configuring 201 * @adev: Device we are configuring for. 202 * 203 * Set PIO mode for device, in host controller PCI config space. This 204 * function handles PIO set up for all chips that are pre ATA100 and 205 * also early ATA100 devices. 206 * 207 * LOCKING: 208 * None (inherited from caller). 209 */ 210 211 static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 212 { 213 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 214 int port = sis_old_port_base(adev); 215 u8 t1, t2; 216 int speed = adev->pio_mode - XFER_PIO_0; 217 218 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 219 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 220 221 sis_set_fifo(ap, adev); 222 223 pci_read_config_byte(pdev, port, &t1); 224 pci_read_config_byte(pdev, port + 1, &t2); 225 226 t1 &= ~0x0F; /* Clear active/recovery timings */ 227 t2 &= ~0x07; 228 229 t1 |= active[speed]; 230 t2 |= recovery[speed]; 231 232 pci_write_config_byte(pdev, port, t1); 233 pci_write_config_byte(pdev, port + 1, t2); 234 } 235 236 /** 237 * sis_100_set_pioode - Initialize host controller PATA PIO timings 238 * @ap: Port whose timings we are configuring 239 * @adev: Device we are configuring for. 240 * 241 * Set PIO mode for device, in host controller PCI config space. This 242 * function handles PIO set up for ATA100 devices and early ATA133. 243 * 244 * LOCKING: 245 * None (inherited from caller). 246 */ 247 248 static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 249 { 250 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 251 int port = sis_old_port_base(adev); 252 int speed = adev->pio_mode - XFER_PIO_0; 253 254 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 255 256 sis_set_fifo(ap, adev); 257 258 pci_write_config_byte(pdev, port, actrec[speed]); 259 } 260 261 /** 262 * sis_133_set_pioode - Initialize host controller PATA PIO timings 263 * @ap: Port whose timings we are configuring 264 * @adev: Device we are configuring for. 265 * 266 * Set PIO mode for device, in host controller PCI config space. This 267 * function handles PIO set up for the later ATA133 devices. 268 * 269 * LOCKING: 270 * None (inherited from caller). 271 */ 272 273 static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 274 { 275 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 276 int port = 0x40; 277 u32 t1; 278 u32 reg54; 279 int speed = adev->pio_mode - XFER_PIO_0; 280 281 const u32 timing133[] = { 282 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 283 0x0C266000, 284 0x04263000, 285 0x0C0A3000, 286 0x05093000 287 }; 288 const u32 timing100[] = { 289 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 290 0x091C4000, 291 0x031C2000, 292 0x09072000, 293 0x04062000 294 }; 295 296 sis_set_fifo(ap, adev); 297 298 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 299 pci_read_config_dword(pdev, 0x54, ®54); 300 if (reg54 & 0x40000000) 301 port = 0x70; 302 port += 8 * ap->port_no + 4 * adev->devno; 303 304 pci_read_config_dword(pdev, port, &t1); 305 t1 &= 0xC0C00FFF; /* Mask out timing */ 306 307 if (t1 & 0x08) /* 100 or 133 ? */ 308 t1 |= timing133[speed]; 309 else 310 t1 |= timing100[speed]; 311 pci_write_config_byte(pdev, port, t1); 312 } 313 314 /** 315 * sis_old_set_dmamode - Initialize host controller PATA DMA timings 316 * @ap: Port whose timings we are configuring 317 * @adev: Device to program 318 * 319 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 320 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 321 * the old ide/pci driver. 322 * 323 * LOCKING: 324 * None (inherited from caller). 325 */ 326 327 static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 328 { 329 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 330 int speed = adev->dma_mode - XFER_MW_DMA_0; 331 int drive_pci = sis_old_port_base(adev); 332 u16 timing; 333 334 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 }; 335 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 336 337 pci_read_config_word(pdev, drive_pci, &timing); 338 339 if (adev->dma_mode < XFER_UDMA_0) { 340 /* bits 3-0 hold recovery timing bits 8-10 active timing and 341 the higer bits are dependant on the device */ 342 timing &= ~ 0x870F; 343 timing |= mwdma_bits[speed]; 344 pci_write_config_word(pdev, drive_pci, timing); 345 } else { 346 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 347 speed = adev->dma_mode - XFER_UDMA_0; 348 timing &= ~0x6000; 349 timing |= udma_bits[speed]; 350 } 351 } 352 353 /** 354 * sis_66_set_dmamode - Initialize host controller PATA DMA timings 355 * @ap: Port whose timings we are configuring 356 * @adev: Device to program 357 * 358 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 359 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 360 * the old ide/pci driver. 361 * 362 * LOCKING: 363 * None (inherited from caller). 364 */ 365 366 static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 367 { 368 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 369 int speed = adev->dma_mode - XFER_MW_DMA_0; 370 int drive_pci = sis_old_port_base(adev); 371 u16 timing; 372 373 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 }; 374 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000}; 375 376 pci_read_config_word(pdev, drive_pci, &timing); 377 378 if (adev->dma_mode < XFER_UDMA_0) { 379 /* bits 3-0 hold recovery timing bits 8-10 active timing and 380 the higer bits are dependant on the device, bit 15 udma */ 381 timing &= ~0x870F; 382 timing |= mwdma_bits[speed]; 383 } else { 384 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 385 speed = adev->dma_mode - XFER_UDMA_0; 386 timing &= ~0xF000; 387 timing |= udma_bits[speed]; 388 } 389 pci_write_config_word(pdev, drive_pci, timing); 390 } 391 392 /** 393 * sis_100_set_dmamode - Initialize host controller PATA DMA timings 394 * @ap: Port whose timings we are configuring 395 * @adev: Device to program 396 * 397 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 398 * Handles UDMA66 and early UDMA100 devices. 399 * 400 * LOCKING: 401 * None (inherited from caller). 402 */ 403 404 static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 405 { 406 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 407 int speed = adev->dma_mode - XFER_MW_DMA_0; 408 int drive_pci = sis_old_port_base(adev); 409 u8 timing; 410 411 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 412 413 pci_read_config_byte(pdev, drive_pci + 1, &timing); 414 415 if (adev->dma_mode < XFER_UDMA_0) { 416 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 417 } else { 418 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 419 speed = adev->dma_mode - XFER_UDMA_0; 420 timing &= ~0x8F; 421 timing |= udma_bits[speed]; 422 } 423 pci_write_config_byte(pdev, drive_pci + 1, timing); 424 } 425 426 /** 427 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 428 * @ap: Port whose timings we are configuring 429 * @adev: Device to program 430 * 431 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 432 * Handles early SiS 961 bridges. Supports MWDMA as well unlike 433 * the old ide/pci driver. 434 * 435 * LOCKING: 436 * None (inherited from caller). 437 */ 438 439 static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 440 { 441 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 442 int speed = adev->dma_mode - XFER_MW_DMA_0; 443 int drive_pci = sis_old_port_base(adev); 444 u8 timing; 445 /* Low 4 bits are timing */ 446 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 447 448 pci_read_config_byte(pdev, drive_pci + 1, &timing); 449 450 if (adev->dma_mode < XFER_UDMA_0) { 451 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 452 } else { 453 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 454 speed = adev->dma_mode - XFER_UDMA_0; 455 timing &= ~0x8F; 456 timing |= udma_bits[speed]; 457 } 458 pci_write_config_byte(pdev, drive_pci + 1, timing); 459 } 460 461 /** 462 * sis_133_set_dmamode - Initialize host controller PATA DMA timings 463 * @ap: Port whose timings we are configuring 464 * @adev: Device to program 465 * 466 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 467 * Handles early SiS 961 bridges. Supports MWDMA as well unlike 468 * the old ide/pci driver. 469 * 470 * LOCKING: 471 * None (inherited from caller). 472 */ 473 474 static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 475 { 476 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 477 int speed = adev->dma_mode - XFER_MW_DMA_0; 478 int port = 0x40; 479 u32 t1; 480 u32 reg54; 481 482 /* bits 4- cycle time 8 - cvs time */ 483 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 484 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 485 486 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 487 pci_read_config_dword(pdev, 0x54, ®54); 488 if (reg54 & 0x40000000) 489 port = 0x70; 490 port += (8 * ap->port_no) + (4 * adev->devno); 491 492 pci_read_config_dword(pdev, port, &t1); 493 494 if (adev->dma_mode < XFER_UDMA_0) { 495 t1 &= ~0x00000004; 496 /* FIXME: need data sheet to add MWDMA here. Also lacking on 497 ide/pci driver */ 498 } else { 499 speed = adev->dma_mode - XFER_UDMA_0; 500 /* if & 8 no UDMA133 - need info for ... */ 501 t1 &= ~0x00000FF0; 502 t1 |= 0x00000004; 503 if (t1 & 0x08) 504 t1 |= timing_u133[speed]; 505 else 506 t1 |= timing_u100[speed]; 507 } 508 pci_write_config_dword(pdev, port, t1); 509 } 510 511 static struct scsi_host_template sis_sht = { 512 .module = THIS_MODULE, 513 .name = DRV_NAME, 514 .ioctl = ata_scsi_ioctl, 515 .queuecommand = ata_scsi_queuecmd, 516 .can_queue = ATA_DEF_QUEUE, 517 .this_id = ATA_SHT_THIS_ID, 518 .sg_tablesize = LIBATA_MAX_PRD, 519 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 520 .emulated = ATA_SHT_EMULATED, 521 .use_clustering = ATA_SHT_USE_CLUSTERING, 522 .proc_name = DRV_NAME, 523 .dma_boundary = ATA_DMA_BOUNDARY, 524 .slave_configure = ata_scsi_slave_config, 525 .slave_destroy = ata_scsi_slave_destroy, 526 .bios_param = ata_std_bios_param, 527 }; 528 529 static const struct ata_port_operations sis_133_ops = { 530 .port_disable = ata_port_disable, 531 .set_piomode = sis_133_set_piomode, 532 .set_dmamode = sis_133_set_dmamode, 533 .mode_filter = ata_pci_default_filter, 534 535 .tf_load = ata_tf_load, 536 .tf_read = ata_tf_read, 537 .check_status = ata_check_status, 538 .exec_command = ata_exec_command, 539 .dev_select = ata_std_dev_select, 540 541 .freeze = ata_bmdma_freeze, 542 .thaw = ata_bmdma_thaw, 543 .error_handler = sis_error_handler, 544 .post_internal_cmd = ata_bmdma_post_internal_cmd, 545 .cable_detect = sis_133_cable_detect, 546 547 .bmdma_setup = ata_bmdma_setup, 548 .bmdma_start = ata_bmdma_start, 549 .bmdma_stop = ata_bmdma_stop, 550 .bmdma_status = ata_bmdma_status, 551 .qc_prep = ata_qc_prep, 552 .qc_issue = ata_qc_issue_prot, 553 .data_xfer = ata_data_xfer, 554 555 .irq_handler = ata_interrupt, 556 .irq_clear = ata_bmdma_irq_clear, 557 .irq_on = ata_irq_on, 558 .irq_ack = ata_irq_ack, 559 560 .port_start = ata_port_start, 561 }; 562 563 static const struct ata_port_operations sis_133_for_sata_ops = { 564 .port_disable = ata_port_disable, 565 .set_piomode = sis_133_set_piomode, 566 .set_dmamode = sis_133_set_dmamode, 567 .mode_filter = ata_pci_default_filter, 568 569 .tf_load = ata_tf_load, 570 .tf_read = ata_tf_read, 571 .check_status = ata_check_status, 572 .exec_command = ata_exec_command, 573 .dev_select = ata_std_dev_select, 574 575 .freeze = ata_bmdma_freeze, 576 .thaw = ata_bmdma_thaw, 577 .error_handler = ata_bmdma_error_handler, 578 .post_internal_cmd = ata_bmdma_post_internal_cmd, 579 .cable_detect = sis_133_cable_detect, 580 581 .bmdma_setup = ata_bmdma_setup, 582 .bmdma_start = ata_bmdma_start, 583 .bmdma_stop = ata_bmdma_stop, 584 .bmdma_status = ata_bmdma_status, 585 .qc_prep = ata_qc_prep, 586 .qc_issue = ata_qc_issue_prot, 587 .data_xfer = ata_data_xfer, 588 589 .irq_handler = ata_interrupt, 590 .irq_clear = ata_bmdma_irq_clear, 591 .irq_on = ata_irq_on, 592 .irq_ack = ata_irq_ack, 593 594 .port_start = ata_port_start, 595 }; 596 597 static const struct ata_port_operations sis_133_early_ops = { 598 .port_disable = ata_port_disable, 599 .set_piomode = sis_100_set_piomode, 600 .set_dmamode = sis_133_early_set_dmamode, 601 .mode_filter = ata_pci_default_filter, 602 603 .tf_load = ata_tf_load, 604 .tf_read = ata_tf_read, 605 .check_status = ata_check_status, 606 .exec_command = ata_exec_command, 607 .dev_select = ata_std_dev_select, 608 609 .freeze = ata_bmdma_freeze, 610 .thaw = ata_bmdma_thaw, 611 .error_handler = sis_error_handler, 612 .post_internal_cmd = ata_bmdma_post_internal_cmd, 613 .cable_detect = sis_66_cable_detect, 614 615 .bmdma_setup = ata_bmdma_setup, 616 .bmdma_start = ata_bmdma_start, 617 .bmdma_stop = ata_bmdma_stop, 618 .bmdma_status = ata_bmdma_status, 619 .qc_prep = ata_qc_prep, 620 .qc_issue = ata_qc_issue_prot, 621 .data_xfer = ata_data_xfer, 622 623 .irq_handler = ata_interrupt, 624 .irq_clear = ata_bmdma_irq_clear, 625 .irq_on = ata_irq_on, 626 .irq_ack = ata_irq_ack, 627 628 .port_start = ata_port_start, 629 }; 630 631 static const struct ata_port_operations sis_100_ops = { 632 .port_disable = ata_port_disable, 633 .set_piomode = sis_100_set_piomode, 634 .set_dmamode = sis_100_set_dmamode, 635 .mode_filter = ata_pci_default_filter, 636 637 .tf_load = ata_tf_load, 638 .tf_read = ata_tf_read, 639 .check_status = ata_check_status, 640 .exec_command = ata_exec_command, 641 .dev_select = ata_std_dev_select, 642 643 .freeze = ata_bmdma_freeze, 644 .thaw = ata_bmdma_thaw, 645 .error_handler = sis_error_handler, 646 .post_internal_cmd = ata_bmdma_post_internal_cmd, 647 .cable_detect = sis_66_cable_detect, 648 649 .bmdma_setup = ata_bmdma_setup, 650 .bmdma_start = ata_bmdma_start, 651 .bmdma_stop = ata_bmdma_stop, 652 .bmdma_status = ata_bmdma_status, 653 .qc_prep = ata_qc_prep, 654 .qc_issue = ata_qc_issue_prot, 655 .data_xfer = ata_data_xfer, 656 657 .irq_handler = ata_interrupt, 658 .irq_clear = ata_bmdma_irq_clear, 659 .irq_on = ata_irq_on, 660 .irq_ack = ata_irq_ack, 661 662 .port_start = ata_port_start, 663 }; 664 665 static const struct ata_port_operations sis_66_ops = { 666 .port_disable = ata_port_disable, 667 .set_piomode = sis_old_set_piomode, 668 .set_dmamode = sis_66_set_dmamode, 669 .mode_filter = ata_pci_default_filter, 670 671 .tf_load = ata_tf_load, 672 .tf_read = ata_tf_read, 673 .check_status = ata_check_status, 674 .exec_command = ata_exec_command, 675 .dev_select = ata_std_dev_select, 676 .cable_detect = sis_66_cable_detect, 677 678 .freeze = ata_bmdma_freeze, 679 .thaw = ata_bmdma_thaw, 680 .error_handler = sis_error_handler, 681 .post_internal_cmd = ata_bmdma_post_internal_cmd, 682 683 .bmdma_setup = ata_bmdma_setup, 684 .bmdma_start = ata_bmdma_start, 685 .bmdma_stop = ata_bmdma_stop, 686 .bmdma_status = ata_bmdma_status, 687 .qc_prep = ata_qc_prep, 688 .qc_issue = ata_qc_issue_prot, 689 .data_xfer = ata_data_xfer, 690 691 .irq_handler = ata_interrupt, 692 .irq_clear = ata_bmdma_irq_clear, 693 .irq_on = ata_irq_on, 694 .irq_ack = ata_irq_ack, 695 696 .port_start = ata_port_start, 697 }; 698 699 static const struct ata_port_operations sis_old_ops = { 700 .port_disable = ata_port_disable, 701 .set_piomode = sis_old_set_piomode, 702 .set_dmamode = sis_old_set_dmamode, 703 .mode_filter = ata_pci_default_filter, 704 705 .tf_load = ata_tf_load, 706 .tf_read = ata_tf_read, 707 .check_status = ata_check_status, 708 .exec_command = ata_exec_command, 709 .dev_select = ata_std_dev_select, 710 711 .freeze = ata_bmdma_freeze, 712 .thaw = ata_bmdma_thaw, 713 .error_handler = sis_error_handler, 714 .post_internal_cmd = ata_bmdma_post_internal_cmd, 715 .cable_detect = ata_cable_40wire, 716 717 .bmdma_setup = ata_bmdma_setup, 718 .bmdma_start = ata_bmdma_start, 719 .bmdma_stop = ata_bmdma_stop, 720 .bmdma_status = ata_bmdma_status, 721 .qc_prep = ata_qc_prep, 722 .qc_issue = ata_qc_issue_prot, 723 .data_xfer = ata_data_xfer, 724 725 .irq_handler = ata_interrupt, 726 .irq_clear = ata_bmdma_irq_clear, 727 .irq_on = ata_irq_on, 728 .irq_ack = ata_irq_ack, 729 730 .port_start = ata_port_start, 731 }; 732 733 static const struct ata_port_info sis_info = { 734 .sht = &sis_sht, 735 .flags = ATA_FLAG_SLAVE_POSS, 736 .pio_mask = 0x1f, /* pio0-4 */ 737 .mwdma_mask = 0x07, 738 .udma_mask = 0, 739 .port_ops = &sis_old_ops, 740 }; 741 static const struct ata_port_info sis_info33 = { 742 .sht = &sis_sht, 743 .flags = ATA_FLAG_SLAVE_POSS, 744 .pio_mask = 0x1f, /* pio0-4 */ 745 .mwdma_mask = 0x07, 746 .udma_mask = ATA_UDMA2, /* UDMA 33 */ 747 .port_ops = &sis_old_ops, 748 }; 749 static const struct ata_port_info sis_info66 = { 750 .sht = &sis_sht, 751 .flags = ATA_FLAG_SLAVE_POSS, 752 .pio_mask = 0x1f, /* pio0-4 */ 753 .udma_mask = ATA_UDMA4, /* UDMA 66 */ 754 .port_ops = &sis_66_ops, 755 }; 756 static const struct ata_port_info sis_info100 = { 757 .sht = &sis_sht, 758 .flags = ATA_FLAG_SLAVE_POSS, 759 .pio_mask = 0x1f, /* pio0-4 */ 760 .udma_mask = ATA_UDMA5, 761 .port_ops = &sis_100_ops, 762 }; 763 static const struct ata_port_info sis_info100_early = { 764 .sht = &sis_sht, 765 .flags = ATA_FLAG_SLAVE_POSS, 766 .udma_mask = ATA_UDMA5, 767 .pio_mask = 0x1f, /* pio0-4 */ 768 .port_ops = &sis_66_ops, 769 }; 770 static const struct ata_port_info sis_info133 = { 771 .sht = &sis_sht, 772 .flags = ATA_FLAG_SLAVE_POSS, 773 .pio_mask = 0x1f, /* pio0-4 */ 774 .udma_mask = ATA_UDMA6, 775 .port_ops = &sis_133_ops, 776 }; 777 const struct ata_port_info sis_info133_for_sata = { 778 .sht = &sis_sht, 779 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 780 .pio_mask = 0x1f, /* pio0-4 */ 781 .udma_mask = ATA_UDMA6, 782 .port_ops = &sis_133_for_sata_ops, 783 }; 784 static const struct ata_port_info sis_info133_early = { 785 .sht = &sis_sht, 786 .flags = ATA_FLAG_SLAVE_POSS, 787 .pio_mask = 0x1f, /* pio0-4 */ 788 .udma_mask = ATA_UDMA6, 789 .port_ops = &sis_133_early_ops, 790 }; 791 792 /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 793 EXPORT_SYMBOL_GPL(sis_info133_for_sata); 794 795 static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 796 { 797 u16 regw; 798 u8 reg; 799 800 if (sis->info == &sis_info133) { 801 pci_read_config_word(pdev, 0x50, ®w); 802 if (regw & 0x08) 803 pci_write_config_word(pdev, 0x50, regw & ~0x08); 804 pci_read_config_word(pdev, 0x52, ®w); 805 if (regw & 0x08) 806 pci_write_config_word(pdev, 0x52, regw & ~0x08); 807 return; 808 } 809 810 if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 811 /* Fix up latency */ 812 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 813 /* Set compatibility bit */ 814 pci_read_config_byte(pdev, 0x49, ®); 815 if (!(reg & 0x01)) 816 pci_write_config_byte(pdev, 0x49, reg | 0x01); 817 return; 818 } 819 820 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 821 /* Fix up latency */ 822 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 823 /* Set compatibility bit */ 824 pci_read_config_byte(pdev, 0x52, ®); 825 if (!(reg & 0x04)) 826 pci_write_config_byte(pdev, 0x52, reg | 0x04); 827 return; 828 } 829 830 if (sis->info == &sis_info33) { 831 pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 832 if (( reg & 0x0F ) != 0x00) 833 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 834 /* Fall through to ATA16 fixup below */ 835 } 836 837 if (sis->info == &sis_info || sis->info == &sis_info33) { 838 /* force per drive recovery and active timings 839 needed on ATA_33 and below chips */ 840 pci_read_config_byte(pdev, 0x52, ®); 841 if (!(reg & 0x08)) 842 pci_write_config_byte(pdev, 0x52, reg|0x08); 843 return; 844 } 845 846 BUG(); 847 } 848 849 /** 850 * sis_init_one - Register SiS ATA PCI device with kernel services 851 * @pdev: PCI device to register 852 * @ent: Entry in sis_pci_tbl matching with @pdev 853 * 854 * Called from kernel PCI layer. We probe for combined mode (sigh), 855 * and then hand over control to libata, for it to do the rest. 856 * 857 * LOCKING: 858 * Inherited from PCI layer (may sleep). 859 * 860 * RETURNS: 861 * Zero on success, or -ERRNO value. 862 */ 863 864 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 865 { 866 static int printed_version; 867 struct ata_port_info port; 868 const struct ata_port_info *ppi[] = { &port, NULL }; 869 struct pci_dev *host = NULL; 870 struct sis_chipset *chipset = NULL; 871 struct sis_chipset *sets; 872 873 static struct sis_chipset sis_chipsets[] = { 874 875 { 0x0968, &sis_info133 }, 876 { 0x0966, &sis_info133 }, 877 { 0x0965, &sis_info133 }, 878 { 0x0745, &sis_info100 }, 879 { 0x0735, &sis_info100 }, 880 { 0x0733, &sis_info100 }, 881 { 0x0635, &sis_info100 }, 882 { 0x0633, &sis_info100 }, 883 884 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 885 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 886 887 { 0x0640, &sis_info66 }, 888 { 0x0630, &sis_info66 }, 889 { 0x0620, &sis_info66 }, 890 { 0x0540, &sis_info66 }, 891 { 0x0530, &sis_info66 }, 892 893 { 0x5600, &sis_info33 }, 894 { 0x5598, &sis_info33 }, 895 { 0x5597, &sis_info33 }, 896 { 0x5591, &sis_info33 }, 897 { 0x5582, &sis_info33 }, 898 { 0x5581, &sis_info33 }, 899 900 { 0x5596, &sis_info }, 901 { 0x5571, &sis_info }, 902 { 0x5517, &sis_info }, 903 { 0x5511, &sis_info }, 904 905 {0} 906 }; 907 static struct sis_chipset sis133_early = { 908 0x0, &sis_info133_early 909 }; 910 static struct sis_chipset sis133 = { 911 0x0, &sis_info133 912 }; 913 static struct sis_chipset sis100_early = { 914 0x0, &sis_info100_early 915 }; 916 static struct sis_chipset sis100 = { 917 0x0, &sis_info100 918 }; 919 920 if (!printed_version++) 921 dev_printk(KERN_DEBUG, &pdev->dev, 922 "version " DRV_VERSION "\n"); 923 924 /* We have to find the bridge first */ 925 926 for (sets = &sis_chipsets[0]; sets->device; sets++) { 927 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 928 if (host != NULL) { 929 chipset = sets; /* Match found */ 930 if (sets->device == 0x630) { /* SIS630 */ 931 u8 host_rev; 932 pci_read_config_byte(host, PCI_REVISION_ID, &host_rev); 933 if (host_rev >= 0x30) /* 630 ET */ 934 chipset = &sis100_early; 935 } 936 break; 937 } 938 } 939 940 /* Look for concealed bridges */ 941 if (chipset == NULL) { 942 /* Second check */ 943 u32 idemisc; 944 u16 trueid; 945 946 /* Disable ID masking and register remapping then 947 see what the real ID is */ 948 949 pci_read_config_dword(pdev, 0x54, &idemisc); 950 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 951 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 952 pci_write_config_dword(pdev, 0x54, idemisc); 953 954 switch(trueid) { 955 case 0x5518: /* SIS 962/963 */ 956 chipset = &sis133; 957 if ((idemisc & 0x40000000) == 0) { 958 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 959 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); 960 } 961 break; 962 case 0x0180: /* SIS 965/965L */ 963 chipset = &sis133; 964 break; 965 case 0x1180: /* SIS 966/966L */ 966 chipset = &sis133; 967 break; 968 } 969 } 970 971 /* Further check */ 972 if (chipset == NULL) { 973 struct pci_dev *lpc_bridge; 974 u16 trueid; 975 u8 prefctl; 976 u8 idecfg; 977 u8 sbrev; 978 979 /* Try the second unmasking technique */ 980 pci_read_config_byte(pdev, 0x4a, &idecfg); 981 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 982 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 983 pci_write_config_byte(pdev, 0x4a, idecfg); 984 985 switch(trueid) { 986 case 0x5517: 987 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 988 if (lpc_bridge == NULL) 989 break; 990 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev); 991 pci_read_config_byte(pdev, 0x49, &prefctl); 992 pci_dev_put(lpc_bridge); 993 994 if (sbrev == 0x10 && (prefctl & 0x80)) { 995 chipset = &sis133_early; 996 break; 997 } 998 chipset = &sis100; 999 break; 1000 } 1001 } 1002 pci_dev_put(host); 1003 1004 /* No chipset info, no support */ 1005 if (chipset == NULL) 1006 return -ENODEV; 1007 1008 port = *chipset->info; 1009 port.private_data = chipset; 1010 1011 sis_fixup(pdev, chipset); 1012 1013 return ata_pci_init_one(pdev, ppi); 1014 } 1015 1016 static const struct pci_device_id sis_pci_tbl[] = { 1017 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 1018 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 1019 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 1020 1021 { } 1022 }; 1023 1024 static struct pci_driver sis_pci_driver = { 1025 .name = DRV_NAME, 1026 .id_table = sis_pci_tbl, 1027 .probe = sis_init_one, 1028 .remove = ata_pci_remove_one, 1029 #ifdef CONFIG_PM 1030 .suspend = ata_pci_device_suspend, 1031 .resume = ata_pci_device_resume, 1032 #endif 1033 }; 1034 1035 static int __init sis_init(void) 1036 { 1037 return pci_register_driver(&sis_pci_driver); 1038 } 1039 1040 static void __exit sis_exit(void) 1041 { 1042 pci_unregister_driver(&sis_pci_driver); 1043 } 1044 1045 module_init(sis_init); 1046 module_exit(sis_exit); 1047 1048 MODULE_AUTHOR("Alan Cox"); 1049 MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 1050 MODULE_LICENSE("GPL"); 1051 MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 1052 MODULE_VERSION(DRV_VERSION); 1053 1054