1669a5db4SJeff Garzik /* 2669a5db4SJeff Garzik * pata_sis.c - SiS ATA driver 3669a5db4SJeff Garzik * 4ab771630SAlan Cox * (C) 2005 Red Hat 54761c06cSBartlomiej Zolnierkiewicz * (C) 2007 Bartlomiej Zolnierkiewicz 6669a5db4SJeff Garzik * 7669a5db4SJeff Garzik * Based upon linux/drivers/ide/pci/sis5513.c 8669a5db4SJeff Garzik * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 9669a5db4SJeff Garzik * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 10669a5db4SJeff Garzik * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 11669a5db4SJeff Garzik * SiS Taiwan : for direct support and hardware. 12669a5db4SJeff Garzik * Daniela Engert : for initial ATA100 advices and numerous others. 13669a5db4SJeff Garzik * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 14669a5db4SJeff Garzik * for checking code correctness, providing patches. 15669a5db4SJeff Garzik * Original tests and design on the SiS620 chipset. 16669a5db4SJeff Garzik * ATA100 tests and design on the SiS735 chipset. 17669a5db4SJeff Garzik * ATA16/33 support from specs 18669a5db4SJeff Garzik * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 19669a5db4SJeff Garzik * 20669a5db4SJeff Garzik * 21669a5db4SJeff Garzik * TODO 22669a5db4SJeff Garzik * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 23669a5db4SJeff Garzik * More Testing 24669a5db4SJeff Garzik */ 25669a5db4SJeff Garzik 26669a5db4SJeff Garzik #include <linux/kernel.h> 27669a5db4SJeff Garzik #include <linux/module.h> 28669a5db4SJeff Garzik #include <linux/pci.h> 29669a5db4SJeff Garzik #include <linux/init.h> 30669a5db4SJeff Garzik #include <linux/blkdev.h> 31669a5db4SJeff Garzik #include <linux/delay.h> 32669a5db4SJeff Garzik #include <linux/device.h> 33669a5db4SJeff Garzik #include <scsi/scsi_host.h> 34669a5db4SJeff Garzik #include <linux/libata.h> 35669a5db4SJeff Garzik #include <linux/ata.h> 364bb64fb9SAlan #include "sis.h" 37669a5db4SJeff Garzik 38669a5db4SJeff Garzik #define DRV_NAME "pata_sis" 394761c06cSBartlomiej Zolnierkiewicz #define DRV_VERSION "0.5.2" 40669a5db4SJeff Garzik 41669a5db4SJeff Garzik struct sis_chipset { 42669a5db4SJeff Garzik u16 device; /* PCI host ID */ 431626aeb8STejun Heo const struct ata_port_info *info; /* Info block */ 44669a5db4SJeff Garzik /* Probably add family, cable detect type etc here to clean 45669a5db4SJeff Garzik up code later */ 46669a5db4SJeff Garzik }; 47669a5db4SJeff Garzik 487dcbc1f2SJakub W. Jozwicki J struct sis_laptop { 497dcbc1f2SJakub W. Jozwicki J u16 device; 507dcbc1f2SJakub W. Jozwicki J u16 subvendor; 517dcbc1f2SJakub W. Jozwicki J u16 subdevice; 527dcbc1f2SJakub W. Jozwicki J }; 537dcbc1f2SJakub W. Jozwicki J 547dcbc1f2SJakub W. Jozwicki J static const struct sis_laptop sis_laptop[] = { 557dcbc1f2SJakub W. Jozwicki J /* devid, subvendor, subdev */ 567dcbc1f2SJakub W. Jozwicki J { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 574f2d47cfSAlan Cox { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ 581f71d067SGabriel C { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ 59edb80471SKai Krakow { 0x5513, 0x1039, 0x5513 }, /* Targa Visionary 1000 */ 607dcbc1f2SJakub W. Jozwicki J /* end marker */ 617dcbc1f2SJakub W. Jozwicki J { 0, } 627dcbc1f2SJakub W. Jozwicki J }; 637dcbc1f2SJakub W. Jozwicki J 647dcbc1f2SJakub W. Jozwicki J static int sis_short_ata40(struct pci_dev *dev) 657dcbc1f2SJakub W. Jozwicki J { 667dcbc1f2SJakub W. Jozwicki J const struct sis_laptop *lap = &sis_laptop[0]; 677dcbc1f2SJakub W. Jozwicki J 687dcbc1f2SJakub W. Jozwicki J while (lap->device) { 697dcbc1f2SJakub W. Jozwicki J if (lap->device == dev->device && 707dcbc1f2SJakub W. Jozwicki J lap->subvendor == dev->subsystem_vendor && 717dcbc1f2SJakub W. Jozwicki J lap->subdevice == dev->subsystem_device) 727dcbc1f2SJakub W. Jozwicki J return 1; 737dcbc1f2SJakub W. Jozwicki J lap++; 747dcbc1f2SJakub W. Jozwicki J } 757dcbc1f2SJakub W. Jozwicki J 767dcbc1f2SJakub W. Jozwicki J return 0; 777dcbc1f2SJakub W. Jozwicki J } 787dcbc1f2SJakub W. Jozwicki J 79669a5db4SJeff Garzik /** 80dd668d15SAlan Cox * sis_old_port_base - return PCI configuration base for dev 81669a5db4SJeff Garzik * @adev: device 82669a5db4SJeff Garzik * 83669a5db4SJeff Garzik * Returns the base of the PCI configuration registers for this port 84669a5db4SJeff Garzik * number. 85669a5db4SJeff Garzik */ 86669a5db4SJeff Garzik 87dd668d15SAlan Cox static int sis_old_port_base(struct ata_device *adev) 88669a5db4SJeff Garzik { 899af5c9c9STejun Heo return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); 90669a5db4SJeff Garzik } 91669a5db4SJeff Garzik 92669a5db4SJeff Garzik /** 932e413f51SAlan Cox * sis_133_cable_detect - check for 40/80 pin 94669a5db4SJeff Garzik * @ap: Port 95d4b2bab4STejun Heo * @deadline: deadline jiffies for the operation 96669a5db4SJeff Garzik * 97669a5db4SJeff Garzik * Perform cable detection for the later UDMA133 capable 98669a5db4SJeff Garzik * SiS chipset. 99669a5db4SJeff Garzik */ 100669a5db4SJeff Garzik 1012e413f51SAlan Cox static int sis_133_cable_detect(struct ata_port *ap) 1022e413f51SAlan Cox { 1032e413f51SAlan Cox struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1042e413f51SAlan Cox u16 tmp; 1052e413f51SAlan Cox 1062e413f51SAlan Cox /* The top bit of this register is the cable detect bit */ 1072e413f51SAlan Cox pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 1082e413f51SAlan Cox if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 1092e413f51SAlan Cox return ATA_CBL_PATA40; 1102e413f51SAlan Cox return ATA_CBL_PATA80; 1112e413f51SAlan Cox } 1122e413f51SAlan Cox 1132e413f51SAlan Cox /** 1142e413f51SAlan Cox * sis_66_cable_detect - check for 40/80 pin 1152e413f51SAlan Cox * @ap: Port 116d4b2bab4STejun Heo * @deadline: deadline jiffies for the operation 1172e413f51SAlan Cox * 1182e413f51SAlan Cox * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 1192e413f51SAlan Cox * SiS IDE controllers. 1202e413f51SAlan Cox */ 1212e413f51SAlan Cox 1222e413f51SAlan Cox static int sis_66_cable_detect(struct ata_port *ap) 1232e413f51SAlan Cox { 1242e413f51SAlan Cox struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1252e413f51SAlan Cox u8 tmp; 1262e413f51SAlan Cox 1272e413f51SAlan Cox /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 1282e413f51SAlan Cox pci_read_config_byte(pdev, 0x48, &tmp); 1292e413f51SAlan Cox tmp >>= ap->port_no; 1302e413f51SAlan Cox if ((tmp & 0x10) && !sis_short_ata40(pdev)) 1312e413f51SAlan Cox return ATA_CBL_PATA40; 1322e413f51SAlan Cox return ATA_CBL_PATA80; 1332e413f51SAlan Cox } 1342e413f51SAlan Cox 1352e413f51SAlan Cox 1362e413f51SAlan Cox /** 1372e413f51SAlan Cox * sis_pre_reset - probe begin 138cc0680a5STejun Heo * @link: ATA link 139d4b2bab4STejun Heo * @deadline: deadline jiffies for the operation 1402e413f51SAlan Cox * 1412e413f51SAlan Cox * Set up cable type and use generic probe init 1422e413f51SAlan Cox */ 1432e413f51SAlan Cox 144cc0680a5STejun Heo static int sis_pre_reset(struct ata_link *link, unsigned long deadline) 145669a5db4SJeff Garzik { 146669a5db4SJeff Garzik static const struct pci_bits sis_enable_bits[] = { 147669a5db4SJeff Garzik { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 148669a5db4SJeff Garzik { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 149669a5db4SJeff Garzik }; 150669a5db4SJeff Garzik 151cc0680a5STejun Heo struct ata_port *ap = link->ap; 152669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 153669a5db4SJeff Garzik 154c961922bSAlan Cox if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 155c961922bSAlan Cox return -ENOENT; 156d4b2bab4STejun Heo 15715ce0943SAlan Cox /* Clear the FIFO settings. We can't enable the FIFO until 15815ce0943SAlan Cox we know we are poking at a disk */ 15915ce0943SAlan Cox pci_write_config_byte(pdev, 0x4B, 0); 1609363c382STejun Heo return ata_sff_prereset(link, deadline); 161669a5db4SJeff Garzik } 162669a5db4SJeff Garzik 1632e413f51SAlan Cox 164669a5db4SJeff Garzik /** 165669a5db4SJeff Garzik * sis_set_fifo - Set RWP fifo bits for this device 166669a5db4SJeff Garzik * @ap: Port 167669a5db4SJeff Garzik * @adev: Device 168669a5db4SJeff Garzik * 169669a5db4SJeff Garzik * SIS chipsets implement prefetch/postwrite bits for each device 170669a5db4SJeff Garzik * on both channels. This functionality is not ATAPI compatible and 171669a5db4SJeff Garzik * must be configured according to the class of device present 172669a5db4SJeff Garzik */ 173669a5db4SJeff Garzik 174669a5db4SJeff Garzik static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 175669a5db4SJeff Garzik { 176669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 177669a5db4SJeff Garzik u8 fifoctrl; 178669a5db4SJeff Garzik u8 mask = 0x11; 179669a5db4SJeff Garzik 180669a5db4SJeff Garzik mask <<= (2 * ap->port_no); 181669a5db4SJeff Garzik mask <<= adev->devno; 182669a5db4SJeff Garzik 183669a5db4SJeff Garzik /* This holds various bits including the FIFO control */ 184669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x4B, &fifoctrl); 185669a5db4SJeff Garzik fifoctrl &= ~mask; 186669a5db4SJeff Garzik 187669a5db4SJeff Garzik /* Enable for ATA (disk) only */ 188669a5db4SJeff Garzik if (adev->class == ATA_DEV_ATA) 189669a5db4SJeff Garzik fifoctrl |= mask; 190669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4B, fifoctrl); 191669a5db4SJeff Garzik } 192669a5db4SJeff Garzik 193669a5db4SJeff Garzik /** 194669a5db4SJeff Garzik * sis_old_set_piomode - Initialize host controller PATA PIO timings 195669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 196669a5db4SJeff Garzik * @adev: Device we are configuring for. 197669a5db4SJeff Garzik * 198669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 199669a5db4SJeff Garzik * function handles PIO set up for all chips that are pre ATA100 and 200669a5db4SJeff Garzik * also early ATA100 devices. 201669a5db4SJeff Garzik * 202669a5db4SJeff Garzik * LOCKING: 203669a5db4SJeff Garzik * None (inherited from caller). 204669a5db4SJeff Garzik */ 205669a5db4SJeff Garzik 206669a5db4SJeff Garzik static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 207669a5db4SJeff Garzik { 208669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 209dd668d15SAlan Cox int port = sis_old_port_base(adev); 210669a5db4SJeff Garzik u8 t1, t2; 211669a5db4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 212669a5db4SJeff Garzik 213669a5db4SJeff Garzik const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 214669a5db4SJeff Garzik const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 215669a5db4SJeff Garzik 216669a5db4SJeff Garzik sis_set_fifo(ap, adev); 217669a5db4SJeff Garzik 218669a5db4SJeff Garzik pci_read_config_byte(pdev, port, &t1); 219669a5db4SJeff Garzik pci_read_config_byte(pdev, port + 1, &t2); 220669a5db4SJeff Garzik 221669a5db4SJeff Garzik t1 &= ~0x0F; /* Clear active/recovery timings */ 222669a5db4SJeff Garzik t2 &= ~0x07; 223669a5db4SJeff Garzik 224669a5db4SJeff Garzik t1 |= active[speed]; 225669a5db4SJeff Garzik t2 |= recovery[speed]; 226669a5db4SJeff Garzik 227669a5db4SJeff Garzik pci_write_config_byte(pdev, port, t1); 228669a5db4SJeff Garzik pci_write_config_byte(pdev, port + 1, t2); 229669a5db4SJeff Garzik } 230669a5db4SJeff Garzik 231669a5db4SJeff Garzik /** 2324761c06cSBartlomiej Zolnierkiewicz * sis_100_set_piomode - Initialize host controller PATA PIO timings 233669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 234669a5db4SJeff Garzik * @adev: Device we are configuring for. 235669a5db4SJeff Garzik * 236669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 237669a5db4SJeff Garzik * function handles PIO set up for ATA100 devices and early ATA133. 238669a5db4SJeff Garzik * 239669a5db4SJeff Garzik * LOCKING: 240669a5db4SJeff Garzik * None (inherited from caller). 241669a5db4SJeff Garzik */ 242669a5db4SJeff Garzik 243669a5db4SJeff Garzik static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 244669a5db4SJeff Garzik { 245669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 246dd668d15SAlan Cox int port = sis_old_port_base(adev); 247669a5db4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 248669a5db4SJeff Garzik 249669a5db4SJeff Garzik const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 250669a5db4SJeff Garzik 251669a5db4SJeff Garzik sis_set_fifo(ap, adev); 252669a5db4SJeff Garzik 253669a5db4SJeff Garzik pci_write_config_byte(pdev, port, actrec[speed]); 254669a5db4SJeff Garzik } 255669a5db4SJeff Garzik 256669a5db4SJeff Garzik /** 2574761c06cSBartlomiej Zolnierkiewicz * sis_133_set_piomode - Initialize host controller PATA PIO timings 258669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 259669a5db4SJeff Garzik * @adev: Device we are configuring for. 260669a5db4SJeff Garzik * 261669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 262669a5db4SJeff Garzik * function handles PIO set up for the later ATA133 devices. 263669a5db4SJeff Garzik * 264669a5db4SJeff Garzik * LOCKING: 265669a5db4SJeff Garzik * None (inherited from caller). 266669a5db4SJeff Garzik */ 267669a5db4SJeff Garzik 268669a5db4SJeff Garzik static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 269669a5db4SJeff Garzik { 270669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 271669a5db4SJeff Garzik int port = 0x40; 272669a5db4SJeff Garzik u32 t1; 273669a5db4SJeff Garzik u32 reg54; 274669a5db4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 275669a5db4SJeff Garzik 276669a5db4SJeff Garzik const u32 timing133[] = { 277669a5db4SJeff Garzik 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 278669a5db4SJeff Garzik 0x0C266000, 279669a5db4SJeff Garzik 0x04263000, 280669a5db4SJeff Garzik 0x0C0A3000, 281669a5db4SJeff Garzik 0x05093000 282669a5db4SJeff Garzik }; 283669a5db4SJeff Garzik const u32 timing100[] = { 284669a5db4SJeff Garzik 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 285669a5db4SJeff Garzik 0x091C4000, 286669a5db4SJeff Garzik 0x031C2000, 287669a5db4SJeff Garzik 0x09072000, 288669a5db4SJeff Garzik 0x04062000 289669a5db4SJeff Garzik }; 290669a5db4SJeff Garzik 291669a5db4SJeff Garzik sis_set_fifo(ap, adev); 292669a5db4SJeff Garzik 293669a5db4SJeff Garzik /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 294669a5db4SJeff Garzik pci_read_config_dword(pdev, 0x54, ®54); 295669a5db4SJeff Garzik if (reg54 & 0x40000000) 296669a5db4SJeff Garzik port = 0x70; 297669a5db4SJeff Garzik port += 8 * ap->port_no + 4 * adev->devno; 298669a5db4SJeff Garzik 299669a5db4SJeff Garzik pci_read_config_dword(pdev, port, &t1); 300669a5db4SJeff Garzik t1 &= 0xC0C00FFF; /* Mask out timing */ 301669a5db4SJeff Garzik 302669a5db4SJeff Garzik if (t1 & 0x08) /* 100 or 133 ? */ 303669a5db4SJeff Garzik t1 |= timing133[speed]; 304669a5db4SJeff Garzik else 305669a5db4SJeff Garzik t1 |= timing100[speed]; 306669a5db4SJeff Garzik pci_write_config_byte(pdev, port, t1); 307669a5db4SJeff Garzik } 308669a5db4SJeff Garzik 309669a5db4SJeff Garzik /** 310669a5db4SJeff Garzik * sis_old_set_dmamode - Initialize host controller PATA DMA timings 311669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 312669a5db4SJeff Garzik * @adev: Device to program 313669a5db4SJeff Garzik * 314669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 315669a5db4SJeff Garzik * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 316669a5db4SJeff Garzik * the old ide/pci driver. 317669a5db4SJeff Garzik * 318669a5db4SJeff Garzik * LOCKING: 319669a5db4SJeff Garzik * None (inherited from caller). 320669a5db4SJeff Garzik */ 321669a5db4SJeff Garzik 322669a5db4SJeff Garzik static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 323669a5db4SJeff Garzik { 324669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 325669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 326dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 327669a5db4SJeff Garzik u16 timing; 328669a5db4SJeff Garzik 3294761c06cSBartlomiej Zolnierkiewicz const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 330669a5db4SJeff Garzik const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 331669a5db4SJeff Garzik 332669a5db4SJeff Garzik pci_read_config_word(pdev, drive_pci, &timing); 333669a5db4SJeff Garzik 334669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 335669a5db4SJeff Garzik /* bits 3-0 hold recovery timing bits 8-10 active timing and 3361967b7ffSJoe Perches the higher bits are dependant on the device */ 337669a5db4SJeff Garzik timing &= ~0x870F; 338669a5db4SJeff Garzik timing |= mwdma_bits[speed]; 339669a5db4SJeff Garzik } else { 340669a5db4SJeff Garzik /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 341669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 342669a5db4SJeff Garzik timing &= ~0x6000; 343669a5db4SJeff Garzik timing |= udma_bits[speed]; 344669a5db4SJeff Garzik } 3454761c06cSBartlomiej Zolnierkiewicz pci_write_config_word(pdev, drive_pci, timing); 346669a5db4SJeff Garzik } 347669a5db4SJeff Garzik 348669a5db4SJeff Garzik /** 349669a5db4SJeff Garzik * sis_66_set_dmamode - Initialize host controller PATA DMA timings 350669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 351669a5db4SJeff Garzik * @adev: Device to program 352669a5db4SJeff Garzik * 353669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 354669a5db4SJeff Garzik * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 355669a5db4SJeff Garzik * the old ide/pci driver. 356669a5db4SJeff Garzik * 357669a5db4SJeff Garzik * LOCKING: 358669a5db4SJeff Garzik * None (inherited from caller). 359669a5db4SJeff Garzik */ 360669a5db4SJeff Garzik 361669a5db4SJeff Garzik static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 362669a5db4SJeff Garzik { 363669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 364669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 365dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 366669a5db4SJeff Garzik u16 timing; 367669a5db4SJeff Garzik 368edeb614cSTejun Heo /* MWDMA 0-2 and UDMA 0-5 */ 3694761c06cSBartlomiej Zolnierkiewicz const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 370edeb614cSTejun Heo const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; 371669a5db4SJeff Garzik 372669a5db4SJeff Garzik pci_read_config_word(pdev, drive_pci, &timing); 373669a5db4SJeff Garzik 374669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 375669a5db4SJeff Garzik /* bits 3-0 hold recovery timing bits 8-10 active timing and 3761967b7ffSJoe Perches the higher bits are dependant on the device, bit 15 udma */ 377669a5db4SJeff Garzik timing &= ~0x870F; 378669a5db4SJeff Garzik timing |= mwdma_bits[speed]; 379669a5db4SJeff Garzik } else { 380669a5db4SJeff Garzik /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 381669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 382dd668d15SAlan Cox timing &= ~0xF000; 383669a5db4SJeff Garzik timing |= udma_bits[speed]; 384669a5db4SJeff Garzik } 385669a5db4SJeff Garzik pci_write_config_word(pdev, drive_pci, timing); 386669a5db4SJeff Garzik } 387669a5db4SJeff Garzik 388669a5db4SJeff Garzik /** 389669a5db4SJeff Garzik * sis_100_set_dmamode - Initialize host controller PATA DMA timings 390669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 391669a5db4SJeff Garzik * @adev: Device to program 392669a5db4SJeff Garzik * 393669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 394669a5db4SJeff Garzik * Handles UDMA66 and early UDMA100 devices. 395669a5db4SJeff Garzik * 396669a5db4SJeff Garzik * LOCKING: 397669a5db4SJeff Garzik * None (inherited from caller). 398669a5db4SJeff Garzik */ 399669a5db4SJeff Garzik 400669a5db4SJeff Garzik static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 401669a5db4SJeff Garzik { 402669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 403669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 404dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 405dd668d15SAlan Cox u8 timing; 406669a5db4SJeff Garzik 407dd668d15SAlan Cox const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 408669a5db4SJeff Garzik 409dd668d15SAlan Cox pci_read_config_byte(pdev, drive_pci + 1, &timing); 410669a5db4SJeff Garzik 411669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 412669a5db4SJeff Garzik /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 413669a5db4SJeff Garzik } else { 414dd668d15SAlan Cox /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 415669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 416dd668d15SAlan Cox timing &= ~0x8F; 417669a5db4SJeff Garzik timing |= udma_bits[speed]; 418669a5db4SJeff Garzik } 419dd668d15SAlan Cox pci_write_config_byte(pdev, drive_pci + 1, timing); 420669a5db4SJeff Garzik } 421669a5db4SJeff Garzik 422669a5db4SJeff Garzik /** 423669a5db4SJeff Garzik * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 424669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 425669a5db4SJeff Garzik * @adev: Device to program 426669a5db4SJeff Garzik * 427669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 4284761c06cSBartlomiej Zolnierkiewicz * Handles early SiS 961 bridges. 429669a5db4SJeff Garzik * 430669a5db4SJeff Garzik * LOCKING: 431669a5db4SJeff Garzik * None (inherited from caller). 432669a5db4SJeff Garzik */ 433669a5db4SJeff Garzik 434669a5db4SJeff Garzik static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 435669a5db4SJeff Garzik { 436669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 437669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 438dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 439dd668d15SAlan Cox u8 timing; 440dd668d15SAlan Cox /* Low 4 bits are timing */ 441dd668d15SAlan Cox static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 442669a5db4SJeff Garzik 443dd668d15SAlan Cox pci_read_config_byte(pdev, drive_pci + 1, &timing); 444669a5db4SJeff Garzik 445669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 446669a5db4SJeff Garzik /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 447669a5db4SJeff Garzik } else { 448dd668d15SAlan Cox /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 449669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 450dd668d15SAlan Cox timing &= ~0x8F; 451669a5db4SJeff Garzik timing |= udma_bits[speed]; 452669a5db4SJeff Garzik } 453dd668d15SAlan Cox pci_write_config_byte(pdev, drive_pci + 1, timing); 454669a5db4SJeff Garzik } 455669a5db4SJeff Garzik 456669a5db4SJeff Garzik /** 457669a5db4SJeff Garzik * sis_133_set_dmamode - Initialize host controller PATA DMA timings 458669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 459669a5db4SJeff Garzik * @adev: Device to program 460669a5db4SJeff Garzik * 461669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 462669a5db4SJeff Garzik * 463669a5db4SJeff Garzik * LOCKING: 464669a5db4SJeff Garzik * None (inherited from caller). 465669a5db4SJeff Garzik */ 466669a5db4SJeff Garzik 467669a5db4SJeff Garzik static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 468669a5db4SJeff Garzik { 469669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 470669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 471669a5db4SJeff Garzik int port = 0x40; 472669a5db4SJeff Garzik u32 t1; 473669a5db4SJeff Garzik u32 reg54; 474669a5db4SJeff Garzik 475669a5db4SJeff Garzik /* bits 4- cycle time 8 - cvs time */ 4762e413f51SAlan Cox static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 4772e413f51SAlan Cox static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 478669a5db4SJeff Garzik 479669a5db4SJeff Garzik /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 480669a5db4SJeff Garzik pci_read_config_dword(pdev, 0x54, ®54); 481669a5db4SJeff Garzik if (reg54 & 0x40000000) 482669a5db4SJeff Garzik port = 0x70; 483669a5db4SJeff Garzik port += (8 * ap->port_no) + (4 * adev->devno); 484669a5db4SJeff Garzik 485669a5db4SJeff Garzik pci_read_config_dword(pdev, port, &t1); 486669a5db4SJeff Garzik 487669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 488669a5db4SJeff Garzik t1 &= ~0x00000004; 489669a5db4SJeff Garzik /* FIXME: need data sheet to add MWDMA here. Also lacking on 490669a5db4SJeff Garzik ide/pci driver */ 491669a5db4SJeff Garzik } else { 492669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 493669a5db4SJeff Garzik /* if & 8 no UDMA133 - need info for ... */ 494669a5db4SJeff Garzik t1 &= ~0x00000FF0; 495669a5db4SJeff Garzik t1 |= 0x00000004; 496669a5db4SJeff Garzik if (t1 & 0x08) 497669a5db4SJeff Garzik t1 |= timing_u133[speed]; 498669a5db4SJeff Garzik else 499669a5db4SJeff Garzik t1 |= timing_u100[speed]; 500669a5db4SJeff Garzik } 501669a5db4SJeff Garzik pci_write_config_dword(pdev, port, t1); 502669a5db4SJeff Garzik } 503669a5db4SJeff Garzik 504669a5db4SJeff Garzik static struct scsi_host_template sis_sht = { 50568d1d07bSTejun Heo ATA_BMDMA_SHT(DRV_NAME), 506669a5db4SJeff Garzik }; 507669a5db4SJeff Garzik 508029cfd6bSTejun Heo static struct ata_port_operations sis_133_for_sata_ops = { 509029cfd6bSTejun Heo .inherits = &ata_bmdma_port_ops, 510669a5db4SJeff Garzik .set_piomode = sis_133_set_piomode, 511669a5db4SJeff Garzik .set_dmamode = sis_133_set_dmamode, 512029cfd6bSTejun Heo .cable_detect = sis_133_cable_detect, 513029cfd6bSTejun Heo }; 514669a5db4SJeff Garzik 515029cfd6bSTejun Heo static struct ata_port_operations sis_base_ops = { 516029cfd6bSTejun Heo .inherits = &ata_bmdma_port_ops, 517a1efdabaSTejun Heo .prereset = sis_pre_reset, 518669a5db4SJeff Garzik }; 519669a5db4SJeff Garzik 520029cfd6bSTejun Heo static struct ata_port_operations sis_133_ops = { 521029cfd6bSTejun Heo .inherits = &sis_base_ops, 522a3cabb27SUwe Koziolek .set_piomode = sis_133_set_piomode, 523a3cabb27SUwe Koziolek .set_dmamode = sis_133_set_dmamode, 524a3cabb27SUwe Koziolek .cable_detect = sis_133_cable_detect, 525a3cabb27SUwe Koziolek }; 526a3cabb27SUwe Koziolek 527029cfd6bSTejun Heo static struct ata_port_operations sis_133_early_ops = { 528029cfd6bSTejun Heo .inherits = &sis_base_ops, 529669a5db4SJeff Garzik .set_piomode = sis_100_set_piomode, 530669a5db4SJeff Garzik .set_dmamode = sis_133_early_set_dmamode, 5312e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 532669a5db4SJeff Garzik }; 533669a5db4SJeff Garzik 534029cfd6bSTejun Heo static struct ata_port_operations sis_100_ops = { 535029cfd6bSTejun Heo .inherits = &sis_base_ops, 536669a5db4SJeff Garzik .set_piomode = sis_100_set_piomode, 537669a5db4SJeff Garzik .set_dmamode = sis_100_set_dmamode, 5382e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 539669a5db4SJeff Garzik }; 540669a5db4SJeff Garzik 541029cfd6bSTejun Heo static struct ata_port_operations sis_66_ops = { 542029cfd6bSTejun Heo .inherits = &sis_base_ops, 543669a5db4SJeff Garzik .set_piomode = sis_old_set_piomode, 544669a5db4SJeff Garzik .set_dmamode = sis_66_set_dmamode, 5452e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 546669a5db4SJeff Garzik }; 547669a5db4SJeff Garzik 548029cfd6bSTejun Heo static struct ata_port_operations sis_old_ops = { 549029cfd6bSTejun Heo .inherits = &sis_base_ops, 550669a5db4SJeff Garzik .set_piomode = sis_old_set_piomode, 551669a5db4SJeff Garzik .set_dmamode = sis_old_set_dmamode, 5522e413f51SAlan Cox .cable_detect = ata_cable_40wire, 553669a5db4SJeff Garzik }; 554669a5db4SJeff Garzik 5551626aeb8STejun Heo static const struct ata_port_info sis_info = { 5561d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 557669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 558669a5db4SJeff Garzik .mwdma_mask = 0x07, 559669a5db4SJeff Garzik .udma_mask = 0, 560669a5db4SJeff Garzik .port_ops = &sis_old_ops, 561669a5db4SJeff Garzik }; 5621626aeb8STejun Heo static const struct ata_port_info sis_info33 = { 5631d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 564669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 565669a5db4SJeff Garzik .mwdma_mask = 0x07, 566669a5db4SJeff Garzik .udma_mask = ATA_UDMA2, /* UDMA 33 */ 567669a5db4SJeff Garzik .port_ops = &sis_old_ops, 568669a5db4SJeff Garzik }; 5691626aeb8STejun Heo static const struct ata_port_info sis_info66 = { 5701d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 571669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 572669a5db4SJeff Garzik .udma_mask = ATA_UDMA4, /* UDMA 66 */ 573669a5db4SJeff Garzik .port_ops = &sis_66_ops, 574669a5db4SJeff Garzik }; 5751626aeb8STejun Heo static const struct ata_port_info sis_info100 = { 5761d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 577669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 578669a5db4SJeff Garzik .udma_mask = ATA_UDMA5, 579669a5db4SJeff Garzik .port_ops = &sis_100_ops, 580669a5db4SJeff Garzik }; 5811626aeb8STejun Heo static const struct ata_port_info sis_info100_early = { 5821d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 583669a5db4SJeff Garzik .udma_mask = ATA_UDMA5, 584669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 585669a5db4SJeff Garzik .port_ops = &sis_66_ops, 586669a5db4SJeff Garzik }; 587a3cabb27SUwe Koziolek static const struct ata_port_info sis_info133 = { 5881d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 589669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 590669a5db4SJeff Garzik .udma_mask = ATA_UDMA6, 591669a5db4SJeff Garzik .port_ops = &sis_133_ops, 592669a5db4SJeff Garzik }; 593a3cabb27SUwe Koziolek const struct ata_port_info sis_info133_for_sata = { 594a3cabb27SUwe Koziolek .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 595a3cabb27SUwe Koziolek .pio_mask = 0x1f, /* pio0-4 */ 596a3cabb27SUwe Koziolek .udma_mask = ATA_UDMA6, 597a3cabb27SUwe Koziolek .port_ops = &sis_133_for_sata_ops, 598a3cabb27SUwe Koziolek }; 5991626aeb8STejun Heo static const struct ata_port_info sis_info133_early = { 6001d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 601669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 602669a5db4SJeff Garzik .udma_mask = ATA_UDMA6, 603669a5db4SJeff Garzik .port_ops = &sis_133_early_ops, 604669a5db4SJeff Garzik }; 605669a5db4SJeff Garzik 6069b14dec5SAlan /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 607a3cabb27SUwe Koziolek EXPORT_SYMBOL_GPL(sis_info133_for_sata); 608669a5db4SJeff Garzik 609669a5db4SJeff Garzik static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 610669a5db4SJeff Garzik { 611669a5db4SJeff Garzik u16 regw; 612669a5db4SJeff Garzik u8 reg; 613669a5db4SJeff Garzik 614669a5db4SJeff Garzik if (sis->info == &sis_info133) { 615669a5db4SJeff Garzik pci_read_config_word(pdev, 0x50, ®w); 616669a5db4SJeff Garzik if (regw & 0x08) 617669a5db4SJeff Garzik pci_write_config_word(pdev, 0x50, regw & ~0x08); 618669a5db4SJeff Garzik pci_read_config_word(pdev, 0x52, ®w); 619669a5db4SJeff Garzik if (regw & 0x08) 620669a5db4SJeff Garzik pci_write_config_word(pdev, 0x52, regw & ~0x08); 621669a5db4SJeff Garzik return; 622669a5db4SJeff Garzik } 623669a5db4SJeff Garzik 624669a5db4SJeff Garzik if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 625669a5db4SJeff Garzik /* Fix up latency */ 626669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 627669a5db4SJeff Garzik /* Set compatibility bit */ 628669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x49, ®); 629669a5db4SJeff Garzik if (!(reg & 0x01)) 630669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x49, reg | 0x01); 631669a5db4SJeff Garzik return; 632669a5db4SJeff Garzik } 633669a5db4SJeff Garzik 634669a5db4SJeff Garzik if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 635669a5db4SJeff Garzik /* Fix up latency */ 636669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 637669a5db4SJeff Garzik /* Set compatibility bit */ 638669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x52, ®); 639669a5db4SJeff Garzik if (!(reg & 0x04)) 640669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x52, reg | 0x04); 641669a5db4SJeff Garzik return; 642669a5db4SJeff Garzik } 643669a5db4SJeff Garzik 644669a5db4SJeff Garzik if (sis->info == &sis_info33) { 645669a5db4SJeff Garzik pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 646669a5db4SJeff Garzik if (( reg & 0x0F ) != 0x00) 647669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 648669a5db4SJeff Garzik /* Fall through to ATA16 fixup below */ 649669a5db4SJeff Garzik } 650669a5db4SJeff Garzik 651669a5db4SJeff Garzik if (sis->info == &sis_info || sis->info == &sis_info33) { 652669a5db4SJeff Garzik /* force per drive recovery and active timings 653669a5db4SJeff Garzik needed on ATA_33 and below chips */ 654669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x52, ®); 655669a5db4SJeff Garzik if (!(reg & 0x08)) 656669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x52, reg|0x08); 657669a5db4SJeff Garzik return; 658669a5db4SJeff Garzik } 659669a5db4SJeff Garzik 660669a5db4SJeff Garzik BUG(); 661669a5db4SJeff Garzik } 662669a5db4SJeff Garzik 663669a5db4SJeff Garzik /** 664669a5db4SJeff Garzik * sis_init_one - Register SiS ATA PCI device with kernel services 665669a5db4SJeff Garzik * @pdev: PCI device to register 666669a5db4SJeff Garzik * @ent: Entry in sis_pci_tbl matching with @pdev 667669a5db4SJeff Garzik * 668669a5db4SJeff Garzik * Called from kernel PCI layer. We probe for combined mode (sigh), 669669a5db4SJeff Garzik * and then hand over control to libata, for it to do the rest. 670669a5db4SJeff Garzik * 671669a5db4SJeff Garzik * LOCKING: 672669a5db4SJeff Garzik * Inherited from PCI layer (may sleep). 673669a5db4SJeff Garzik * 674669a5db4SJeff Garzik * RETURNS: 675669a5db4SJeff Garzik * Zero on success, or -ERRNO value. 676669a5db4SJeff Garzik */ 677669a5db4SJeff Garzik 678669a5db4SJeff Garzik static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 679669a5db4SJeff Garzik { 680669a5db4SJeff Garzik static int printed_version; 681887125e3STejun Heo const struct ata_port_info *ppi[] = { NULL, NULL }; 682669a5db4SJeff Garzik struct pci_dev *host = NULL; 683669a5db4SJeff Garzik struct sis_chipset *chipset = NULL; 684f3769e9dSAlan Cox struct sis_chipset *sets; 685f08048e9STejun Heo int rc; 686669a5db4SJeff Garzik 687669a5db4SJeff Garzik static struct sis_chipset sis_chipsets[] = { 688af323a2fSAlan Cox 689af323a2fSAlan Cox { 0x0968, &sis_info133 }, 690af323a2fSAlan Cox { 0x0966, &sis_info133 }, 691af323a2fSAlan Cox { 0x0965, &sis_info133 }, 692669a5db4SJeff Garzik { 0x0745, &sis_info100 }, 693669a5db4SJeff Garzik { 0x0735, &sis_info100 }, 694669a5db4SJeff Garzik { 0x0733, &sis_info100 }, 695669a5db4SJeff Garzik { 0x0635, &sis_info100 }, 696669a5db4SJeff Garzik { 0x0633, &sis_info100 }, 697669a5db4SJeff Garzik 698669a5db4SJeff Garzik { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 699669a5db4SJeff Garzik { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 700669a5db4SJeff Garzik 701669a5db4SJeff Garzik { 0x0640, &sis_info66 }, 702669a5db4SJeff Garzik { 0x0630, &sis_info66 }, 703669a5db4SJeff Garzik { 0x0620, &sis_info66 }, 704669a5db4SJeff Garzik { 0x0540, &sis_info66 }, 705669a5db4SJeff Garzik { 0x0530, &sis_info66 }, 706669a5db4SJeff Garzik 707669a5db4SJeff Garzik { 0x5600, &sis_info33 }, 708669a5db4SJeff Garzik { 0x5598, &sis_info33 }, 709669a5db4SJeff Garzik { 0x5597, &sis_info33 }, 710669a5db4SJeff Garzik { 0x5591, &sis_info33 }, 711669a5db4SJeff Garzik { 0x5582, &sis_info33 }, 712669a5db4SJeff Garzik { 0x5581, &sis_info33 }, 713669a5db4SJeff Garzik 714669a5db4SJeff Garzik { 0x5596, &sis_info }, 715669a5db4SJeff Garzik { 0x5571, &sis_info }, 716669a5db4SJeff Garzik { 0x5517, &sis_info }, 717669a5db4SJeff Garzik { 0x5511, &sis_info }, 718669a5db4SJeff Garzik 719669a5db4SJeff Garzik {0} 720669a5db4SJeff Garzik }; 721669a5db4SJeff Garzik static struct sis_chipset sis133_early = { 722669a5db4SJeff Garzik 0x0, &sis_info133_early 723669a5db4SJeff Garzik }; 724669a5db4SJeff Garzik static struct sis_chipset sis133 = { 725669a5db4SJeff Garzik 0x0, &sis_info133 726669a5db4SJeff Garzik }; 727669a5db4SJeff Garzik static struct sis_chipset sis100_early = { 728669a5db4SJeff Garzik 0x0, &sis_info100_early 729669a5db4SJeff Garzik }; 730669a5db4SJeff Garzik static struct sis_chipset sis100 = { 731669a5db4SJeff Garzik 0x0, &sis_info100 732669a5db4SJeff Garzik }; 733669a5db4SJeff Garzik 734669a5db4SJeff Garzik if (!printed_version++) 735669a5db4SJeff Garzik dev_printk(KERN_DEBUG, &pdev->dev, 736669a5db4SJeff Garzik "version " DRV_VERSION "\n"); 737669a5db4SJeff Garzik 738f08048e9STejun Heo rc = pcim_enable_device(pdev); 739f08048e9STejun Heo if (rc) 740f08048e9STejun Heo return rc; 741669a5db4SJeff Garzik 742f08048e9STejun Heo /* We have to find the bridge first */ 743f3769e9dSAlan Cox for (sets = &sis_chipsets[0]; sets->device; sets++) { 744f3769e9dSAlan Cox host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 745669a5db4SJeff Garzik if (host != NULL) { 746f3769e9dSAlan Cox chipset = sets; /* Match found */ 747f3769e9dSAlan Cox if (sets->device == 0x630) { /* SIS630 */ 74844c10138SAuke Kok if (host->revision >= 0x30) /* 630 ET */ 749669a5db4SJeff Garzik chipset = &sis100_early; 750669a5db4SJeff Garzik } 751669a5db4SJeff Garzik break; 752669a5db4SJeff Garzik } 753669a5db4SJeff Garzik } 754669a5db4SJeff Garzik 755669a5db4SJeff Garzik /* Look for concealed bridges */ 756f3769e9dSAlan Cox if (chipset == NULL) { 757669a5db4SJeff Garzik /* Second check */ 758669a5db4SJeff Garzik u32 idemisc; 759669a5db4SJeff Garzik u16 trueid; 760669a5db4SJeff Garzik 761669a5db4SJeff Garzik /* Disable ID masking and register remapping then 762669a5db4SJeff Garzik see what the real ID is */ 763669a5db4SJeff Garzik 764669a5db4SJeff Garzik pci_read_config_dword(pdev, 0x54, &idemisc); 765669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 766669a5db4SJeff Garzik pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 767669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc); 768669a5db4SJeff Garzik 769669a5db4SJeff Garzik switch(trueid) { 770669a5db4SJeff Garzik case 0x5518: /* SIS 962/963 */ 771669a5db4SJeff Garzik chipset = &sis133; 772669a5db4SJeff Garzik if ((idemisc & 0x40000000) == 0) { 773669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 774669a5db4SJeff Garzik printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); 775669a5db4SJeff Garzik } 776669a5db4SJeff Garzik break; 777669a5db4SJeff Garzik case 0x0180: /* SIS 965/965L */ 778669a5db4SJeff Garzik chipset = &sis133; 779669a5db4SJeff Garzik break; 780669a5db4SJeff Garzik case 0x1180: /* SIS 966/966L */ 781669a5db4SJeff Garzik chipset = &sis133; 782669a5db4SJeff Garzik break; 783669a5db4SJeff Garzik } 784669a5db4SJeff Garzik } 785669a5db4SJeff Garzik 786669a5db4SJeff Garzik /* Further check */ 787669a5db4SJeff Garzik if (chipset == NULL) { 788669a5db4SJeff Garzik struct pci_dev *lpc_bridge; 789669a5db4SJeff Garzik u16 trueid; 790669a5db4SJeff Garzik u8 prefctl; 791669a5db4SJeff Garzik u8 idecfg; 792669a5db4SJeff Garzik 793669a5db4SJeff Garzik /* Try the second unmasking technique */ 794669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x4a, &idecfg); 795669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 796669a5db4SJeff Garzik pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 797669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4a, idecfg); 798669a5db4SJeff Garzik 799669a5db4SJeff Garzik switch(trueid) { 800669a5db4SJeff Garzik case 0x5517: 801669a5db4SJeff Garzik lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 802669a5db4SJeff Garzik if (lpc_bridge == NULL) 803669a5db4SJeff Garzik break; 804669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x49, &prefctl); 805669a5db4SJeff Garzik pci_dev_put(lpc_bridge); 806669a5db4SJeff Garzik 80744c10138SAuke Kok if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { 808669a5db4SJeff Garzik chipset = &sis133_early; 809669a5db4SJeff Garzik break; 810669a5db4SJeff Garzik } 811669a5db4SJeff Garzik chipset = &sis100; 812669a5db4SJeff Garzik break; 813669a5db4SJeff Garzik } 814669a5db4SJeff Garzik } 815669a5db4SJeff Garzik pci_dev_put(host); 816669a5db4SJeff Garzik 817669a5db4SJeff Garzik /* No chipset info, no support */ 818669a5db4SJeff Garzik if (chipset == NULL) 819669a5db4SJeff Garzik return -ENODEV; 820669a5db4SJeff Garzik 821887125e3STejun Heo ppi[0] = chipset->info; 822669a5db4SJeff Garzik 823669a5db4SJeff Garzik sis_fixup(pdev, chipset); 824669a5db4SJeff Garzik 8259363c382STejun Heo return ata_pci_sff_init_one(pdev, ppi, &sis_sht, chipset); 826669a5db4SJeff Garzik } 827669a5db4SJeff Garzik 828669a5db4SJeff Garzik static const struct pci_device_id sis_pci_tbl[] = { 8292d2744fcSJeff Garzik { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 8302d2744fcSJeff Garzik { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 831a3cabb27SUwe Koziolek { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 8322d2744fcSJeff Garzik 833669a5db4SJeff Garzik { } 834669a5db4SJeff Garzik }; 835669a5db4SJeff Garzik 836669a5db4SJeff Garzik static struct pci_driver sis_pci_driver = { 837669a5db4SJeff Garzik .name = DRV_NAME, 838669a5db4SJeff Garzik .id_table = sis_pci_tbl, 839669a5db4SJeff Garzik .probe = sis_init_one, 840669a5db4SJeff Garzik .remove = ata_pci_remove_one, 841438ac6d5STejun Heo #ifdef CONFIG_PM 84262d64ae0SAlan .suspend = ata_pci_device_suspend, 84362d64ae0SAlan .resume = ata_pci_device_resume, 844438ac6d5STejun Heo #endif 845669a5db4SJeff Garzik }; 846669a5db4SJeff Garzik 847669a5db4SJeff Garzik static int __init sis_init(void) 848669a5db4SJeff Garzik { 849669a5db4SJeff Garzik return pci_register_driver(&sis_pci_driver); 850669a5db4SJeff Garzik } 851669a5db4SJeff Garzik 852669a5db4SJeff Garzik static void __exit sis_exit(void) 853669a5db4SJeff Garzik { 854669a5db4SJeff Garzik pci_unregister_driver(&sis_pci_driver); 855669a5db4SJeff Garzik } 856669a5db4SJeff Garzik 857669a5db4SJeff Garzik module_init(sis_init); 858669a5db4SJeff Garzik module_exit(sis_exit); 859669a5db4SJeff Garzik 860669a5db4SJeff Garzik MODULE_AUTHOR("Alan Cox"); 861669a5db4SJeff Garzik MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 862669a5db4SJeff Garzik MODULE_LICENSE("GPL"); 863669a5db4SJeff Garzik MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 864669a5db4SJeff Garzik MODULE_VERSION(DRV_VERSION); 865669a5db4SJeff Garzik 866