1669a5db4SJeff Garzik /* 2669a5db4SJeff Garzik * pata_sis.c - SiS ATA driver 3669a5db4SJeff Garzik * 4669a5db4SJeff Garzik * (C) 2005 Red Hat <alan@redhat.com> 54761c06cSBartlomiej Zolnierkiewicz * (C) 2007 Bartlomiej Zolnierkiewicz 6669a5db4SJeff Garzik * 7669a5db4SJeff Garzik * Based upon linux/drivers/ide/pci/sis5513.c 8669a5db4SJeff Garzik * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 9669a5db4SJeff Garzik * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 10669a5db4SJeff Garzik * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 11669a5db4SJeff Garzik * SiS Taiwan : for direct support and hardware. 12669a5db4SJeff Garzik * Daniela Engert : for initial ATA100 advices and numerous others. 13669a5db4SJeff Garzik * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 14669a5db4SJeff Garzik * for checking code correctness, providing patches. 15669a5db4SJeff Garzik * Original tests and design on the SiS620 chipset. 16669a5db4SJeff Garzik * ATA100 tests and design on the SiS735 chipset. 17669a5db4SJeff Garzik * ATA16/33 support from specs 18669a5db4SJeff Garzik * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 19669a5db4SJeff Garzik * 20669a5db4SJeff Garzik * 21669a5db4SJeff Garzik * TODO 22669a5db4SJeff Garzik * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 23669a5db4SJeff Garzik * More Testing 24669a5db4SJeff Garzik */ 25669a5db4SJeff Garzik 26669a5db4SJeff Garzik #include <linux/kernel.h> 27669a5db4SJeff Garzik #include <linux/module.h> 28669a5db4SJeff Garzik #include <linux/pci.h> 29669a5db4SJeff Garzik #include <linux/init.h> 30669a5db4SJeff Garzik #include <linux/blkdev.h> 31669a5db4SJeff Garzik #include <linux/delay.h> 32669a5db4SJeff Garzik #include <linux/device.h> 33669a5db4SJeff Garzik #include <scsi/scsi_host.h> 34669a5db4SJeff Garzik #include <linux/libata.h> 35669a5db4SJeff Garzik #include <linux/ata.h> 364bb64fb9SAlan #include "sis.h" 37669a5db4SJeff Garzik 38669a5db4SJeff Garzik #define DRV_NAME "pata_sis" 394761c06cSBartlomiej Zolnierkiewicz #define DRV_VERSION "0.5.2" 40669a5db4SJeff Garzik 41669a5db4SJeff Garzik struct sis_chipset { 42669a5db4SJeff Garzik u16 device; /* PCI host ID */ 431626aeb8STejun Heo const struct ata_port_info *info; /* Info block */ 44669a5db4SJeff Garzik /* Probably add family, cable detect type etc here to clean 45669a5db4SJeff Garzik up code later */ 46669a5db4SJeff Garzik }; 47669a5db4SJeff Garzik 487dcbc1f2SJakub W. Jozwicki J struct sis_laptop { 497dcbc1f2SJakub W. Jozwicki J u16 device; 507dcbc1f2SJakub W. Jozwicki J u16 subvendor; 517dcbc1f2SJakub W. Jozwicki J u16 subdevice; 527dcbc1f2SJakub W. Jozwicki J }; 537dcbc1f2SJakub W. Jozwicki J 547dcbc1f2SJakub W. Jozwicki J static const struct sis_laptop sis_laptop[] = { 557dcbc1f2SJakub W. Jozwicki J /* devid, subvendor, subdev */ 567dcbc1f2SJakub W. Jozwicki J { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 574f2d47cfSAlan Cox { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ 581f71d067SGabriel C { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ 597dcbc1f2SJakub W. Jozwicki J /* end marker */ 607dcbc1f2SJakub W. Jozwicki J { 0, } 617dcbc1f2SJakub W. Jozwicki J }; 627dcbc1f2SJakub W. Jozwicki J 637dcbc1f2SJakub W. Jozwicki J static int sis_short_ata40(struct pci_dev *dev) 647dcbc1f2SJakub W. Jozwicki J { 657dcbc1f2SJakub W. Jozwicki J const struct sis_laptop *lap = &sis_laptop[0]; 667dcbc1f2SJakub W. Jozwicki J 677dcbc1f2SJakub W. Jozwicki J while (lap->device) { 687dcbc1f2SJakub W. Jozwicki J if (lap->device == dev->device && 697dcbc1f2SJakub W. Jozwicki J lap->subvendor == dev->subsystem_vendor && 707dcbc1f2SJakub W. Jozwicki J lap->subdevice == dev->subsystem_device) 717dcbc1f2SJakub W. Jozwicki J return 1; 727dcbc1f2SJakub W. Jozwicki J lap++; 737dcbc1f2SJakub W. Jozwicki J } 747dcbc1f2SJakub W. Jozwicki J 757dcbc1f2SJakub W. Jozwicki J return 0; 767dcbc1f2SJakub W. Jozwicki J } 777dcbc1f2SJakub W. Jozwicki J 78669a5db4SJeff Garzik /** 79dd668d15SAlan Cox * sis_old_port_base - return PCI configuration base for dev 80669a5db4SJeff Garzik * @adev: device 81669a5db4SJeff Garzik * 82669a5db4SJeff Garzik * Returns the base of the PCI configuration registers for this port 83669a5db4SJeff Garzik * number. 84669a5db4SJeff Garzik */ 85669a5db4SJeff Garzik 86dd668d15SAlan Cox static int sis_old_port_base(struct ata_device *adev) 87669a5db4SJeff Garzik { 889af5c9c9STejun Heo return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); 89669a5db4SJeff Garzik } 90669a5db4SJeff Garzik 91669a5db4SJeff Garzik /** 922e413f51SAlan Cox * sis_133_cable_detect - check for 40/80 pin 93669a5db4SJeff Garzik * @ap: Port 94d4b2bab4STejun Heo * @deadline: deadline jiffies for the operation 95669a5db4SJeff Garzik * 96669a5db4SJeff Garzik * Perform cable detection for the later UDMA133 capable 97669a5db4SJeff Garzik * SiS chipset. 98669a5db4SJeff Garzik */ 99669a5db4SJeff Garzik 1002e413f51SAlan Cox static int sis_133_cable_detect(struct ata_port *ap) 1012e413f51SAlan Cox { 1022e413f51SAlan Cox struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1032e413f51SAlan Cox u16 tmp; 1042e413f51SAlan Cox 1052e413f51SAlan Cox /* The top bit of this register is the cable detect bit */ 1062e413f51SAlan Cox pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 1072e413f51SAlan Cox if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 1082e413f51SAlan Cox return ATA_CBL_PATA40; 1092e413f51SAlan Cox return ATA_CBL_PATA80; 1102e413f51SAlan Cox } 1112e413f51SAlan Cox 1122e413f51SAlan Cox /** 1132e413f51SAlan Cox * sis_66_cable_detect - check for 40/80 pin 1142e413f51SAlan Cox * @ap: Port 115d4b2bab4STejun Heo * @deadline: deadline jiffies for the operation 1162e413f51SAlan Cox * 1172e413f51SAlan Cox * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 1182e413f51SAlan Cox * SiS IDE controllers. 1192e413f51SAlan Cox */ 1202e413f51SAlan Cox 1212e413f51SAlan Cox static int sis_66_cable_detect(struct ata_port *ap) 1222e413f51SAlan Cox { 1232e413f51SAlan Cox struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1242e413f51SAlan Cox u8 tmp; 1252e413f51SAlan Cox 1262e413f51SAlan Cox /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 1272e413f51SAlan Cox pci_read_config_byte(pdev, 0x48, &tmp); 1282e413f51SAlan Cox tmp >>= ap->port_no; 1292e413f51SAlan Cox if ((tmp & 0x10) && !sis_short_ata40(pdev)) 1302e413f51SAlan Cox return ATA_CBL_PATA40; 1312e413f51SAlan Cox return ATA_CBL_PATA80; 1322e413f51SAlan Cox } 1332e413f51SAlan Cox 1342e413f51SAlan Cox 1352e413f51SAlan Cox /** 1362e413f51SAlan Cox * sis_pre_reset - probe begin 137cc0680a5STejun Heo * @link: ATA link 138d4b2bab4STejun Heo * @deadline: deadline jiffies for the operation 1392e413f51SAlan Cox * 1402e413f51SAlan Cox * Set up cable type and use generic probe init 1412e413f51SAlan Cox */ 1422e413f51SAlan Cox 143cc0680a5STejun Heo static int sis_pre_reset(struct ata_link *link, unsigned long deadline) 144669a5db4SJeff Garzik { 145669a5db4SJeff Garzik static const struct pci_bits sis_enable_bits[] = { 146669a5db4SJeff Garzik { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 147669a5db4SJeff Garzik { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 148669a5db4SJeff Garzik }; 149669a5db4SJeff Garzik 150cc0680a5STejun Heo struct ata_port *ap = link->ap; 151669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 152669a5db4SJeff Garzik 153c961922bSAlan Cox if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 154c961922bSAlan Cox return -ENOENT; 155d4b2bab4STejun Heo 15615ce0943SAlan Cox /* Clear the FIFO settings. We can't enable the FIFO until 15715ce0943SAlan Cox we know we are poking at a disk */ 15815ce0943SAlan Cox pci_write_config_byte(pdev, 0x4B, 0); 1599363c382STejun Heo return ata_sff_prereset(link, deadline); 160669a5db4SJeff Garzik } 161669a5db4SJeff Garzik 1622e413f51SAlan Cox 163669a5db4SJeff Garzik /** 164669a5db4SJeff Garzik * sis_set_fifo - Set RWP fifo bits for this device 165669a5db4SJeff Garzik * @ap: Port 166669a5db4SJeff Garzik * @adev: Device 167669a5db4SJeff Garzik * 168669a5db4SJeff Garzik * SIS chipsets implement prefetch/postwrite bits for each device 169669a5db4SJeff Garzik * on both channels. This functionality is not ATAPI compatible and 170669a5db4SJeff Garzik * must be configured according to the class of device present 171669a5db4SJeff Garzik */ 172669a5db4SJeff Garzik 173669a5db4SJeff Garzik static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 174669a5db4SJeff Garzik { 175669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 176669a5db4SJeff Garzik u8 fifoctrl; 177669a5db4SJeff Garzik u8 mask = 0x11; 178669a5db4SJeff Garzik 179669a5db4SJeff Garzik mask <<= (2 * ap->port_no); 180669a5db4SJeff Garzik mask <<= adev->devno; 181669a5db4SJeff Garzik 182669a5db4SJeff Garzik /* This holds various bits including the FIFO control */ 183669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x4B, &fifoctrl); 184669a5db4SJeff Garzik fifoctrl &= ~mask; 185669a5db4SJeff Garzik 186669a5db4SJeff Garzik /* Enable for ATA (disk) only */ 187669a5db4SJeff Garzik if (adev->class == ATA_DEV_ATA) 188669a5db4SJeff Garzik fifoctrl |= mask; 189669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4B, fifoctrl); 190669a5db4SJeff Garzik } 191669a5db4SJeff Garzik 192669a5db4SJeff Garzik /** 193669a5db4SJeff Garzik * sis_old_set_piomode - Initialize host controller PATA PIO timings 194669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 195669a5db4SJeff Garzik * @adev: Device we are configuring for. 196669a5db4SJeff Garzik * 197669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 198669a5db4SJeff Garzik * function handles PIO set up for all chips that are pre ATA100 and 199669a5db4SJeff Garzik * also early ATA100 devices. 200669a5db4SJeff Garzik * 201669a5db4SJeff Garzik * LOCKING: 202669a5db4SJeff Garzik * None (inherited from caller). 203669a5db4SJeff Garzik */ 204669a5db4SJeff Garzik 205669a5db4SJeff Garzik static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 206669a5db4SJeff Garzik { 207669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 208dd668d15SAlan Cox int port = sis_old_port_base(adev); 209669a5db4SJeff Garzik u8 t1, t2; 210669a5db4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 211669a5db4SJeff Garzik 212669a5db4SJeff Garzik const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 213669a5db4SJeff Garzik const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 214669a5db4SJeff Garzik 215669a5db4SJeff Garzik sis_set_fifo(ap, adev); 216669a5db4SJeff Garzik 217669a5db4SJeff Garzik pci_read_config_byte(pdev, port, &t1); 218669a5db4SJeff Garzik pci_read_config_byte(pdev, port + 1, &t2); 219669a5db4SJeff Garzik 220669a5db4SJeff Garzik t1 &= ~0x0F; /* Clear active/recovery timings */ 221669a5db4SJeff Garzik t2 &= ~0x07; 222669a5db4SJeff Garzik 223669a5db4SJeff Garzik t1 |= active[speed]; 224669a5db4SJeff Garzik t2 |= recovery[speed]; 225669a5db4SJeff Garzik 226669a5db4SJeff Garzik pci_write_config_byte(pdev, port, t1); 227669a5db4SJeff Garzik pci_write_config_byte(pdev, port + 1, t2); 228669a5db4SJeff Garzik } 229669a5db4SJeff Garzik 230669a5db4SJeff Garzik /** 2314761c06cSBartlomiej Zolnierkiewicz * sis_100_set_piomode - Initialize host controller PATA PIO timings 232669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 233669a5db4SJeff Garzik * @adev: Device we are configuring for. 234669a5db4SJeff Garzik * 235669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 236669a5db4SJeff Garzik * function handles PIO set up for ATA100 devices and early ATA133. 237669a5db4SJeff Garzik * 238669a5db4SJeff Garzik * LOCKING: 239669a5db4SJeff Garzik * None (inherited from caller). 240669a5db4SJeff Garzik */ 241669a5db4SJeff Garzik 242669a5db4SJeff Garzik static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 243669a5db4SJeff Garzik { 244669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 245dd668d15SAlan Cox int port = sis_old_port_base(adev); 246669a5db4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 247669a5db4SJeff Garzik 248669a5db4SJeff Garzik const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 249669a5db4SJeff Garzik 250669a5db4SJeff Garzik sis_set_fifo(ap, adev); 251669a5db4SJeff Garzik 252669a5db4SJeff Garzik pci_write_config_byte(pdev, port, actrec[speed]); 253669a5db4SJeff Garzik } 254669a5db4SJeff Garzik 255669a5db4SJeff Garzik /** 2564761c06cSBartlomiej Zolnierkiewicz * sis_133_set_piomode - Initialize host controller PATA PIO timings 257669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 258669a5db4SJeff Garzik * @adev: Device we are configuring for. 259669a5db4SJeff Garzik * 260669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 261669a5db4SJeff Garzik * function handles PIO set up for the later ATA133 devices. 262669a5db4SJeff Garzik * 263669a5db4SJeff Garzik * LOCKING: 264669a5db4SJeff Garzik * None (inherited from caller). 265669a5db4SJeff Garzik */ 266669a5db4SJeff Garzik 267669a5db4SJeff Garzik static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 268669a5db4SJeff Garzik { 269669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 270669a5db4SJeff Garzik int port = 0x40; 271669a5db4SJeff Garzik u32 t1; 272669a5db4SJeff Garzik u32 reg54; 273669a5db4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 274669a5db4SJeff Garzik 275669a5db4SJeff Garzik const u32 timing133[] = { 276669a5db4SJeff Garzik 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 277669a5db4SJeff Garzik 0x0C266000, 278669a5db4SJeff Garzik 0x04263000, 279669a5db4SJeff Garzik 0x0C0A3000, 280669a5db4SJeff Garzik 0x05093000 281669a5db4SJeff Garzik }; 282669a5db4SJeff Garzik const u32 timing100[] = { 283669a5db4SJeff Garzik 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 284669a5db4SJeff Garzik 0x091C4000, 285669a5db4SJeff Garzik 0x031C2000, 286669a5db4SJeff Garzik 0x09072000, 287669a5db4SJeff Garzik 0x04062000 288669a5db4SJeff Garzik }; 289669a5db4SJeff Garzik 290669a5db4SJeff Garzik sis_set_fifo(ap, adev); 291669a5db4SJeff Garzik 292669a5db4SJeff Garzik /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 293669a5db4SJeff Garzik pci_read_config_dword(pdev, 0x54, ®54); 294669a5db4SJeff Garzik if (reg54 & 0x40000000) 295669a5db4SJeff Garzik port = 0x70; 296669a5db4SJeff Garzik port += 8 * ap->port_no + 4 * adev->devno; 297669a5db4SJeff Garzik 298669a5db4SJeff Garzik pci_read_config_dword(pdev, port, &t1); 299669a5db4SJeff Garzik t1 &= 0xC0C00FFF; /* Mask out timing */ 300669a5db4SJeff Garzik 301669a5db4SJeff Garzik if (t1 & 0x08) /* 100 or 133 ? */ 302669a5db4SJeff Garzik t1 |= timing133[speed]; 303669a5db4SJeff Garzik else 304669a5db4SJeff Garzik t1 |= timing100[speed]; 305669a5db4SJeff Garzik pci_write_config_byte(pdev, port, t1); 306669a5db4SJeff Garzik } 307669a5db4SJeff Garzik 308669a5db4SJeff Garzik /** 309669a5db4SJeff Garzik * sis_old_set_dmamode - Initialize host controller PATA DMA timings 310669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 311669a5db4SJeff Garzik * @adev: Device to program 312669a5db4SJeff Garzik * 313669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 314669a5db4SJeff Garzik * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 315669a5db4SJeff Garzik * the old ide/pci driver. 316669a5db4SJeff Garzik * 317669a5db4SJeff Garzik * LOCKING: 318669a5db4SJeff Garzik * None (inherited from caller). 319669a5db4SJeff Garzik */ 320669a5db4SJeff Garzik 321669a5db4SJeff Garzik static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 322669a5db4SJeff Garzik { 323669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 324669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 325dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 326669a5db4SJeff Garzik u16 timing; 327669a5db4SJeff Garzik 3284761c06cSBartlomiej Zolnierkiewicz const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 329669a5db4SJeff Garzik const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 330669a5db4SJeff Garzik 331669a5db4SJeff Garzik pci_read_config_word(pdev, drive_pci, &timing); 332669a5db4SJeff Garzik 333669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 334669a5db4SJeff Garzik /* bits 3-0 hold recovery timing bits 8-10 active timing and 3351967b7ffSJoe Perches the higher bits are dependant on the device */ 336669a5db4SJeff Garzik timing &= ~0x870F; 337669a5db4SJeff Garzik timing |= mwdma_bits[speed]; 338669a5db4SJeff Garzik } else { 339669a5db4SJeff Garzik /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 340669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 341669a5db4SJeff Garzik timing &= ~0x6000; 342669a5db4SJeff Garzik timing |= udma_bits[speed]; 343669a5db4SJeff Garzik } 3444761c06cSBartlomiej Zolnierkiewicz pci_write_config_word(pdev, drive_pci, timing); 345669a5db4SJeff Garzik } 346669a5db4SJeff Garzik 347669a5db4SJeff Garzik /** 348669a5db4SJeff Garzik * sis_66_set_dmamode - Initialize host controller PATA DMA timings 349669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 350669a5db4SJeff Garzik * @adev: Device to program 351669a5db4SJeff Garzik * 352669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 353669a5db4SJeff Garzik * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 354669a5db4SJeff Garzik * the old ide/pci driver. 355669a5db4SJeff Garzik * 356669a5db4SJeff Garzik * LOCKING: 357669a5db4SJeff Garzik * None (inherited from caller). 358669a5db4SJeff Garzik */ 359669a5db4SJeff Garzik 360669a5db4SJeff Garzik static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 361669a5db4SJeff Garzik { 362669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 363669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 364dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 365669a5db4SJeff Garzik u16 timing; 366669a5db4SJeff Garzik 367edeb614cSTejun Heo /* MWDMA 0-2 and UDMA 0-5 */ 3684761c06cSBartlomiej Zolnierkiewicz const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 369edeb614cSTejun Heo const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; 370669a5db4SJeff Garzik 371669a5db4SJeff Garzik pci_read_config_word(pdev, drive_pci, &timing); 372669a5db4SJeff Garzik 373669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 374669a5db4SJeff Garzik /* bits 3-0 hold recovery timing bits 8-10 active timing and 3751967b7ffSJoe Perches the higher bits are dependant on the device, bit 15 udma */ 376669a5db4SJeff Garzik timing &= ~0x870F; 377669a5db4SJeff Garzik timing |= mwdma_bits[speed]; 378669a5db4SJeff Garzik } else { 379669a5db4SJeff Garzik /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 380669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 381dd668d15SAlan Cox timing &= ~0xF000; 382669a5db4SJeff Garzik timing |= udma_bits[speed]; 383669a5db4SJeff Garzik } 384669a5db4SJeff Garzik pci_write_config_word(pdev, drive_pci, timing); 385669a5db4SJeff Garzik } 386669a5db4SJeff Garzik 387669a5db4SJeff Garzik /** 388669a5db4SJeff Garzik * sis_100_set_dmamode - Initialize host controller PATA DMA timings 389669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 390669a5db4SJeff Garzik * @adev: Device to program 391669a5db4SJeff Garzik * 392669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 393669a5db4SJeff Garzik * Handles UDMA66 and early UDMA100 devices. 394669a5db4SJeff Garzik * 395669a5db4SJeff Garzik * LOCKING: 396669a5db4SJeff Garzik * None (inherited from caller). 397669a5db4SJeff Garzik */ 398669a5db4SJeff Garzik 399669a5db4SJeff Garzik static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 400669a5db4SJeff Garzik { 401669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 402669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 403dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 404dd668d15SAlan Cox u8 timing; 405669a5db4SJeff Garzik 406dd668d15SAlan Cox const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 407669a5db4SJeff Garzik 408dd668d15SAlan Cox pci_read_config_byte(pdev, drive_pci + 1, &timing); 409669a5db4SJeff Garzik 410669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 411669a5db4SJeff Garzik /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 412669a5db4SJeff Garzik } else { 413dd668d15SAlan Cox /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 414669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 415dd668d15SAlan Cox timing &= ~0x8F; 416669a5db4SJeff Garzik timing |= udma_bits[speed]; 417669a5db4SJeff Garzik } 418dd668d15SAlan Cox pci_write_config_byte(pdev, drive_pci + 1, timing); 419669a5db4SJeff Garzik } 420669a5db4SJeff Garzik 421669a5db4SJeff Garzik /** 422669a5db4SJeff Garzik * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 423669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 424669a5db4SJeff Garzik * @adev: Device to program 425669a5db4SJeff Garzik * 426669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 4274761c06cSBartlomiej Zolnierkiewicz * Handles early SiS 961 bridges. 428669a5db4SJeff Garzik * 429669a5db4SJeff Garzik * LOCKING: 430669a5db4SJeff Garzik * None (inherited from caller). 431669a5db4SJeff Garzik */ 432669a5db4SJeff Garzik 433669a5db4SJeff Garzik static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 434669a5db4SJeff Garzik { 435669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 436669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 437dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 438dd668d15SAlan Cox u8 timing; 439dd668d15SAlan Cox /* Low 4 bits are timing */ 440dd668d15SAlan Cox static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 441669a5db4SJeff Garzik 442dd668d15SAlan Cox pci_read_config_byte(pdev, drive_pci + 1, &timing); 443669a5db4SJeff Garzik 444669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 445669a5db4SJeff Garzik /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 446669a5db4SJeff Garzik } else { 447dd668d15SAlan Cox /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 448669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 449dd668d15SAlan Cox timing &= ~0x8F; 450669a5db4SJeff Garzik timing |= udma_bits[speed]; 451669a5db4SJeff Garzik } 452dd668d15SAlan Cox pci_write_config_byte(pdev, drive_pci + 1, timing); 453669a5db4SJeff Garzik } 454669a5db4SJeff Garzik 455669a5db4SJeff Garzik /** 456669a5db4SJeff Garzik * sis_133_set_dmamode - Initialize host controller PATA DMA timings 457669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 458669a5db4SJeff Garzik * @adev: Device to program 459669a5db4SJeff Garzik * 460669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 461669a5db4SJeff Garzik * 462669a5db4SJeff Garzik * LOCKING: 463669a5db4SJeff Garzik * None (inherited from caller). 464669a5db4SJeff Garzik */ 465669a5db4SJeff Garzik 466669a5db4SJeff Garzik static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 467669a5db4SJeff Garzik { 468669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 469669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 470669a5db4SJeff Garzik int port = 0x40; 471669a5db4SJeff Garzik u32 t1; 472669a5db4SJeff Garzik u32 reg54; 473669a5db4SJeff Garzik 474669a5db4SJeff Garzik /* bits 4- cycle time 8 - cvs time */ 4752e413f51SAlan Cox static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 4762e413f51SAlan Cox static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 477669a5db4SJeff Garzik 478669a5db4SJeff Garzik /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 479669a5db4SJeff Garzik pci_read_config_dword(pdev, 0x54, ®54); 480669a5db4SJeff Garzik if (reg54 & 0x40000000) 481669a5db4SJeff Garzik port = 0x70; 482669a5db4SJeff Garzik port += (8 * ap->port_no) + (4 * adev->devno); 483669a5db4SJeff Garzik 484669a5db4SJeff Garzik pci_read_config_dword(pdev, port, &t1); 485669a5db4SJeff Garzik 486669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 487669a5db4SJeff Garzik t1 &= ~0x00000004; 488669a5db4SJeff Garzik /* FIXME: need data sheet to add MWDMA here. Also lacking on 489669a5db4SJeff Garzik ide/pci driver */ 490669a5db4SJeff Garzik } else { 491669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 492669a5db4SJeff Garzik /* if & 8 no UDMA133 - need info for ... */ 493669a5db4SJeff Garzik t1 &= ~0x00000FF0; 494669a5db4SJeff Garzik t1 |= 0x00000004; 495669a5db4SJeff Garzik if (t1 & 0x08) 496669a5db4SJeff Garzik t1 |= timing_u133[speed]; 497669a5db4SJeff Garzik else 498669a5db4SJeff Garzik t1 |= timing_u100[speed]; 499669a5db4SJeff Garzik } 500669a5db4SJeff Garzik pci_write_config_dword(pdev, port, t1); 501669a5db4SJeff Garzik } 502669a5db4SJeff Garzik 503669a5db4SJeff Garzik static struct scsi_host_template sis_sht = { 50468d1d07bSTejun Heo ATA_BMDMA_SHT(DRV_NAME), 505669a5db4SJeff Garzik }; 506669a5db4SJeff Garzik 507029cfd6bSTejun Heo static struct ata_port_operations sis_133_for_sata_ops = { 508029cfd6bSTejun Heo .inherits = &ata_bmdma_port_ops, 509669a5db4SJeff Garzik .set_piomode = sis_133_set_piomode, 510669a5db4SJeff Garzik .set_dmamode = sis_133_set_dmamode, 511029cfd6bSTejun Heo .cable_detect = sis_133_cable_detect, 512029cfd6bSTejun Heo }; 513669a5db4SJeff Garzik 514029cfd6bSTejun Heo static struct ata_port_operations sis_base_ops = { 515029cfd6bSTejun Heo .inherits = &ata_bmdma_port_ops, 516a1efdabaSTejun Heo .prereset = sis_pre_reset, 517669a5db4SJeff Garzik }; 518669a5db4SJeff Garzik 519029cfd6bSTejun Heo static struct ata_port_operations sis_133_ops = { 520029cfd6bSTejun Heo .inherits = &sis_base_ops, 521a3cabb27SUwe Koziolek .set_piomode = sis_133_set_piomode, 522a3cabb27SUwe Koziolek .set_dmamode = sis_133_set_dmamode, 523a3cabb27SUwe Koziolek .cable_detect = sis_133_cable_detect, 524a3cabb27SUwe Koziolek }; 525a3cabb27SUwe Koziolek 526029cfd6bSTejun Heo static struct ata_port_operations sis_133_early_ops = { 527029cfd6bSTejun Heo .inherits = &sis_base_ops, 528669a5db4SJeff Garzik .set_piomode = sis_100_set_piomode, 529669a5db4SJeff Garzik .set_dmamode = sis_133_early_set_dmamode, 5302e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 531669a5db4SJeff Garzik }; 532669a5db4SJeff Garzik 533029cfd6bSTejun Heo static struct ata_port_operations sis_100_ops = { 534029cfd6bSTejun Heo .inherits = &sis_base_ops, 535669a5db4SJeff Garzik .set_piomode = sis_100_set_piomode, 536669a5db4SJeff Garzik .set_dmamode = sis_100_set_dmamode, 5372e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 538669a5db4SJeff Garzik }; 539669a5db4SJeff Garzik 540029cfd6bSTejun Heo static struct ata_port_operations sis_66_ops = { 541029cfd6bSTejun Heo .inherits = &sis_base_ops, 542669a5db4SJeff Garzik .set_piomode = sis_old_set_piomode, 543669a5db4SJeff Garzik .set_dmamode = sis_66_set_dmamode, 5442e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 545669a5db4SJeff Garzik }; 546669a5db4SJeff Garzik 547029cfd6bSTejun Heo static struct ata_port_operations sis_old_ops = { 548029cfd6bSTejun Heo .inherits = &sis_base_ops, 549669a5db4SJeff Garzik .set_piomode = sis_old_set_piomode, 550669a5db4SJeff Garzik .set_dmamode = sis_old_set_dmamode, 5512e413f51SAlan Cox .cable_detect = ata_cable_40wire, 552669a5db4SJeff Garzik }; 553669a5db4SJeff Garzik 5541626aeb8STejun Heo static const struct ata_port_info sis_info = { 5551d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 556669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 557669a5db4SJeff Garzik .mwdma_mask = 0x07, 558669a5db4SJeff Garzik .udma_mask = 0, 559669a5db4SJeff Garzik .port_ops = &sis_old_ops, 560669a5db4SJeff Garzik }; 5611626aeb8STejun Heo static const struct ata_port_info sis_info33 = { 5621d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 563669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 564669a5db4SJeff Garzik .mwdma_mask = 0x07, 565669a5db4SJeff Garzik .udma_mask = ATA_UDMA2, /* UDMA 33 */ 566669a5db4SJeff Garzik .port_ops = &sis_old_ops, 567669a5db4SJeff Garzik }; 5681626aeb8STejun Heo static const struct ata_port_info sis_info66 = { 5691d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 570669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 571669a5db4SJeff Garzik .udma_mask = ATA_UDMA4, /* UDMA 66 */ 572669a5db4SJeff Garzik .port_ops = &sis_66_ops, 573669a5db4SJeff Garzik }; 5741626aeb8STejun Heo static const struct ata_port_info sis_info100 = { 5751d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 576669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 577669a5db4SJeff Garzik .udma_mask = ATA_UDMA5, 578669a5db4SJeff Garzik .port_ops = &sis_100_ops, 579669a5db4SJeff Garzik }; 5801626aeb8STejun Heo static const struct ata_port_info sis_info100_early = { 5811d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 582669a5db4SJeff Garzik .udma_mask = ATA_UDMA5, 583669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 584669a5db4SJeff Garzik .port_ops = &sis_66_ops, 585669a5db4SJeff Garzik }; 586a3cabb27SUwe Koziolek static const struct ata_port_info sis_info133 = { 5871d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 588669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 589669a5db4SJeff Garzik .udma_mask = ATA_UDMA6, 590669a5db4SJeff Garzik .port_ops = &sis_133_ops, 591669a5db4SJeff Garzik }; 592a3cabb27SUwe Koziolek const struct ata_port_info sis_info133_for_sata = { 593a3cabb27SUwe Koziolek .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 594a3cabb27SUwe Koziolek .pio_mask = 0x1f, /* pio0-4 */ 595a3cabb27SUwe Koziolek .udma_mask = ATA_UDMA6, 596a3cabb27SUwe Koziolek .port_ops = &sis_133_for_sata_ops, 597a3cabb27SUwe Koziolek }; 5981626aeb8STejun Heo static const struct ata_port_info sis_info133_early = { 5991d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 600669a5db4SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 601669a5db4SJeff Garzik .udma_mask = ATA_UDMA6, 602669a5db4SJeff Garzik .port_ops = &sis_133_early_ops, 603669a5db4SJeff Garzik }; 604669a5db4SJeff Garzik 6059b14dec5SAlan /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 606a3cabb27SUwe Koziolek EXPORT_SYMBOL_GPL(sis_info133_for_sata); 607669a5db4SJeff Garzik 608669a5db4SJeff Garzik static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 609669a5db4SJeff Garzik { 610669a5db4SJeff Garzik u16 regw; 611669a5db4SJeff Garzik u8 reg; 612669a5db4SJeff Garzik 613669a5db4SJeff Garzik if (sis->info == &sis_info133) { 614669a5db4SJeff Garzik pci_read_config_word(pdev, 0x50, ®w); 615669a5db4SJeff Garzik if (regw & 0x08) 616669a5db4SJeff Garzik pci_write_config_word(pdev, 0x50, regw & ~0x08); 617669a5db4SJeff Garzik pci_read_config_word(pdev, 0x52, ®w); 618669a5db4SJeff Garzik if (regw & 0x08) 619669a5db4SJeff Garzik pci_write_config_word(pdev, 0x52, regw & ~0x08); 620669a5db4SJeff Garzik return; 621669a5db4SJeff Garzik } 622669a5db4SJeff Garzik 623669a5db4SJeff Garzik if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 624669a5db4SJeff Garzik /* Fix up latency */ 625669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 626669a5db4SJeff Garzik /* Set compatibility bit */ 627669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x49, ®); 628669a5db4SJeff Garzik if (!(reg & 0x01)) 629669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x49, reg | 0x01); 630669a5db4SJeff Garzik return; 631669a5db4SJeff Garzik } 632669a5db4SJeff Garzik 633669a5db4SJeff Garzik if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 634669a5db4SJeff Garzik /* Fix up latency */ 635669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 636669a5db4SJeff Garzik /* Set compatibility bit */ 637669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x52, ®); 638669a5db4SJeff Garzik if (!(reg & 0x04)) 639669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x52, reg | 0x04); 640669a5db4SJeff Garzik return; 641669a5db4SJeff Garzik } 642669a5db4SJeff Garzik 643669a5db4SJeff Garzik if (sis->info == &sis_info33) { 644669a5db4SJeff Garzik pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 645669a5db4SJeff Garzik if (( reg & 0x0F ) != 0x00) 646669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 647669a5db4SJeff Garzik /* Fall through to ATA16 fixup below */ 648669a5db4SJeff Garzik } 649669a5db4SJeff Garzik 650669a5db4SJeff Garzik if (sis->info == &sis_info || sis->info == &sis_info33) { 651669a5db4SJeff Garzik /* force per drive recovery and active timings 652669a5db4SJeff Garzik needed on ATA_33 and below chips */ 653669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x52, ®); 654669a5db4SJeff Garzik if (!(reg & 0x08)) 655669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x52, reg|0x08); 656669a5db4SJeff Garzik return; 657669a5db4SJeff Garzik } 658669a5db4SJeff Garzik 659669a5db4SJeff Garzik BUG(); 660669a5db4SJeff Garzik } 661669a5db4SJeff Garzik 662669a5db4SJeff Garzik /** 663669a5db4SJeff Garzik * sis_init_one - Register SiS ATA PCI device with kernel services 664669a5db4SJeff Garzik * @pdev: PCI device to register 665669a5db4SJeff Garzik * @ent: Entry in sis_pci_tbl matching with @pdev 666669a5db4SJeff Garzik * 667669a5db4SJeff Garzik * Called from kernel PCI layer. We probe for combined mode (sigh), 668669a5db4SJeff Garzik * and then hand over control to libata, for it to do the rest. 669669a5db4SJeff Garzik * 670669a5db4SJeff Garzik * LOCKING: 671669a5db4SJeff Garzik * Inherited from PCI layer (may sleep). 672669a5db4SJeff Garzik * 673669a5db4SJeff Garzik * RETURNS: 674669a5db4SJeff Garzik * Zero on success, or -ERRNO value. 675669a5db4SJeff Garzik */ 676669a5db4SJeff Garzik 677669a5db4SJeff Garzik static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 678669a5db4SJeff Garzik { 679669a5db4SJeff Garzik static int printed_version; 680887125e3STejun Heo const struct ata_port_info *ppi[] = { NULL, NULL }; 681669a5db4SJeff Garzik struct pci_dev *host = NULL; 682669a5db4SJeff Garzik struct sis_chipset *chipset = NULL; 683f3769e9dSAlan Cox struct sis_chipset *sets; 684f08048e9STejun Heo int rc; 685669a5db4SJeff Garzik 686669a5db4SJeff Garzik static struct sis_chipset sis_chipsets[] = { 687af323a2fSAlan Cox 688af323a2fSAlan Cox { 0x0968, &sis_info133 }, 689af323a2fSAlan Cox { 0x0966, &sis_info133 }, 690af323a2fSAlan Cox { 0x0965, &sis_info133 }, 691669a5db4SJeff Garzik { 0x0745, &sis_info100 }, 692669a5db4SJeff Garzik { 0x0735, &sis_info100 }, 693669a5db4SJeff Garzik { 0x0733, &sis_info100 }, 694669a5db4SJeff Garzik { 0x0635, &sis_info100 }, 695669a5db4SJeff Garzik { 0x0633, &sis_info100 }, 696669a5db4SJeff Garzik 697669a5db4SJeff Garzik { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 698669a5db4SJeff Garzik { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 699669a5db4SJeff Garzik 700669a5db4SJeff Garzik { 0x0640, &sis_info66 }, 701669a5db4SJeff Garzik { 0x0630, &sis_info66 }, 702669a5db4SJeff Garzik { 0x0620, &sis_info66 }, 703669a5db4SJeff Garzik { 0x0540, &sis_info66 }, 704669a5db4SJeff Garzik { 0x0530, &sis_info66 }, 705669a5db4SJeff Garzik 706669a5db4SJeff Garzik { 0x5600, &sis_info33 }, 707669a5db4SJeff Garzik { 0x5598, &sis_info33 }, 708669a5db4SJeff Garzik { 0x5597, &sis_info33 }, 709669a5db4SJeff Garzik { 0x5591, &sis_info33 }, 710669a5db4SJeff Garzik { 0x5582, &sis_info33 }, 711669a5db4SJeff Garzik { 0x5581, &sis_info33 }, 712669a5db4SJeff Garzik 713669a5db4SJeff Garzik { 0x5596, &sis_info }, 714669a5db4SJeff Garzik { 0x5571, &sis_info }, 715669a5db4SJeff Garzik { 0x5517, &sis_info }, 716669a5db4SJeff Garzik { 0x5511, &sis_info }, 717669a5db4SJeff Garzik 718669a5db4SJeff Garzik {0} 719669a5db4SJeff Garzik }; 720669a5db4SJeff Garzik static struct sis_chipset sis133_early = { 721669a5db4SJeff Garzik 0x0, &sis_info133_early 722669a5db4SJeff Garzik }; 723669a5db4SJeff Garzik static struct sis_chipset sis133 = { 724669a5db4SJeff Garzik 0x0, &sis_info133 725669a5db4SJeff Garzik }; 726669a5db4SJeff Garzik static struct sis_chipset sis100_early = { 727669a5db4SJeff Garzik 0x0, &sis_info100_early 728669a5db4SJeff Garzik }; 729669a5db4SJeff Garzik static struct sis_chipset sis100 = { 730669a5db4SJeff Garzik 0x0, &sis_info100 731669a5db4SJeff Garzik }; 732669a5db4SJeff Garzik 733669a5db4SJeff Garzik if (!printed_version++) 734669a5db4SJeff Garzik dev_printk(KERN_DEBUG, &pdev->dev, 735669a5db4SJeff Garzik "version " DRV_VERSION "\n"); 736669a5db4SJeff Garzik 737f08048e9STejun Heo rc = pcim_enable_device(pdev); 738f08048e9STejun Heo if (rc) 739f08048e9STejun Heo return rc; 740669a5db4SJeff Garzik 741f08048e9STejun Heo /* We have to find the bridge first */ 742f3769e9dSAlan Cox for (sets = &sis_chipsets[0]; sets->device; sets++) { 743f3769e9dSAlan Cox host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 744669a5db4SJeff Garzik if (host != NULL) { 745f3769e9dSAlan Cox chipset = sets; /* Match found */ 746f3769e9dSAlan Cox if (sets->device == 0x630) { /* SIS630 */ 74744c10138SAuke Kok if (host->revision >= 0x30) /* 630 ET */ 748669a5db4SJeff Garzik chipset = &sis100_early; 749669a5db4SJeff Garzik } 750669a5db4SJeff Garzik break; 751669a5db4SJeff Garzik } 752669a5db4SJeff Garzik } 753669a5db4SJeff Garzik 754669a5db4SJeff Garzik /* Look for concealed bridges */ 755f3769e9dSAlan Cox if (chipset == NULL) { 756669a5db4SJeff Garzik /* Second check */ 757669a5db4SJeff Garzik u32 idemisc; 758669a5db4SJeff Garzik u16 trueid; 759669a5db4SJeff Garzik 760669a5db4SJeff Garzik /* Disable ID masking and register remapping then 761669a5db4SJeff Garzik see what the real ID is */ 762669a5db4SJeff Garzik 763669a5db4SJeff Garzik pci_read_config_dword(pdev, 0x54, &idemisc); 764669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 765669a5db4SJeff Garzik pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 766669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc); 767669a5db4SJeff Garzik 768669a5db4SJeff Garzik switch(trueid) { 769669a5db4SJeff Garzik case 0x5518: /* SIS 962/963 */ 770669a5db4SJeff Garzik chipset = &sis133; 771669a5db4SJeff Garzik if ((idemisc & 0x40000000) == 0) { 772669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 773669a5db4SJeff Garzik printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); 774669a5db4SJeff Garzik } 775669a5db4SJeff Garzik break; 776669a5db4SJeff Garzik case 0x0180: /* SIS 965/965L */ 777669a5db4SJeff Garzik chipset = &sis133; 778669a5db4SJeff Garzik break; 779669a5db4SJeff Garzik case 0x1180: /* SIS 966/966L */ 780669a5db4SJeff Garzik chipset = &sis133; 781669a5db4SJeff Garzik break; 782669a5db4SJeff Garzik } 783669a5db4SJeff Garzik } 784669a5db4SJeff Garzik 785669a5db4SJeff Garzik /* Further check */ 786669a5db4SJeff Garzik if (chipset == NULL) { 787669a5db4SJeff Garzik struct pci_dev *lpc_bridge; 788669a5db4SJeff Garzik u16 trueid; 789669a5db4SJeff Garzik u8 prefctl; 790669a5db4SJeff Garzik u8 idecfg; 791669a5db4SJeff Garzik 792669a5db4SJeff Garzik /* Try the second unmasking technique */ 793669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x4a, &idecfg); 794669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 795669a5db4SJeff Garzik pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 796669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4a, idecfg); 797669a5db4SJeff Garzik 798669a5db4SJeff Garzik switch(trueid) { 799669a5db4SJeff Garzik case 0x5517: 800669a5db4SJeff Garzik lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 801669a5db4SJeff Garzik if (lpc_bridge == NULL) 802669a5db4SJeff Garzik break; 803669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x49, &prefctl); 804669a5db4SJeff Garzik pci_dev_put(lpc_bridge); 805669a5db4SJeff Garzik 80644c10138SAuke Kok if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { 807669a5db4SJeff Garzik chipset = &sis133_early; 808669a5db4SJeff Garzik break; 809669a5db4SJeff Garzik } 810669a5db4SJeff Garzik chipset = &sis100; 811669a5db4SJeff Garzik break; 812669a5db4SJeff Garzik } 813669a5db4SJeff Garzik } 814669a5db4SJeff Garzik pci_dev_put(host); 815669a5db4SJeff Garzik 816669a5db4SJeff Garzik /* No chipset info, no support */ 817669a5db4SJeff Garzik if (chipset == NULL) 818669a5db4SJeff Garzik return -ENODEV; 819669a5db4SJeff Garzik 820887125e3STejun Heo ppi[0] = chipset->info; 821669a5db4SJeff Garzik 822669a5db4SJeff Garzik sis_fixup(pdev, chipset); 823669a5db4SJeff Garzik 8249363c382STejun Heo return ata_pci_sff_init_one(pdev, ppi, &sis_sht, chipset); 825669a5db4SJeff Garzik } 826669a5db4SJeff Garzik 827669a5db4SJeff Garzik static const struct pci_device_id sis_pci_tbl[] = { 8282d2744fcSJeff Garzik { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 8292d2744fcSJeff Garzik { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 830a3cabb27SUwe Koziolek { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 8312d2744fcSJeff Garzik 832669a5db4SJeff Garzik { } 833669a5db4SJeff Garzik }; 834669a5db4SJeff Garzik 835669a5db4SJeff Garzik static struct pci_driver sis_pci_driver = { 836669a5db4SJeff Garzik .name = DRV_NAME, 837669a5db4SJeff Garzik .id_table = sis_pci_tbl, 838669a5db4SJeff Garzik .probe = sis_init_one, 839669a5db4SJeff Garzik .remove = ata_pci_remove_one, 840438ac6d5STejun Heo #ifdef CONFIG_PM 84162d64ae0SAlan .suspend = ata_pci_device_suspend, 84262d64ae0SAlan .resume = ata_pci_device_resume, 843438ac6d5STejun Heo #endif 844669a5db4SJeff Garzik }; 845669a5db4SJeff Garzik 846669a5db4SJeff Garzik static int __init sis_init(void) 847669a5db4SJeff Garzik { 848669a5db4SJeff Garzik return pci_register_driver(&sis_pci_driver); 849669a5db4SJeff Garzik } 850669a5db4SJeff Garzik 851669a5db4SJeff Garzik static void __exit sis_exit(void) 852669a5db4SJeff Garzik { 853669a5db4SJeff Garzik pci_unregister_driver(&sis_pci_driver); 854669a5db4SJeff Garzik } 855669a5db4SJeff Garzik 856669a5db4SJeff Garzik module_init(sis_init); 857669a5db4SJeff Garzik module_exit(sis_exit); 858669a5db4SJeff Garzik 859669a5db4SJeff Garzik MODULE_AUTHOR("Alan Cox"); 860669a5db4SJeff Garzik MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 861669a5db4SJeff Garzik MODULE_LICENSE("GPL"); 862669a5db4SJeff Garzik MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 863669a5db4SJeff Garzik MODULE_VERSION(DRV_VERSION); 864669a5db4SJeff Garzik 865