109c434b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2669a5db4SJeff Garzik /* 3669a5db4SJeff Garzik * pata_sis.c - SiS ATA driver 4669a5db4SJeff Garzik * 5ab771630SAlan Cox * (C) 2005 Red Hat 6750c7136SBartlomiej Zolnierkiewicz * (C) 2007,2009 Bartlomiej Zolnierkiewicz 7669a5db4SJeff Garzik * 8669a5db4SJeff Garzik * Based upon linux/drivers/ide/pci/sis5513.c 9669a5db4SJeff Garzik * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 10669a5db4SJeff Garzik * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 11669a5db4SJeff Garzik * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 12669a5db4SJeff Garzik * SiS Taiwan : for direct support and hardware. 13669a5db4SJeff Garzik * Daniela Engert : for initial ATA100 advices and numerous others. 14669a5db4SJeff Garzik * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 15669a5db4SJeff Garzik * for checking code correctness, providing patches. 16669a5db4SJeff Garzik * Original tests and design on the SiS620 chipset. 17669a5db4SJeff Garzik * ATA100 tests and design on the SiS735 chipset. 18669a5db4SJeff Garzik * ATA16/33 support from specs 19669a5db4SJeff Garzik * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 20669a5db4SJeff Garzik * 21669a5db4SJeff Garzik * 22669a5db4SJeff Garzik * TODO 23669a5db4SJeff Garzik * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 24669a5db4SJeff Garzik * More Testing 25669a5db4SJeff Garzik */ 26669a5db4SJeff Garzik 27669a5db4SJeff Garzik #include <linux/kernel.h> 28669a5db4SJeff Garzik #include <linux/module.h> 29669a5db4SJeff Garzik #include <linux/pci.h> 30669a5db4SJeff Garzik #include <linux/blkdev.h> 31669a5db4SJeff Garzik #include <linux/delay.h> 32669a5db4SJeff Garzik #include <linux/device.h> 33669a5db4SJeff Garzik #include <scsi/scsi_host.h> 34669a5db4SJeff Garzik #include <linux/libata.h> 35669a5db4SJeff Garzik #include <linux/ata.h> 364bb64fb9SAlan #include "sis.h" 37669a5db4SJeff Garzik 38669a5db4SJeff Garzik #define DRV_NAME "pata_sis" 394761c06cSBartlomiej Zolnierkiewicz #define DRV_VERSION "0.5.2" 40669a5db4SJeff Garzik 41669a5db4SJeff Garzik struct sis_chipset { 42669a5db4SJeff Garzik u16 device; /* PCI host ID */ 431626aeb8STejun Heo const struct ata_port_info *info; /* Info block */ 44669a5db4SJeff Garzik /* Probably add family, cable detect type etc here to clean 45669a5db4SJeff Garzik up code later */ 46669a5db4SJeff Garzik }; 47669a5db4SJeff Garzik 487dcbc1f2SJakub W. Jozwicki J struct sis_laptop { 497dcbc1f2SJakub W. Jozwicki J u16 device; 507dcbc1f2SJakub W. Jozwicki J u16 subvendor; 517dcbc1f2SJakub W. Jozwicki J u16 subdevice; 527dcbc1f2SJakub W. Jozwicki J }; 537dcbc1f2SJakub W. Jozwicki J 547dcbc1f2SJakub W. Jozwicki J static const struct sis_laptop sis_laptop[] = { 557dcbc1f2SJakub W. Jozwicki J /* devid, subvendor, subdev */ 567dcbc1f2SJakub W. Jozwicki J { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 574f2d47cfSAlan Cox { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ 581f71d067SGabriel C { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ 597dcbc1f2SJakub W. Jozwicki J /* end marker */ 607dcbc1f2SJakub W. Jozwicki J { 0, } 617dcbc1f2SJakub W. Jozwicki J }; 627dcbc1f2SJakub W. Jozwicki J 637dcbc1f2SJakub W. Jozwicki J static int sis_short_ata40(struct pci_dev *dev) 647dcbc1f2SJakub W. Jozwicki J { 657dcbc1f2SJakub W. Jozwicki J const struct sis_laptop *lap = &sis_laptop[0]; 667dcbc1f2SJakub W. Jozwicki J 677dcbc1f2SJakub W. Jozwicki J while (lap->device) { 687dcbc1f2SJakub W. Jozwicki J if (lap->device == dev->device && 697dcbc1f2SJakub W. Jozwicki J lap->subvendor == dev->subsystem_vendor && 707dcbc1f2SJakub W. Jozwicki J lap->subdevice == dev->subsystem_device) 717dcbc1f2SJakub W. Jozwicki J return 1; 727dcbc1f2SJakub W. Jozwicki J lap++; 737dcbc1f2SJakub W. Jozwicki J } 747dcbc1f2SJakub W. Jozwicki J 757dcbc1f2SJakub W. Jozwicki J return 0; 767dcbc1f2SJakub W. Jozwicki J } 777dcbc1f2SJakub W. Jozwicki J 78669a5db4SJeff Garzik /** 79dd668d15SAlan Cox * sis_old_port_base - return PCI configuration base for dev 80669a5db4SJeff Garzik * @adev: device 81669a5db4SJeff Garzik * 82669a5db4SJeff Garzik * Returns the base of the PCI configuration registers for this port 83669a5db4SJeff Garzik * number. 84669a5db4SJeff Garzik */ 85669a5db4SJeff Garzik 86dd668d15SAlan Cox static int sis_old_port_base(struct ata_device *adev) 87669a5db4SJeff Garzik { 889af5c9c9STejun Heo return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); 89669a5db4SJeff Garzik } 90669a5db4SJeff Garzik 91669a5db4SJeff Garzik /** 92023a0175SDan McGee * sis_port_base - return PCI configuration base for dev 93023a0175SDan McGee * @adev: device 94023a0175SDan McGee * 95023a0175SDan McGee * Returns the base of the PCI configuration registers for this port 96023a0175SDan McGee * number. 97023a0175SDan McGee */ 98023a0175SDan McGee 99023a0175SDan McGee static int sis_port_base(struct ata_device *adev) 100023a0175SDan McGee { 101023a0175SDan McGee struct ata_port *ap = adev->link->ap; 102023a0175SDan McGee struct pci_dev *pdev = to_pci_dev(ap->host->dev); 103023a0175SDan McGee int port = 0x40; 104023a0175SDan McGee u32 reg54; 105023a0175SDan McGee 106023a0175SDan McGee /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */ 107023a0175SDan McGee pci_read_config_dword(pdev, 0x54, ®54); 108023a0175SDan McGee if (reg54 & 0x40000000) 109023a0175SDan McGee port = 0x70; 110023a0175SDan McGee 111023a0175SDan McGee return port + (8 * ap->port_no) + (4 * adev->devno); 112023a0175SDan McGee } 113023a0175SDan McGee 114023a0175SDan McGee /** 1152e413f51SAlan Cox * sis_133_cable_detect - check for 40/80 pin 116669a5db4SJeff Garzik * @ap: Port 117669a5db4SJeff Garzik * 118669a5db4SJeff Garzik * Perform cable detection for the later UDMA133 capable 119669a5db4SJeff Garzik * SiS chipset. 120669a5db4SJeff Garzik */ 121669a5db4SJeff Garzik 1222e413f51SAlan Cox static int sis_133_cable_detect(struct ata_port *ap) 1232e413f51SAlan Cox { 1242e413f51SAlan Cox struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1252e413f51SAlan Cox u16 tmp; 1262e413f51SAlan Cox 1272e413f51SAlan Cox /* The top bit of this register is the cable detect bit */ 1282e413f51SAlan Cox pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 1292e413f51SAlan Cox if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 1302e413f51SAlan Cox return ATA_CBL_PATA40; 1312e413f51SAlan Cox return ATA_CBL_PATA80; 1322e413f51SAlan Cox } 1332e413f51SAlan Cox 1342e413f51SAlan Cox /** 1352e413f51SAlan Cox * sis_66_cable_detect - check for 40/80 pin 1362e413f51SAlan Cox * @ap: Port 1372e413f51SAlan Cox * 1382e413f51SAlan Cox * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 1392e413f51SAlan Cox * SiS IDE controllers. 1402e413f51SAlan Cox */ 1412e413f51SAlan Cox 1422e413f51SAlan Cox static int sis_66_cable_detect(struct ata_port *ap) 1432e413f51SAlan Cox { 1442e413f51SAlan Cox struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1452e413f51SAlan Cox u8 tmp; 1462e413f51SAlan Cox 1472e413f51SAlan Cox /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 1482e413f51SAlan Cox pci_read_config_byte(pdev, 0x48, &tmp); 1492e413f51SAlan Cox tmp >>= ap->port_no; 1502e413f51SAlan Cox if ((tmp & 0x10) && !sis_short_ata40(pdev)) 1512e413f51SAlan Cox return ATA_CBL_PATA40; 1522e413f51SAlan Cox return ATA_CBL_PATA80; 1532e413f51SAlan Cox } 1542e413f51SAlan Cox 1552e413f51SAlan Cox 1562e413f51SAlan Cox /** 1572e413f51SAlan Cox * sis_pre_reset - probe begin 158cc0680a5STejun Heo * @link: ATA link 159d4b2bab4STejun Heo * @deadline: deadline jiffies for the operation 1602e413f51SAlan Cox * 1612e413f51SAlan Cox * Set up cable type and use generic probe init 1622e413f51SAlan Cox */ 1632e413f51SAlan Cox 164cc0680a5STejun Heo static int sis_pre_reset(struct ata_link *link, unsigned long deadline) 165669a5db4SJeff Garzik { 166669a5db4SJeff Garzik static const struct pci_bits sis_enable_bits[] = { 167669a5db4SJeff Garzik { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 168669a5db4SJeff Garzik { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 169669a5db4SJeff Garzik }; 170669a5db4SJeff Garzik 171cc0680a5STejun Heo struct ata_port *ap = link->ap; 172669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 173669a5db4SJeff Garzik 174c961922bSAlan Cox if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 175c961922bSAlan Cox return -ENOENT; 176d4b2bab4STejun Heo 17715ce0943SAlan Cox /* Clear the FIFO settings. We can't enable the FIFO until 17815ce0943SAlan Cox we know we are poking at a disk */ 17915ce0943SAlan Cox pci_write_config_byte(pdev, 0x4B, 0); 1809363c382STejun Heo return ata_sff_prereset(link, deadline); 181669a5db4SJeff Garzik } 182669a5db4SJeff Garzik 1832e413f51SAlan Cox 184669a5db4SJeff Garzik /** 185669a5db4SJeff Garzik * sis_set_fifo - Set RWP fifo bits for this device 186669a5db4SJeff Garzik * @ap: Port 187669a5db4SJeff Garzik * @adev: Device 188669a5db4SJeff Garzik * 189669a5db4SJeff Garzik * SIS chipsets implement prefetch/postwrite bits for each device 190669a5db4SJeff Garzik * on both channels. This functionality is not ATAPI compatible and 191669a5db4SJeff Garzik * must be configured according to the class of device present 192669a5db4SJeff Garzik */ 193669a5db4SJeff Garzik 194669a5db4SJeff Garzik static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 195669a5db4SJeff Garzik { 196669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 197669a5db4SJeff Garzik u8 fifoctrl; 198669a5db4SJeff Garzik u8 mask = 0x11; 199669a5db4SJeff Garzik 200669a5db4SJeff Garzik mask <<= (2 * ap->port_no); 201669a5db4SJeff Garzik mask <<= adev->devno; 202669a5db4SJeff Garzik 203669a5db4SJeff Garzik /* This holds various bits including the FIFO control */ 204669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x4B, &fifoctrl); 205669a5db4SJeff Garzik fifoctrl &= ~mask; 206669a5db4SJeff Garzik 207669a5db4SJeff Garzik /* Enable for ATA (disk) only */ 208669a5db4SJeff Garzik if (adev->class == ATA_DEV_ATA) 209669a5db4SJeff Garzik fifoctrl |= mask; 210669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4B, fifoctrl); 211669a5db4SJeff Garzik } 212669a5db4SJeff Garzik 213669a5db4SJeff Garzik /** 214669a5db4SJeff Garzik * sis_old_set_piomode - Initialize host controller PATA PIO timings 215669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 216669a5db4SJeff Garzik * @adev: Device we are configuring for. 217669a5db4SJeff Garzik * 218669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 219669a5db4SJeff Garzik * function handles PIO set up for all chips that are pre ATA100 and 220669a5db4SJeff Garzik * also early ATA100 devices. 221669a5db4SJeff Garzik * 222669a5db4SJeff Garzik * LOCKING: 223669a5db4SJeff Garzik * None (inherited from caller). 224669a5db4SJeff Garzik */ 225669a5db4SJeff Garzik 226669a5db4SJeff Garzik static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 227669a5db4SJeff Garzik { 228669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 229dd668d15SAlan Cox int port = sis_old_port_base(adev); 230669a5db4SJeff Garzik u8 t1, t2; 231669a5db4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 232669a5db4SJeff Garzik 233c03a476dSDan McGee static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 234c03a476dSDan McGee static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 235669a5db4SJeff Garzik 236669a5db4SJeff Garzik sis_set_fifo(ap, adev); 237669a5db4SJeff Garzik 238669a5db4SJeff Garzik pci_read_config_byte(pdev, port, &t1); 239669a5db4SJeff Garzik pci_read_config_byte(pdev, port + 1, &t2); 240669a5db4SJeff Garzik 241669a5db4SJeff Garzik t1 &= ~0x0F; /* Clear active/recovery timings */ 242669a5db4SJeff Garzik t2 &= ~0x07; 243669a5db4SJeff Garzik 244669a5db4SJeff Garzik t1 |= active[speed]; 245669a5db4SJeff Garzik t2 |= recovery[speed]; 246669a5db4SJeff Garzik 247669a5db4SJeff Garzik pci_write_config_byte(pdev, port, t1); 248669a5db4SJeff Garzik pci_write_config_byte(pdev, port + 1, t2); 249669a5db4SJeff Garzik } 250669a5db4SJeff Garzik 251669a5db4SJeff Garzik /** 2524761c06cSBartlomiej Zolnierkiewicz * sis_100_set_piomode - Initialize host controller PATA PIO timings 253669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 254669a5db4SJeff Garzik * @adev: Device we are configuring for. 255669a5db4SJeff Garzik * 256669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 257669a5db4SJeff Garzik * function handles PIO set up for ATA100 devices and early ATA133. 258669a5db4SJeff Garzik * 259669a5db4SJeff Garzik * LOCKING: 260669a5db4SJeff Garzik * None (inherited from caller). 261669a5db4SJeff Garzik */ 262669a5db4SJeff Garzik 263669a5db4SJeff Garzik static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 264669a5db4SJeff Garzik { 265669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 266dd668d15SAlan Cox int port = sis_old_port_base(adev); 267669a5db4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 268669a5db4SJeff Garzik 269c03a476dSDan McGee static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 270669a5db4SJeff Garzik 271669a5db4SJeff Garzik sis_set_fifo(ap, adev); 272669a5db4SJeff Garzik 273669a5db4SJeff Garzik pci_write_config_byte(pdev, port, actrec[speed]); 274669a5db4SJeff Garzik } 275669a5db4SJeff Garzik 276669a5db4SJeff Garzik /** 2771b52f2a4SJeff Garzik * sis_133_set_piomode - Initialize host controller PATA PIO timings 278669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 279669a5db4SJeff Garzik * @adev: Device we are configuring for. 280669a5db4SJeff Garzik * 281669a5db4SJeff Garzik * Set PIO mode for device, in host controller PCI config space. This 2821b52f2a4SJeff Garzik * function handles PIO set up for the later ATA133 devices. 283669a5db4SJeff Garzik * 284669a5db4SJeff Garzik * LOCKING: 285669a5db4SJeff Garzik * None (inherited from caller). 286669a5db4SJeff Garzik */ 287669a5db4SJeff Garzik 2881b52f2a4SJeff Garzik static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 289669a5db4SJeff Garzik { 290669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 291023a0175SDan McGee int port; 292669a5db4SJeff Garzik u32 t1; 2931b52f2a4SJeff Garzik int speed = adev->pio_mode - XFER_PIO_0; 294669a5db4SJeff Garzik 295c03a476dSDan McGee static const u32 timing133[] = { 296669a5db4SJeff Garzik 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 297669a5db4SJeff Garzik 0x0C266000, 298669a5db4SJeff Garzik 0x04263000, 299669a5db4SJeff Garzik 0x0C0A3000, 300669a5db4SJeff Garzik 0x05093000 301669a5db4SJeff Garzik }; 302c03a476dSDan McGee static const u32 timing100[] = { 303669a5db4SJeff Garzik 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 304669a5db4SJeff Garzik 0x091C4000, 305669a5db4SJeff Garzik 0x031C2000, 306669a5db4SJeff Garzik 0x09072000, 307669a5db4SJeff Garzik 0x04062000 308669a5db4SJeff Garzik }; 309669a5db4SJeff Garzik 310669a5db4SJeff Garzik sis_set_fifo(ap, adev); 311669a5db4SJeff Garzik 312023a0175SDan McGee port = sis_port_base(adev); 313669a5db4SJeff Garzik pci_read_config_dword(pdev, port, &t1); 314669a5db4SJeff Garzik t1 &= 0xC0C00FFF; /* Mask out timing */ 315669a5db4SJeff Garzik 316669a5db4SJeff Garzik if (t1 & 0x08) /* 100 or 133 ? */ 317669a5db4SJeff Garzik t1 |= timing133[speed]; 318669a5db4SJeff Garzik else 319669a5db4SJeff Garzik t1 |= timing100[speed]; 320669a5db4SJeff Garzik pci_write_config_byte(pdev, port, t1); 321669a5db4SJeff Garzik } 322669a5db4SJeff Garzik 323669a5db4SJeff Garzik /** 324669a5db4SJeff Garzik * sis_old_set_dmamode - Initialize host controller PATA DMA timings 325669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 326669a5db4SJeff Garzik * @adev: Device to program 327669a5db4SJeff Garzik * 328669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 329669a5db4SJeff Garzik * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 330669a5db4SJeff Garzik * the old ide/pci driver. 331669a5db4SJeff Garzik * 332669a5db4SJeff Garzik * LOCKING: 333669a5db4SJeff Garzik * None (inherited from caller). 334669a5db4SJeff Garzik */ 335669a5db4SJeff Garzik 336669a5db4SJeff Garzik static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 337669a5db4SJeff Garzik { 338669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 339669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 340dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 341669a5db4SJeff Garzik u16 timing; 342669a5db4SJeff Garzik 343c03a476dSDan McGee static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 344c03a476dSDan McGee static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 345669a5db4SJeff Garzik 346669a5db4SJeff Garzik pci_read_config_word(pdev, drive_pci, &timing); 347669a5db4SJeff Garzik 348669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 349669a5db4SJeff Garzik /* bits 3-0 hold recovery timing bits 8-10 active timing and 35025985edcSLucas De Marchi the higher bits are dependent on the device */ 351669a5db4SJeff Garzik timing &= ~0x870F; 352669a5db4SJeff Garzik timing |= mwdma_bits[speed]; 353669a5db4SJeff Garzik } else { 354669a5db4SJeff Garzik /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 355669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 356669a5db4SJeff Garzik timing &= ~0x6000; 357669a5db4SJeff Garzik timing |= udma_bits[speed]; 358669a5db4SJeff Garzik } 3594761c06cSBartlomiej Zolnierkiewicz pci_write_config_word(pdev, drive_pci, timing); 360669a5db4SJeff Garzik } 361669a5db4SJeff Garzik 362669a5db4SJeff Garzik /** 363669a5db4SJeff Garzik * sis_66_set_dmamode - Initialize host controller PATA DMA timings 364669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 365669a5db4SJeff Garzik * @adev: Device to program 366669a5db4SJeff Garzik * 367669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 368669a5db4SJeff Garzik * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 369669a5db4SJeff Garzik * the old ide/pci driver. 370669a5db4SJeff Garzik * 371669a5db4SJeff Garzik * LOCKING: 372669a5db4SJeff Garzik * None (inherited from caller). 373669a5db4SJeff Garzik */ 374669a5db4SJeff Garzik 375669a5db4SJeff Garzik static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 376669a5db4SJeff Garzik { 377669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 378669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 379dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 380669a5db4SJeff Garzik u16 timing; 381669a5db4SJeff Garzik 382edeb614cSTejun Heo /* MWDMA 0-2 and UDMA 0-5 */ 383c03a476dSDan McGee static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 384c03a476dSDan McGee static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; 385669a5db4SJeff Garzik 386669a5db4SJeff Garzik pci_read_config_word(pdev, drive_pci, &timing); 387669a5db4SJeff Garzik 388669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 389669a5db4SJeff Garzik /* bits 3-0 hold recovery timing bits 8-10 active timing and 39025985edcSLucas De Marchi the higher bits are dependent on the device, bit 15 udma */ 391669a5db4SJeff Garzik timing &= ~0x870F; 392669a5db4SJeff Garzik timing |= mwdma_bits[speed]; 393669a5db4SJeff Garzik } else { 394669a5db4SJeff Garzik /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 395669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 396dd668d15SAlan Cox timing &= ~0xF000; 397669a5db4SJeff Garzik timing |= udma_bits[speed]; 398669a5db4SJeff Garzik } 399669a5db4SJeff Garzik pci_write_config_word(pdev, drive_pci, timing); 400669a5db4SJeff Garzik } 401669a5db4SJeff Garzik 402669a5db4SJeff Garzik /** 403669a5db4SJeff Garzik * sis_100_set_dmamode - Initialize host controller PATA DMA timings 404669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 405669a5db4SJeff Garzik * @adev: Device to program 406669a5db4SJeff Garzik * 407669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 4081b52f2a4SJeff Garzik * Handles UDMA66 and early UDMA100 devices. 409669a5db4SJeff Garzik * 410669a5db4SJeff Garzik * LOCKING: 411669a5db4SJeff Garzik * None (inherited from caller). 412669a5db4SJeff Garzik */ 413669a5db4SJeff Garzik 414669a5db4SJeff Garzik static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 415669a5db4SJeff Garzik { 416669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 417669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 418dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 4191b52f2a4SJeff Garzik u8 timing; 420669a5db4SJeff Garzik 421c03a476dSDan McGee static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 422669a5db4SJeff Garzik 4231b52f2a4SJeff Garzik pci_read_config_byte(pdev, drive_pci + 1, &timing); 424669a5db4SJeff Garzik 425669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 4261b52f2a4SJeff Garzik /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 427669a5db4SJeff Garzik } else { 428dd668d15SAlan Cox /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 429669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 4301b52f2a4SJeff Garzik timing &= ~0x8F; 431669a5db4SJeff Garzik timing |= udma_bits[speed]; 432669a5db4SJeff Garzik } 4331b52f2a4SJeff Garzik pci_write_config_byte(pdev, drive_pci + 1, timing); 434669a5db4SJeff Garzik } 435669a5db4SJeff Garzik 436669a5db4SJeff Garzik /** 437669a5db4SJeff Garzik * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 438669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 439669a5db4SJeff Garzik * @adev: Device to program 440669a5db4SJeff Garzik * 441669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 4424761c06cSBartlomiej Zolnierkiewicz * Handles early SiS 961 bridges. 443669a5db4SJeff Garzik * 444669a5db4SJeff Garzik * LOCKING: 445669a5db4SJeff Garzik * None (inherited from caller). 446669a5db4SJeff Garzik */ 447669a5db4SJeff Garzik 448669a5db4SJeff Garzik static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 449669a5db4SJeff Garzik { 450669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 451669a5db4SJeff Garzik int speed = adev->dma_mode - XFER_MW_DMA_0; 452dd668d15SAlan Cox int drive_pci = sis_old_port_base(adev); 4531b52f2a4SJeff Garzik u8 timing; 4541b52f2a4SJeff Garzik /* Low 4 bits are timing */ 4551b52f2a4SJeff Garzik static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 456669a5db4SJeff Garzik 4571b52f2a4SJeff Garzik pci_read_config_byte(pdev, drive_pci + 1, &timing); 458669a5db4SJeff Garzik 459669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 4601b52f2a4SJeff Garzik /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 461669a5db4SJeff Garzik } else { 462dd668d15SAlan Cox /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 463669a5db4SJeff Garzik speed = adev->dma_mode - XFER_UDMA_0; 4641b52f2a4SJeff Garzik timing &= ~0x8F; 465669a5db4SJeff Garzik timing |= udma_bits[speed]; 466669a5db4SJeff Garzik } 4671b52f2a4SJeff Garzik pci_write_config_byte(pdev, drive_pci + 1, timing); 468669a5db4SJeff Garzik } 469669a5db4SJeff Garzik 470669a5db4SJeff Garzik /** 471669a5db4SJeff Garzik * sis_133_set_dmamode - Initialize host controller PATA DMA timings 472669a5db4SJeff Garzik * @ap: Port whose timings we are configuring 473669a5db4SJeff Garzik * @adev: Device to program 474669a5db4SJeff Garzik * 475669a5db4SJeff Garzik * Set UDMA/MWDMA mode for device, in host controller PCI config space. 476669a5db4SJeff Garzik * 477669a5db4SJeff Garzik * LOCKING: 478669a5db4SJeff Garzik * None (inherited from caller). 479669a5db4SJeff Garzik */ 480669a5db4SJeff Garzik 481669a5db4SJeff Garzik static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 482669a5db4SJeff Garzik { 483669a5db4SJeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 484023a0175SDan McGee int port; 485669a5db4SJeff Garzik u32 t1; 486669a5db4SJeff Garzik 487023a0175SDan McGee port = sis_port_base(adev); 488669a5db4SJeff Garzik pci_read_config_dword(pdev, port, &t1); 489669a5db4SJeff Garzik 490669a5db4SJeff Garzik if (adev->dma_mode < XFER_UDMA_0) { 49114004f04SDan McGee /* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */ 49214004f04SDan McGee static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 }; 49314004f04SDan McGee static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 }; 49414004f04SDan McGee int speed = adev->dma_mode - XFER_MW_DMA_0; 49514004f04SDan McGee 49614004f04SDan McGee t1 &= 0xC0C00FFF; 49714004f04SDan McGee /* disable UDMA */ 4981b52f2a4SJeff Garzik t1 &= ~0x00000004; 49914004f04SDan McGee if (t1 & 0x08) 50014004f04SDan McGee t1 |= timing_u133[speed]; 50114004f04SDan McGee else 50214004f04SDan McGee t1 |= timing_u100[speed]; 503669a5db4SJeff Garzik } else { 50414004f04SDan McGee /* bits 4- cycle time 8 - cvs time */ 50514004f04SDan McGee static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 50614004f04SDan McGee static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 507023a0175SDan McGee int speed = adev->dma_mode - XFER_UDMA_0; 50814004f04SDan McGee 509669a5db4SJeff Garzik t1 &= ~0x00000FF0; 51014004f04SDan McGee /* enable UDMA */ 511669a5db4SJeff Garzik t1 |= 0x00000004; 512669a5db4SJeff Garzik if (t1 & 0x08) 513669a5db4SJeff Garzik t1 |= timing_u133[speed]; 514669a5db4SJeff Garzik else 515669a5db4SJeff Garzik t1 |= timing_u100[speed]; 516669a5db4SJeff Garzik } 517669a5db4SJeff Garzik pci_write_config_dword(pdev, port, t1); 518669a5db4SJeff Garzik } 519669a5db4SJeff Garzik 520f30f9a5eSDan McGee /** 521f30f9a5eSDan McGee * sis_133_mode_filter - mode selection filter 522f30f9a5eSDan McGee * @adev: ATA device 523*8927c41eSLee Jones * @mask: received mask to manipulate and pass back 524f30f9a5eSDan McGee * 525f30f9a5eSDan McGee * Block UDMA6 on devices that do not support it. 526f30f9a5eSDan McGee */ 527f30f9a5eSDan McGee 528f30f9a5eSDan McGee static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask) 529f30f9a5eSDan McGee { 530f30f9a5eSDan McGee struct ata_port *ap = adev->link->ap; 531f30f9a5eSDan McGee struct pci_dev *pdev = to_pci_dev(ap->host->dev); 532f30f9a5eSDan McGee int port = sis_port_base(adev); 533f30f9a5eSDan McGee u32 t1; 534f30f9a5eSDan McGee 535f30f9a5eSDan McGee pci_read_config_dword(pdev, port, &t1); 536f30f9a5eSDan McGee /* if ATA133 is disabled, mask it out */ 537f30f9a5eSDan McGee if (!(t1 & 0x08)) 538f30f9a5eSDan McGee mask &= ~(0xC0 << ATA_SHIFT_UDMA); 539f30f9a5eSDan McGee return mask; 540f30f9a5eSDan McGee } 541f30f9a5eSDan McGee 542669a5db4SJeff Garzik static struct scsi_host_template sis_sht = { 54368d1d07bSTejun Heo ATA_BMDMA_SHT(DRV_NAME), 544669a5db4SJeff Garzik }; 545669a5db4SJeff Garzik 546029cfd6bSTejun Heo static struct ata_port_operations sis_133_for_sata_ops = { 547029cfd6bSTejun Heo .inherits = &ata_bmdma_port_ops, 548669a5db4SJeff Garzik .set_piomode = sis_133_set_piomode, 549669a5db4SJeff Garzik .set_dmamode = sis_133_set_dmamode, 550029cfd6bSTejun Heo .cable_detect = sis_133_cable_detect, 551029cfd6bSTejun Heo }; 552669a5db4SJeff Garzik 553029cfd6bSTejun Heo static struct ata_port_operations sis_base_ops = { 554029cfd6bSTejun Heo .inherits = &ata_bmdma_port_ops, 555a1efdabaSTejun Heo .prereset = sis_pre_reset, 556669a5db4SJeff Garzik }; 557669a5db4SJeff Garzik 558029cfd6bSTejun Heo static struct ata_port_operations sis_133_ops = { 559029cfd6bSTejun Heo .inherits = &sis_base_ops, 560a3cabb27SUwe Koziolek .set_piomode = sis_133_set_piomode, 561a3cabb27SUwe Koziolek .set_dmamode = sis_133_set_dmamode, 562a3cabb27SUwe Koziolek .cable_detect = sis_133_cable_detect, 563f30f9a5eSDan McGee .mode_filter = sis_133_mode_filter, 564a3cabb27SUwe Koziolek }; 565a3cabb27SUwe Koziolek 566029cfd6bSTejun Heo static struct ata_port_operations sis_133_early_ops = { 567029cfd6bSTejun Heo .inherits = &sis_base_ops, 568669a5db4SJeff Garzik .set_piomode = sis_100_set_piomode, 569669a5db4SJeff Garzik .set_dmamode = sis_133_early_set_dmamode, 5702e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 571669a5db4SJeff Garzik }; 572669a5db4SJeff Garzik 573029cfd6bSTejun Heo static struct ata_port_operations sis_100_ops = { 574029cfd6bSTejun Heo .inherits = &sis_base_ops, 575669a5db4SJeff Garzik .set_piomode = sis_100_set_piomode, 576669a5db4SJeff Garzik .set_dmamode = sis_100_set_dmamode, 5772e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 578669a5db4SJeff Garzik }; 579669a5db4SJeff Garzik 580029cfd6bSTejun Heo static struct ata_port_operations sis_66_ops = { 581029cfd6bSTejun Heo .inherits = &sis_base_ops, 582669a5db4SJeff Garzik .set_piomode = sis_old_set_piomode, 583669a5db4SJeff Garzik .set_dmamode = sis_66_set_dmamode, 5842e413f51SAlan Cox .cable_detect = sis_66_cable_detect, 585669a5db4SJeff Garzik }; 586669a5db4SJeff Garzik 587029cfd6bSTejun Heo static struct ata_port_operations sis_old_ops = { 588029cfd6bSTejun Heo .inherits = &sis_base_ops, 589669a5db4SJeff Garzik .set_piomode = sis_old_set_piomode, 590669a5db4SJeff Garzik .set_dmamode = sis_old_set_dmamode, 5912e413f51SAlan Cox .cable_detect = ata_cable_40wire, 592669a5db4SJeff Garzik }; 593669a5db4SJeff Garzik 5941626aeb8STejun Heo static const struct ata_port_info sis_info = { 5951d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 59614bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4, 59714bdef98SErik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 59814bdef98SErik Inge Bolsø /* No UDMA */ 599669a5db4SJeff Garzik .port_ops = &sis_old_ops, 600669a5db4SJeff Garzik }; 6011626aeb8STejun Heo static const struct ata_port_info sis_info33 = { 6021d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 60314bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4, 60414bdef98SErik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 60514bdef98SErik Inge Bolsø .udma_mask = ATA_UDMA2, 606669a5db4SJeff Garzik .port_ops = &sis_old_ops, 607669a5db4SJeff Garzik }; 6081626aeb8STejun Heo static const struct ata_port_info sis_info66 = { 6091d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 61014bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4, 61114bdef98SErik Inge Bolsø /* No MWDMA */ 61214bdef98SErik Inge Bolsø .udma_mask = ATA_UDMA4, 613669a5db4SJeff Garzik .port_ops = &sis_66_ops, 614669a5db4SJeff Garzik }; 6151626aeb8STejun Heo static const struct ata_port_info sis_info100 = { 6161d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 61714bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4, 61814bdef98SErik Inge Bolsø /* No MWDMA */ 619669a5db4SJeff Garzik .udma_mask = ATA_UDMA5, 620669a5db4SJeff Garzik .port_ops = &sis_100_ops, 621669a5db4SJeff Garzik }; 6221626aeb8STejun Heo static const struct ata_port_info sis_info100_early = { 6231d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 62414bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4, 62514bdef98SErik Inge Bolsø /* No MWDMA */ 626669a5db4SJeff Garzik .udma_mask = ATA_UDMA5, 627669a5db4SJeff Garzik .port_ops = &sis_66_ops, 628669a5db4SJeff Garzik }; 629a3cabb27SUwe Koziolek static const struct ata_port_info sis_info133 = { 6301d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 63114bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4, 63214004f04SDan McGee .mwdma_mask = ATA_MWDMA2, 633669a5db4SJeff Garzik .udma_mask = ATA_UDMA6, 634669a5db4SJeff Garzik .port_ops = &sis_133_ops, 635669a5db4SJeff Garzik }; 636a3cabb27SUwe Koziolek const struct ata_port_info sis_info133_for_sata = { 637c10f97b9SSergei Shtylyov .flags = ATA_FLAG_SLAVE_POSS, 63814bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4, 63914bdef98SErik Inge Bolsø /* No MWDMA */ 640a3cabb27SUwe Koziolek .udma_mask = ATA_UDMA6, 641a3cabb27SUwe Koziolek .port_ops = &sis_133_for_sata_ops, 642a3cabb27SUwe Koziolek }; 6431626aeb8STejun Heo static const struct ata_port_info sis_info133_early = { 6441d2808fdSJeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 64514bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4, 64614bdef98SErik Inge Bolsø /* No MWDMA */ 647669a5db4SJeff Garzik .udma_mask = ATA_UDMA6, 648669a5db4SJeff Garzik .port_ops = &sis_133_early_ops, 649669a5db4SJeff Garzik }; 650669a5db4SJeff Garzik 6519b14dec5SAlan /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 652a3cabb27SUwe Koziolek EXPORT_SYMBOL_GPL(sis_info133_for_sata); 653669a5db4SJeff Garzik 654669a5db4SJeff Garzik static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 655669a5db4SJeff Garzik { 656669a5db4SJeff Garzik u16 regw; 657669a5db4SJeff Garzik u8 reg; 658669a5db4SJeff Garzik 659669a5db4SJeff Garzik if (sis->info == &sis_info133) { 660669a5db4SJeff Garzik pci_read_config_word(pdev, 0x50, ®w); 661669a5db4SJeff Garzik if (regw & 0x08) 662669a5db4SJeff Garzik pci_write_config_word(pdev, 0x50, regw & ~0x08); 663669a5db4SJeff Garzik pci_read_config_word(pdev, 0x52, ®w); 664669a5db4SJeff Garzik if (regw & 0x08) 665669a5db4SJeff Garzik pci_write_config_word(pdev, 0x52, regw & ~0x08); 666669a5db4SJeff Garzik return; 667669a5db4SJeff Garzik } 668669a5db4SJeff Garzik 669669a5db4SJeff Garzik if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 670669a5db4SJeff Garzik /* Fix up latency */ 671669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 672669a5db4SJeff Garzik /* Set compatibility bit */ 673669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x49, ®); 674669a5db4SJeff Garzik if (!(reg & 0x01)) 675669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x49, reg | 0x01); 676669a5db4SJeff Garzik return; 677669a5db4SJeff Garzik } 678669a5db4SJeff Garzik 679669a5db4SJeff Garzik if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 680669a5db4SJeff Garzik /* Fix up latency */ 681669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 682669a5db4SJeff Garzik /* Set compatibility bit */ 683669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x52, ®); 684669a5db4SJeff Garzik if (!(reg & 0x04)) 685669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x52, reg | 0x04); 686669a5db4SJeff Garzik return; 687669a5db4SJeff Garzik } 688669a5db4SJeff Garzik 689669a5db4SJeff Garzik if (sis->info == &sis_info33) { 690669a5db4SJeff Garzik pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 691669a5db4SJeff Garzik if (( reg & 0x0F ) != 0x00) 692669a5db4SJeff Garzik pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 693669a5db4SJeff Garzik /* Fall through to ATA16 fixup below */ 694669a5db4SJeff Garzik } 695669a5db4SJeff Garzik 696669a5db4SJeff Garzik if (sis->info == &sis_info || sis->info == &sis_info33) { 697669a5db4SJeff Garzik /* force per drive recovery and active timings 698669a5db4SJeff Garzik needed on ATA_33 and below chips */ 699669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x52, ®); 700669a5db4SJeff Garzik if (!(reg & 0x08)) 701669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x52, reg|0x08); 702669a5db4SJeff Garzik return; 703669a5db4SJeff Garzik } 704669a5db4SJeff Garzik 705669a5db4SJeff Garzik BUG(); 706669a5db4SJeff Garzik } 707669a5db4SJeff Garzik 708669a5db4SJeff Garzik /** 709669a5db4SJeff Garzik * sis_init_one - Register SiS ATA PCI device with kernel services 710669a5db4SJeff Garzik * @pdev: PCI device to register 711669a5db4SJeff Garzik * @ent: Entry in sis_pci_tbl matching with @pdev 712669a5db4SJeff Garzik * 713669a5db4SJeff Garzik * Called from kernel PCI layer. We probe for combined mode (sigh), 714669a5db4SJeff Garzik * and then hand over control to libata, for it to do the rest. 715669a5db4SJeff Garzik * 716669a5db4SJeff Garzik * LOCKING: 717669a5db4SJeff Garzik * Inherited from PCI layer (may sleep). 718669a5db4SJeff Garzik * 719669a5db4SJeff Garzik * RETURNS: 720669a5db4SJeff Garzik * Zero on success, or -ERRNO value. 721669a5db4SJeff Garzik */ 722669a5db4SJeff Garzik 723669a5db4SJeff Garzik static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 724669a5db4SJeff Garzik { 725887125e3STejun Heo const struct ata_port_info *ppi[] = { NULL, NULL }; 726669a5db4SJeff Garzik struct pci_dev *host = NULL; 727669a5db4SJeff Garzik struct sis_chipset *chipset = NULL; 728f3769e9dSAlan Cox struct sis_chipset *sets; 729f08048e9STejun Heo int rc; 730669a5db4SJeff Garzik 731669a5db4SJeff Garzik static struct sis_chipset sis_chipsets[] = { 732af323a2fSAlan Cox 733af323a2fSAlan Cox { 0x0968, &sis_info133 }, 734af323a2fSAlan Cox { 0x0966, &sis_info133 }, 735af323a2fSAlan Cox { 0x0965, &sis_info133 }, 736669a5db4SJeff Garzik { 0x0745, &sis_info100 }, 737669a5db4SJeff Garzik { 0x0735, &sis_info100 }, 738669a5db4SJeff Garzik { 0x0733, &sis_info100 }, 739669a5db4SJeff Garzik { 0x0635, &sis_info100 }, 740669a5db4SJeff Garzik { 0x0633, &sis_info100 }, 741669a5db4SJeff Garzik 742669a5db4SJeff Garzik { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 743669a5db4SJeff Garzik { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 744669a5db4SJeff Garzik 745669a5db4SJeff Garzik { 0x0640, &sis_info66 }, 746669a5db4SJeff Garzik { 0x0630, &sis_info66 }, 747669a5db4SJeff Garzik { 0x0620, &sis_info66 }, 748669a5db4SJeff Garzik { 0x0540, &sis_info66 }, 749669a5db4SJeff Garzik { 0x0530, &sis_info66 }, 750669a5db4SJeff Garzik 751669a5db4SJeff Garzik { 0x5600, &sis_info33 }, 752669a5db4SJeff Garzik { 0x5598, &sis_info33 }, 753669a5db4SJeff Garzik { 0x5597, &sis_info33 }, 754669a5db4SJeff Garzik { 0x5591, &sis_info33 }, 755669a5db4SJeff Garzik { 0x5582, &sis_info33 }, 756669a5db4SJeff Garzik { 0x5581, &sis_info33 }, 757669a5db4SJeff Garzik 758669a5db4SJeff Garzik { 0x5596, &sis_info }, 759669a5db4SJeff Garzik { 0x5571, &sis_info }, 760669a5db4SJeff Garzik { 0x5517, &sis_info }, 761669a5db4SJeff Garzik { 0x5511, &sis_info }, 762669a5db4SJeff Garzik 763669a5db4SJeff Garzik {0} 764669a5db4SJeff Garzik }; 765669a5db4SJeff Garzik static struct sis_chipset sis133_early = { 766669a5db4SJeff Garzik 0x0, &sis_info133_early 767669a5db4SJeff Garzik }; 768669a5db4SJeff Garzik static struct sis_chipset sis133 = { 769669a5db4SJeff Garzik 0x0, &sis_info133 770669a5db4SJeff Garzik }; 771669a5db4SJeff Garzik static struct sis_chipset sis100_early = { 772669a5db4SJeff Garzik 0x0, &sis_info100_early 773669a5db4SJeff Garzik }; 774669a5db4SJeff Garzik static struct sis_chipset sis100 = { 775669a5db4SJeff Garzik 0x0, &sis_info100 776669a5db4SJeff Garzik }; 777669a5db4SJeff Garzik 77806296a1eSJoe Perches ata_print_version_once(&pdev->dev, DRV_VERSION); 779669a5db4SJeff Garzik 780f08048e9STejun Heo rc = pcim_enable_device(pdev); 781f08048e9STejun Heo if (rc) 782f08048e9STejun Heo return rc; 783669a5db4SJeff Garzik 784f08048e9STejun Heo /* We have to find the bridge first */ 785f3769e9dSAlan Cox for (sets = &sis_chipsets[0]; sets->device; sets++) { 786f3769e9dSAlan Cox host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 787669a5db4SJeff Garzik if (host != NULL) { 788f3769e9dSAlan Cox chipset = sets; /* Match found */ 789f3769e9dSAlan Cox if (sets->device == 0x630) { /* SIS630 */ 79044c10138SAuke Kok if (host->revision >= 0x30) /* 630 ET */ 791669a5db4SJeff Garzik chipset = &sis100_early; 792669a5db4SJeff Garzik } 793669a5db4SJeff Garzik break; 794669a5db4SJeff Garzik } 795669a5db4SJeff Garzik } 796669a5db4SJeff Garzik 797669a5db4SJeff Garzik /* Look for concealed bridges */ 798f3769e9dSAlan Cox if (chipset == NULL) { 799669a5db4SJeff Garzik /* Second check */ 800669a5db4SJeff Garzik u32 idemisc; 801669a5db4SJeff Garzik u16 trueid; 802669a5db4SJeff Garzik 803669a5db4SJeff Garzik /* Disable ID masking and register remapping then 804669a5db4SJeff Garzik see what the real ID is */ 805669a5db4SJeff Garzik 806669a5db4SJeff Garzik pci_read_config_dword(pdev, 0x54, &idemisc); 807669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 808669a5db4SJeff Garzik pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 809669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc); 810669a5db4SJeff Garzik 811669a5db4SJeff Garzik switch(trueid) { 812669a5db4SJeff Garzik case 0x5518: /* SIS 962/963 */ 813f30f9a5eSDan McGee dev_info(&pdev->dev, 814f30f9a5eSDan McGee "SiS 962/963 MuTIOL IDE UDMA133 controller\n"); 815669a5db4SJeff Garzik chipset = &sis133; 816669a5db4SJeff Garzik if ((idemisc & 0x40000000) == 0) { 817669a5db4SJeff Garzik pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 818f30f9a5eSDan McGee dev_info(&pdev->dev, 819f30f9a5eSDan McGee "Switching to 5513 register mapping\n"); 820669a5db4SJeff Garzik } 821669a5db4SJeff Garzik break; 822669a5db4SJeff Garzik case 0x0180: /* SIS 965/965L */ 823669a5db4SJeff Garzik chipset = &sis133; 824669a5db4SJeff Garzik break; 825669a5db4SJeff Garzik case 0x1180: /* SIS 966/966L */ 826669a5db4SJeff Garzik chipset = &sis133; 827669a5db4SJeff Garzik break; 828669a5db4SJeff Garzik } 829669a5db4SJeff Garzik } 830669a5db4SJeff Garzik 831669a5db4SJeff Garzik /* Further check */ 832669a5db4SJeff Garzik if (chipset == NULL) { 833669a5db4SJeff Garzik struct pci_dev *lpc_bridge; 834669a5db4SJeff Garzik u16 trueid; 835669a5db4SJeff Garzik u8 prefctl; 836669a5db4SJeff Garzik u8 idecfg; 837669a5db4SJeff Garzik 838669a5db4SJeff Garzik /* Try the second unmasking technique */ 839669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x4a, &idecfg); 840669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 841669a5db4SJeff Garzik pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 842669a5db4SJeff Garzik pci_write_config_byte(pdev, 0x4a, idecfg); 843669a5db4SJeff Garzik 844669a5db4SJeff Garzik switch(trueid) { 845669a5db4SJeff Garzik case 0x5517: 846669a5db4SJeff Garzik lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 847669a5db4SJeff Garzik if (lpc_bridge == NULL) 848669a5db4SJeff Garzik break; 849669a5db4SJeff Garzik pci_read_config_byte(pdev, 0x49, &prefctl); 850669a5db4SJeff Garzik pci_dev_put(lpc_bridge); 851669a5db4SJeff Garzik 85244c10138SAuke Kok if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { 853669a5db4SJeff Garzik chipset = &sis133_early; 854669a5db4SJeff Garzik break; 855669a5db4SJeff Garzik } 856669a5db4SJeff Garzik chipset = &sis100; 857669a5db4SJeff Garzik break; 858669a5db4SJeff Garzik } 859669a5db4SJeff Garzik } 860669a5db4SJeff Garzik pci_dev_put(host); 861669a5db4SJeff Garzik 862669a5db4SJeff Garzik /* No chipset info, no support */ 863669a5db4SJeff Garzik if (chipset == NULL) 864669a5db4SJeff Garzik return -ENODEV; 865669a5db4SJeff Garzik 866887125e3STejun Heo ppi[0] = chipset->info; 867669a5db4SJeff Garzik 868669a5db4SJeff Garzik sis_fixup(pdev, chipset); 869669a5db4SJeff Garzik 8701c5afdf7STejun Heo return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0); 871669a5db4SJeff Garzik } 872669a5db4SJeff Garzik 87358eb8cd5SBartlomiej Zolnierkiewicz #ifdef CONFIG_PM_SLEEP 874750c7136SBartlomiej Zolnierkiewicz static int sis_reinit_one(struct pci_dev *pdev) 875750c7136SBartlomiej Zolnierkiewicz { 8760a86e1c8SJingoo Han struct ata_host *host = pci_get_drvdata(pdev); 877750c7136SBartlomiej Zolnierkiewicz int rc; 878750c7136SBartlomiej Zolnierkiewicz 879750c7136SBartlomiej Zolnierkiewicz rc = ata_pci_device_do_resume(pdev); 880750c7136SBartlomiej Zolnierkiewicz if (rc) 881750c7136SBartlomiej Zolnierkiewicz return rc; 882750c7136SBartlomiej Zolnierkiewicz 883750c7136SBartlomiej Zolnierkiewicz sis_fixup(pdev, host->private_data); 884750c7136SBartlomiej Zolnierkiewicz 885750c7136SBartlomiej Zolnierkiewicz ata_host_resume(host); 886750c7136SBartlomiej Zolnierkiewicz return 0; 887750c7136SBartlomiej Zolnierkiewicz } 888750c7136SBartlomiej Zolnierkiewicz #endif 889750c7136SBartlomiej Zolnierkiewicz 890669a5db4SJeff Garzik static const struct pci_device_id sis_pci_tbl[] = { 8912d2744fcSJeff Garzik { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 8922d2744fcSJeff Garzik { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 893a3cabb27SUwe Koziolek { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 8942d2744fcSJeff Garzik 895669a5db4SJeff Garzik { } 896669a5db4SJeff Garzik }; 897669a5db4SJeff Garzik 898669a5db4SJeff Garzik static struct pci_driver sis_pci_driver = { 899669a5db4SJeff Garzik .name = DRV_NAME, 900669a5db4SJeff Garzik .id_table = sis_pci_tbl, 901669a5db4SJeff Garzik .probe = sis_init_one, 902669a5db4SJeff Garzik .remove = ata_pci_remove_one, 90358eb8cd5SBartlomiej Zolnierkiewicz #ifdef CONFIG_PM_SLEEP 90462d64ae0SAlan .suspend = ata_pci_device_suspend, 905750c7136SBartlomiej Zolnierkiewicz .resume = sis_reinit_one, 906438ac6d5STejun Heo #endif 907669a5db4SJeff Garzik }; 908669a5db4SJeff Garzik 9092fc75da0SAxel Lin module_pci_driver(sis_pci_driver); 910669a5db4SJeff Garzik 911669a5db4SJeff Garzik MODULE_AUTHOR("Alan Cox"); 912669a5db4SJeff Garzik MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 913669a5db4SJeff Garzik MODULE_LICENSE("GPL"); 914669a5db4SJeff Garzik MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 915669a5db4SJeff Garzik MODULE_VERSION(DRV_VERSION); 916