1 /* 2 * pata_sil680.c - SIL680 PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * 5 * based upon 6 * 7 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003 8 * 9 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 10 * Copyright (C) 2003 Red Hat <alan@redhat.com> 11 * 12 * May be copied or modified under the terms of the GNU General Public License 13 * 14 * Documentation publicly available. 15 * 16 * If you have strange problems with nVidia chipset systems please 17 * see the SI support documentation and update your system BIOS 18 * if necessary 19 * 20 * TODO 21 * If we know all our devices are LBA28 (or LBA28 sized) we could use 22 * the command fifo mode. 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include <linux/init.h> 29 #include <linux/blkdev.h> 30 #include <linux/delay.h> 31 #include <scsi/scsi_host.h> 32 #include <linux/libata.h> 33 34 #define DRV_NAME "pata_sil680" 35 #define DRV_VERSION "0.4.9" 36 37 #define SIL680_MMIO_BAR 5 38 39 /** 40 * sil680_selreg - return register base 41 * @hwif: interface 42 * @r: config offset 43 * 44 * Turn a config register offset into the right address in either 45 * PCI space or MMIO space to access the control register in question 46 * Thankfully this is a configuration operation so isn't performance 47 * criticial. 48 */ 49 50 static unsigned long sil680_selreg(struct ata_port *ap, int r) 51 { 52 unsigned long base = 0xA0 + r; 53 base += (ap->port_no << 4); 54 return base; 55 } 56 57 /** 58 * sil680_seldev - return register base 59 * @hwif: interface 60 * @r: config offset 61 * 62 * Turn a config register offset into the right address in either 63 * PCI space or MMIO space to access the control register in question 64 * including accounting for the unit shift. 65 */ 66 67 static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r) 68 { 69 unsigned long base = 0xA0 + r; 70 base += (ap->port_no << 4); 71 base |= adev->devno ? 2 : 0; 72 return base; 73 } 74 75 76 /** 77 * sil680_cable_detect - cable detection 78 * @ap: ATA port 79 * 80 * Perform cable detection. The SIL680 stores this in PCI config 81 * space for us. 82 */ 83 84 static int sil680_cable_detect(struct ata_port *ap) { 85 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 86 unsigned long addr = sil680_selreg(ap, 0); 87 u8 ata66; 88 pci_read_config_byte(pdev, addr, &ata66); 89 if (ata66 & 1) 90 return ATA_CBL_PATA80; 91 else 92 return ATA_CBL_PATA40; 93 } 94 95 /** 96 * sil680_set_piomode - set initial PIO mode data 97 * @ap: ATA interface 98 * @adev: ATA device 99 * 100 * Program the SIL680 registers for PIO mode. Note that the task speed 101 * registers are shared between the devices so we must pick the lowest 102 * mode for command work. 103 */ 104 105 static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev) 106 { 107 static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 }; 108 static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 }; 109 110 unsigned long tfaddr = sil680_selreg(ap, 0x02); 111 unsigned long addr = sil680_seldev(ap, adev, 0x04); 112 unsigned long addr_mask = 0x80 + 4 * ap->port_no; 113 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 114 int pio = adev->pio_mode - XFER_PIO_0; 115 int lowest_pio = pio; 116 int port_shift = 4 * adev->devno; 117 u16 reg; 118 u8 mode; 119 120 struct ata_device *pair = ata_dev_pair(adev); 121 122 if (pair != NULL && adev->pio_mode > pair->pio_mode) 123 lowest_pio = pair->pio_mode - XFER_PIO_0; 124 125 pci_write_config_word(pdev, addr, speed_p[pio]); 126 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]); 127 128 pci_read_config_word(pdev, tfaddr-2, ®); 129 pci_read_config_byte(pdev, addr_mask, &mode); 130 131 reg &= ~0x0200; /* Clear IORDY */ 132 mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */ 133 134 if (ata_pio_need_iordy(adev)) { 135 reg |= 0x0200; /* Enable IORDY */ 136 mode |= 1 << port_shift; 137 } 138 pci_write_config_word(pdev, tfaddr-2, reg); 139 pci_write_config_byte(pdev, addr_mask, mode); 140 } 141 142 /** 143 * sil680_set_dmamode - set initial DMA mode data 144 * @ap: ATA interface 145 * @adev: ATA device 146 * 147 * Program the MWDMA/UDMA modes for the sil680 k 148 * chipset. The MWDMA mode values are pulled from a lookup table 149 * while the chipset uses mode number for UDMA. 150 */ 151 152 static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev) 153 { 154 static u8 ultra_table[2][7] = { 155 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */ 156 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */ 157 }; 158 static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 }; 159 160 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 161 unsigned long ma = sil680_seldev(ap, adev, 0x08); 162 unsigned long ua = sil680_seldev(ap, adev, 0x0C); 163 unsigned long addr_mask = 0x80 + 4 * ap->port_no; 164 int port_shift = adev->devno * 4; 165 u8 scsc, mode; 166 u16 multi, ultra; 167 168 pci_read_config_byte(pdev, 0x8A, &scsc); 169 pci_read_config_byte(pdev, addr_mask, &mode); 170 pci_read_config_word(pdev, ma, &multi); 171 pci_read_config_word(pdev, ua, &ultra); 172 173 /* Mask timing bits */ 174 ultra &= ~0x3F; 175 mode &= ~(0x03 << port_shift); 176 177 /* Extract scsc */ 178 scsc = (scsc & 0x30) ? 1: 0; 179 180 if (adev->dma_mode >= XFER_UDMA_0) { 181 multi = 0x10C1; 182 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0]; 183 mode |= (0x03 << port_shift); 184 } else { 185 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0]; 186 mode |= (0x02 << port_shift); 187 } 188 pci_write_config_byte(pdev, addr_mask, mode); 189 pci_write_config_word(pdev, ma, multi); 190 pci_write_config_word(pdev, ua, ultra); 191 } 192 193 /** 194 * sil680_sff_exec_command - issue ATA command to host controller 195 * @ap: port to which command is being issued 196 * @tf: ATA taskfile register set 197 * 198 * Issues ATA command, with proper synchronization with interrupt 199 * handler / other threads. Use our MMIO space for PCI posting to avoid 200 * a hideously slow cycle all the way to the device. 201 * 202 * LOCKING: 203 * spin_lock_irqsave(host lock) 204 */ 205 static void sil680_sff_exec_command(struct ata_port *ap, 206 const struct ata_taskfile *tf) 207 { 208 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 209 iowrite8(tf->command, ap->ioaddr.command_addr); 210 ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 211 } 212 213 static bool sil680_sff_irq_check(struct ata_port *ap) 214 { 215 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 216 unsigned long addr = sil680_selreg(ap, 1); 217 u8 val; 218 219 pci_read_config_byte(pdev, addr, &val); 220 221 return val & 0x08; 222 } 223 224 static struct scsi_host_template sil680_sht = { 225 ATA_BMDMA_SHT(DRV_NAME), 226 }; 227 228 229 static struct ata_port_operations sil680_port_ops = { 230 .inherits = &ata_bmdma32_port_ops, 231 .sff_exec_command = sil680_sff_exec_command, 232 .sff_irq_check = sil680_sff_irq_check, 233 .cable_detect = sil680_cable_detect, 234 .set_piomode = sil680_set_piomode, 235 .set_dmamode = sil680_set_dmamode, 236 }; 237 238 /** 239 * sil680_init_chip - chip setup 240 * @pdev: PCI device 241 * 242 * Perform all the chip setup which must be done both when the device 243 * is powered up on boot and when we resume in case we resumed from RAM. 244 * Returns the final clock settings. 245 */ 246 247 static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio) 248 { 249 u8 tmpbyte = 0; 250 251 /* FIXME: double check */ 252 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 253 pdev->revision ? 1 : 255); 254 255 pci_write_config_byte(pdev, 0x80, 0x00); 256 pci_write_config_byte(pdev, 0x84, 0x00); 257 258 pci_read_config_byte(pdev, 0x8A, &tmpbyte); 259 260 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", 261 tmpbyte & 1, tmpbyte & 0x30); 262 263 *try_mmio = 0; 264 #ifdef CONFIG_PPC 265 if (machine_is(cell)) 266 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5); 267 #endif 268 269 switch(tmpbyte & 0x30) { 270 case 0x00: 271 /* 133 clock attempt to force it on */ 272 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10); 273 break; 274 case 0x30: 275 /* if clocking is disabled */ 276 /* 133 clock attempt to force it on */ 277 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20); 278 break; 279 case 0x10: 280 /* 133 already */ 281 break; 282 case 0x20: 283 /* BIOS set PCI x2 clocking */ 284 break; 285 } 286 287 pci_read_config_byte(pdev, 0x8A, &tmpbyte); 288 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", 289 tmpbyte & 1, tmpbyte & 0x30); 290 291 pci_write_config_byte(pdev, 0xA1, 0x72); 292 pci_write_config_word(pdev, 0xA2, 0x328A); 293 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD); 294 pci_write_config_dword(pdev, 0xA8, 0x43924392); 295 pci_write_config_dword(pdev, 0xAC, 0x40094009); 296 pci_write_config_byte(pdev, 0xB1, 0x72); 297 pci_write_config_word(pdev, 0xB2, 0x328A); 298 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD); 299 pci_write_config_dword(pdev, 0xB8, 0x43924392); 300 pci_write_config_dword(pdev, 0xBC, 0x40094009); 301 302 switch(tmpbyte & 0x30) { 303 case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break; 304 case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break; 305 case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break; 306 /* This last case is _NOT_ ok */ 307 case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n"); 308 } 309 return tmpbyte & 0x30; 310 } 311 312 static int __devinit sil680_init_one(struct pci_dev *pdev, 313 const struct pci_device_id *id) 314 { 315 static const struct ata_port_info info = { 316 .flags = ATA_FLAG_SLAVE_POSS, 317 .pio_mask = ATA_PIO4, 318 .mwdma_mask = ATA_MWDMA2, 319 .udma_mask = ATA_UDMA6, 320 .port_ops = &sil680_port_ops 321 }; 322 static const struct ata_port_info info_slow = { 323 .flags = ATA_FLAG_SLAVE_POSS, 324 .pio_mask = ATA_PIO4, 325 .mwdma_mask = ATA_MWDMA2, 326 .udma_mask = ATA_UDMA5, 327 .port_ops = &sil680_port_ops 328 }; 329 const struct ata_port_info *ppi[] = { &info, NULL }; 330 static int printed_version; 331 struct ata_host *host; 332 void __iomem *mmio_base; 333 int rc, try_mmio; 334 335 if (!printed_version++) 336 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 337 338 rc = pcim_enable_device(pdev); 339 if (rc) 340 return rc; 341 342 switch (sil680_init_chip(pdev, &try_mmio)) { 343 case 0: 344 ppi[0] = &info_slow; 345 break; 346 case 0x30: 347 return -ENODEV; 348 } 349 350 if (!try_mmio) 351 goto use_ioports; 352 353 /* Try to acquire MMIO resources and fallback to PIO if 354 * that fails 355 */ 356 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME); 357 if (rc) 358 goto use_ioports; 359 360 /* Allocate host and set it up */ 361 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 362 if (!host) 363 return -ENOMEM; 364 host->iomap = pcim_iomap_table(pdev); 365 366 /* Setup DMA masks */ 367 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 368 if (rc) 369 return rc; 370 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 371 if (rc) 372 return rc; 373 pci_set_master(pdev); 374 375 /* Get MMIO base and initialize port addresses */ 376 mmio_base = host->iomap[SIL680_MMIO_BAR]; 377 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; 378 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; 379 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; 380 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; 381 ata_sff_std_ports(&host->ports[0]->ioaddr); 382 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; 383 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; 384 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; 385 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; 386 ata_sff_std_ports(&host->ports[1]->ioaddr); 387 388 /* Register & activate */ 389 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 390 IRQF_SHARED, &sil680_sht); 391 392 use_ioports: 393 return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0); 394 } 395 396 #ifdef CONFIG_PM 397 static int sil680_reinit_one(struct pci_dev *pdev) 398 { 399 struct ata_host *host = dev_get_drvdata(&pdev->dev); 400 int try_mmio, rc; 401 402 rc = ata_pci_device_do_resume(pdev); 403 if (rc) 404 return rc; 405 sil680_init_chip(pdev, &try_mmio); 406 ata_host_resume(host); 407 return 0; 408 } 409 #endif 410 411 static const struct pci_device_id sil680[] = { 412 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), }, 413 414 { }, 415 }; 416 417 static struct pci_driver sil680_pci_driver = { 418 .name = DRV_NAME, 419 .id_table = sil680, 420 .probe = sil680_init_one, 421 .remove = ata_pci_remove_one, 422 #ifdef CONFIG_PM 423 .suspend = ata_pci_device_suspend, 424 .resume = sil680_reinit_one, 425 #endif 426 }; 427 428 static int __init sil680_init(void) 429 { 430 return pci_register_driver(&sil680_pci_driver); 431 } 432 433 static void __exit sil680_exit(void) 434 { 435 pci_unregister_driver(&sil680_pci_driver); 436 } 437 438 MODULE_AUTHOR("Alan Cox"); 439 MODULE_DESCRIPTION("low-level driver for SI680 PATA"); 440 MODULE_LICENSE("GPL"); 441 MODULE_DEVICE_TABLE(pci, sil680); 442 MODULE_VERSION(DRV_VERSION); 443 444 module_init(sil680_init); 445 module_exit(sil680_exit); 446