1 /* 2 * pata_serverworks.c - Serverworks PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * 5 * based upon 6 * 7 * serverworks.c 8 * 9 * Copyright (C) 1998-2000 Michel Aubry 10 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz 11 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 12 * Portions copyright (c) 2001 Sun Microsystems 13 * 14 * 15 * RCC/ServerWorks IDE driver for Linux 16 * 17 * OSB4: `Open South Bridge' IDE Interface (fn 1) 18 * supports UDMA mode 2 (33 MB/s) 19 * 20 * CSB5: `Champion South Bridge' IDE Interface (fn 1) 21 * all revisions support UDMA mode 4 (66 MB/s) 22 * revision A2.0 and up support UDMA mode 5 (100 MB/s) 23 * 24 * *** The CSB5 does not provide ANY register *** 25 * *** to detect 80-conductor cable presence. *** 26 * 27 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) 28 * 29 * Documentation: 30 * Available under NDA only. Errata info very hard to get. 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/init.h> 37 #include <linux/blkdev.h> 38 #include <linux/delay.h> 39 #include <scsi/scsi_host.h> 40 #include <linux/libata.h> 41 42 #define DRV_NAME "pata_serverworks" 43 #define DRV_VERSION "0.4.3" 44 45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ 46 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ 47 48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 49 * can overrun their FIFOs when used with the CSB5 */ 50 51 static const char *csb_bad_ata100[] = { 52 "ST320011A", 53 "ST340016A", 54 "ST360021A", 55 "ST380021A", 56 NULL 57 }; 58 59 /** 60 * dell_cable - Dell serverworks cable detection 61 * @ap: ATA port to do cable detect 62 * 63 * Dell hide the 40/80 pin select for their interfaces in the top two 64 * bits of the subsystem ID. 65 */ 66 67 static int dell_cable(struct ata_port *ap) { 68 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 69 70 if (pdev->subsystem_device & (1 << (ap->port_no + 14))) 71 return ATA_CBL_PATA80; 72 return ATA_CBL_PATA40; 73 } 74 75 /** 76 * sun_cable - Sun Cobalt 'Alpine' cable detection 77 * @ap: ATA port to do cable select 78 * 79 * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the 80 * subsystem ID the same as dell. We could use one function but we may 81 * need to extend the Dell one in future 82 */ 83 84 static int sun_cable(struct ata_port *ap) { 85 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 86 87 if (pdev->subsystem_device & (1 << (ap->port_no + 14))) 88 return ATA_CBL_PATA80; 89 return ATA_CBL_PATA40; 90 } 91 92 /** 93 * osb4_cable - OSB4 cable detect 94 * @ap: ATA port to check 95 * 96 * The OSB4 isn't UDMA66 capable so this is easy 97 */ 98 99 static int osb4_cable(struct ata_port *ap) { 100 return ATA_CBL_PATA40; 101 } 102 103 /** 104 * csb_cable - CSB5/6 cable detect 105 * @ap: ATA port to check 106 * 107 * Serverworks default arrangement is to use the drive side detection 108 * only. 109 */ 110 111 static int csb_cable(struct ata_port *ap) { 112 return ATA_CBL_PATA_UNK; 113 } 114 115 struct sv_cable_table { 116 int device; 117 int subvendor; 118 int (*cable_detect)(struct ata_port *ap); 119 }; 120 121 /* 122 * Note that we don't copy the old serverworks code because the old 123 * code contains obvious mistakes 124 */ 125 126 static struct sv_cable_table cable_detect[] = { 127 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable }, 128 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable }, 129 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable }, 130 { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable }, 131 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable }, 132 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable }, 133 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable }, 134 { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable }, 135 { } 136 }; 137 138 /** 139 * serverworks_cable_detect - cable detection 140 * @ap: ATA port 141 * 142 * Perform cable detection according to the device and subvendor 143 * identifications 144 */ 145 146 static int serverworks_cable_detect(struct ata_port *ap) 147 { 148 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 149 struct sv_cable_table *cb = cable_detect; 150 151 while(cb->device) { 152 if (cb->device == pdev->device && 153 (cb->subvendor == pdev->subsystem_vendor || 154 cb->subvendor == PCI_ANY_ID)) { 155 return cb->cable_detect(ap); 156 } 157 cb++; 158 } 159 160 BUG(); 161 return -1; /* kill compiler warning */ 162 } 163 164 /** 165 * serverworks_is_csb - Check for CSB or OSB 166 * @pdev: PCI device to check 167 * 168 * Returns true if the device being checked is known to be a CSB 169 * series device. 170 */ 171 172 static u8 serverworks_is_csb(struct pci_dev *pdev) 173 { 174 switch (pdev->device) { 175 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 176 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 177 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 178 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 179 return 1; 180 default: 181 break; 182 } 183 return 0; 184 } 185 186 /** 187 * serverworks_osb4_filter - mode selection filter 188 * @adev: ATA device 189 * @mask: Mask of proposed modes 190 * 191 * Filter the offered modes for the device to apply controller 192 * specific rules. OSB4 requires no UDMA for disks due to a FIFO 193 * bug we hit. 194 */ 195 196 static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask) 197 { 198 if (adev->class == ATA_DEV_ATA) 199 mask &= ~ATA_MASK_UDMA; 200 return ata_bmdma_mode_filter(adev, mask); 201 } 202 203 204 /** 205 * serverworks_csb_filter - mode selection filter 206 * @adev: ATA device 207 * @mask: Mask of proposed modes 208 * 209 * Check the blacklist and disable UDMA5 if matched 210 */ 211 212 static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask) 213 { 214 const char *p; 215 char model_num[ATA_ID_PROD_LEN + 1]; 216 int i; 217 218 /* Disk, UDMA */ 219 if (adev->class != ATA_DEV_ATA) 220 return ata_bmdma_mode_filter(adev, mask); 221 222 /* Actually do need to check */ 223 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 224 225 for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) { 226 if (!strcmp(p, model_num)) 227 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 228 } 229 return ata_bmdma_mode_filter(adev, mask); 230 } 231 232 /** 233 * serverworks_set_piomode - set initial PIO mode data 234 * @ap: ATA interface 235 * @adev: ATA device 236 * 237 * Program the OSB4/CSB5 timing registers for PIO. The PIO register 238 * load is done as a simple lookup. 239 */ 240 static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev) 241 { 242 static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 243 int offset = 1 + 2 * ap->port_no - adev->devno; 244 int devbits = (2 * ap->port_no + adev->devno) * 4; 245 u16 csb5_pio; 246 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 247 int pio = adev->pio_mode - XFER_PIO_0; 248 249 pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]); 250 251 /* The OSB4 just requires the timing but the CSB series want the 252 mode number as well */ 253 if (serverworks_is_csb(pdev)) { 254 pci_read_config_word(pdev, 0x4A, &csb5_pio); 255 csb5_pio &= ~(0x0F << devbits); 256 pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits)); 257 } 258 } 259 260 /** 261 * serverworks_set_dmamode - set initial DMA mode data 262 * @ap: ATA interface 263 * @adev: ATA device 264 * 265 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5 266 * chipset. The MWDMA mode values are pulled from a lookup table 267 * while the chipset uses mode number for UDMA. 268 */ 269 270 static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev) 271 { 272 static const u8 dma_mode[] = { 0x77, 0x21, 0x20 }; 273 int offset = 1 + 2 * ap->port_no - adev->devno; 274 int devbits = 2 * ap->port_no + adev->devno; 275 u8 ultra; 276 u8 ultra_cfg; 277 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 278 279 pci_read_config_byte(pdev, 0x54, &ultra_cfg); 280 pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra); 281 ultra &= ~(0x0F << (adev->devno * 4)); 282 283 if (adev->dma_mode >= XFER_UDMA_0) { 284 pci_write_config_byte(pdev, 0x44 + offset, 0x20); 285 286 ultra |= (adev->dma_mode - XFER_UDMA_0) 287 << (adev->devno * 4); 288 ultra_cfg |= (1 << devbits); 289 } else { 290 pci_write_config_byte(pdev, 0x44 + offset, 291 dma_mode[adev->dma_mode - XFER_MW_DMA_0]); 292 ultra_cfg &= ~(1 << devbits); 293 } 294 pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra); 295 pci_write_config_byte(pdev, 0x54, ultra_cfg); 296 } 297 298 static struct scsi_host_template serverworks_sht = { 299 ATA_BMDMA_SHT(DRV_NAME), 300 }; 301 302 static struct ata_port_operations serverworks_osb4_port_ops = { 303 .inherits = &ata_bmdma_port_ops, 304 .cable_detect = serverworks_cable_detect, 305 .mode_filter = serverworks_osb4_filter, 306 .set_piomode = serverworks_set_piomode, 307 .set_dmamode = serverworks_set_dmamode, 308 }; 309 310 static struct ata_port_operations serverworks_csb_port_ops = { 311 .inherits = &serverworks_osb4_port_ops, 312 .mode_filter = serverworks_csb_filter, 313 }; 314 315 static int serverworks_fixup_osb4(struct pci_dev *pdev) 316 { 317 u32 reg; 318 struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 319 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); 320 if (isa_dev) { 321 pci_read_config_dword(isa_dev, 0x64, ®); 322 reg &= ~0x00002000; /* disable 600ns interrupt mask */ 323 if (!(reg & 0x00004000)) 324 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n"); 325 reg |= 0x00004000; /* enable UDMA/33 support */ 326 pci_write_config_dword(isa_dev, 0x64, reg); 327 pci_dev_put(isa_dev); 328 return 0; 329 } 330 printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n"); 331 return -ENODEV; 332 } 333 334 static int serverworks_fixup_csb(struct pci_dev *pdev) 335 { 336 u8 btr; 337 338 /* Third Channel Test */ 339 if (!(PCI_FUNC(pdev->devfn) & 1)) { 340 struct pci_dev * findev = NULL; 341 u32 reg4c = 0; 342 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 343 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); 344 if (findev) { 345 pci_read_config_dword(findev, 0x4C, ®4c); 346 reg4c &= ~0x000007FF; 347 reg4c |= 0x00000040; 348 reg4c |= 0x00000020; 349 pci_write_config_dword(findev, 0x4C, reg4c); 350 pci_dev_put(findev); 351 } 352 } else { 353 struct pci_dev * findev = NULL; 354 u8 reg41 = 0; 355 356 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 357 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); 358 if (findev) { 359 pci_read_config_byte(findev, 0x41, ®41); 360 reg41 &= ~0x40; 361 pci_write_config_byte(findev, 0x41, reg41); 362 pci_dev_put(findev); 363 } 364 } 365 /* setup the UDMA Control register 366 * 367 * 1. clear bit 6 to enable DMA 368 * 2. enable DMA modes with bits 0-1 369 * 00 : legacy 370 * 01 : udma2 371 * 10 : udma2/udma4 372 * 11 : udma2/udma4/udma5 373 */ 374 pci_read_config_byte(pdev, 0x5A, &btr); 375 btr &= ~0x40; 376 if (!(PCI_FUNC(pdev->devfn) & 1)) 377 btr |= 0x2; 378 else 379 btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; 380 pci_write_config_byte(pdev, 0x5A, btr); 381 382 return btr; 383 } 384 385 static void serverworks_fixup_ht1000(struct pci_dev *pdev) 386 { 387 u8 btr; 388 /* Setup HT1000 SouthBridge Controller - Single Channel Only */ 389 pci_read_config_byte(pdev, 0x5A, &btr); 390 btr &= ~0x40; 391 btr |= 0x3; 392 pci_write_config_byte(pdev, 0x5A, btr); 393 } 394 395 396 static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 397 { 398 static const struct ata_port_info info[4] = { 399 { /* OSB4 */ 400 .flags = ATA_FLAG_SLAVE_POSS, 401 .pio_mask = ATA_PIO4, 402 .mwdma_mask = ATA_MWDMA2, 403 .udma_mask = ATA_UDMA2, 404 .port_ops = &serverworks_osb4_port_ops 405 }, { /* OSB4 no UDMA */ 406 .flags = ATA_FLAG_SLAVE_POSS, 407 .pio_mask = ATA_PIO4, 408 .mwdma_mask = ATA_MWDMA2, 409 /* No UDMA */ 410 .port_ops = &serverworks_osb4_port_ops 411 }, { /* CSB5 */ 412 .flags = ATA_FLAG_SLAVE_POSS, 413 .pio_mask = ATA_PIO4, 414 .mwdma_mask = ATA_MWDMA2, 415 .udma_mask = ATA_UDMA4, 416 .port_ops = &serverworks_csb_port_ops 417 }, { /* CSB5 - later revisions*/ 418 .flags = ATA_FLAG_SLAVE_POSS, 419 .pio_mask = ATA_PIO4, 420 .mwdma_mask = ATA_MWDMA2, 421 .udma_mask = ATA_UDMA5, 422 .port_ops = &serverworks_csb_port_ops 423 } 424 }; 425 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; 426 int rc; 427 428 rc = pcim_enable_device(pdev); 429 if (rc) 430 return rc; 431 432 /* Force master latency timer to 64 PCI clocks */ 433 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); 434 435 /* OSB4 : South Bridge and IDE */ 436 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { 437 /* Select non UDMA capable OSB4 if we can't do fixups */ 438 if ( serverworks_fixup_osb4(pdev) < 0) 439 ppi[0] = &info[1]; 440 } 441 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ 442 else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || 443 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || 444 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { 445 446 /* If the returned btr is the newer revision then 447 select the right info block */ 448 if (serverworks_fixup_csb(pdev) == 3) 449 ppi[0] = &info[3]; 450 451 /* Is this the 3rd channel CSB6 IDE ? */ 452 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) 453 ppi[1] = &ata_dummy_port_info; 454 } 455 /* setup HT1000E */ 456 else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) 457 serverworks_fixup_ht1000(pdev); 458 459 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) 460 ata_pci_bmdma_clear_simplex(pdev); 461 462 return ata_pci_sff_init_one(pdev, ppi, &serverworks_sht, NULL); 463 } 464 465 #ifdef CONFIG_PM 466 static int serverworks_reinit_one(struct pci_dev *pdev) 467 { 468 struct ata_host *host = dev_get_drvdata(&pdev->dev); 469 int rc; 470 471 rc = ata_pci_device_do_resume(pdev); 472 if (rc) 473 return rc; 474 475 /* Force master latency timer to 64 PCI clocks */ 476 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); 477 478 switch (pdev->device) { 479 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE: 480 serverworks_fixup_osb4(pdev); 481 break; 482 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 483 ata_pci_bmdma_clear_simplex(pdev); 484 /* fall through */ 485 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 486 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 487 serverworks_fixup_csb(pdev); 488 break; 489 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 490 serverworks_fixup_ht1000(pdev); 491 break; 492 } 493 494 ata_host_resume(host); 495 return 0; 496 } 497 #endif 498 499 static const struct pci_device_id serverworks[] = { 500 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0}, 501 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2}, 502 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2}, 503 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2}, 504 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2}, 505 506 { }, 507 }; 508 509 static struct pci_driver serverworks_pci_driver = { 510 .name = DRV_NAME, 511 .id_table = serverworks, 512 .probe = serverworks_init_one, 513 .remove = ata_pci_remove_one, 514 #ifdef CONFIG_PM 515 .suspend = ata_pci_device_suspend, 516 .resume = serverworks_reinit_one, 517 #endif 518 }; 519 520 static int __init serverworks_init(void) 521 { 522 return pci_register_driver(&serverworks_pci_driver); 523 } 524 525 static void __exit serverworks_exit(void) 526 { 527 pci_unregister_driver(&serverworks_pci_driver); 528 } 529 530 MODULE_AUTHOR("Alan Cox"); 531 MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6"); 532 MODULE_LICENSE("GPL"); 533 MODULE_DEVICE_TABLE(pci, serverworks); 534 MODULE_VERSION(DRV_VERSION); 535 536 module_init(serverworks_init); 537 module_exit(serverworks_exit); 538