1 /* 2 * pata_rdc - Driver for later RDC PATA controllers 3 * 4 * This is actually a driver for hardware meeting 5 * INCITS 370-2004 (1510D): ATA Host Adapter Standards 6 * 7 * Based on ata_piix. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2, or (at your option) 12 * any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; see the file COPYING. If not, write to 21 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/init.h> 28 #include <linux/blkdev.h> 29 #include <linux/delay.h> 30 #include <linux/device.h> 31 #include <scsi/scsi_host.h> 32 #include <linux/libata.h> 33 #include <linux/dmi.h> 34 35 #define DRV_NAME "pata_rdc" 36 #define DRV_VERSION "0.01" 37 38 struct rdc_host_priv { 39 u32 saved_iocfg; 40 }; 41 42 /** 43 * rdc_pata_cable_detect - Probe host controller cable detect info 44 * @ap: Port for which cable detect info is desired 45 * 46 * Read 80c cable indicator from ATA PCI device's PCI config 47 * register. This register is normally set by firmware (BIOS). 48 * 49 * LOCKING: 50 * None (inherited from caller). 51 */ 52 53 static int rdc_pata_cable_detect(struct ata_port *ap) 54 { 55 struct rdc_host_priv *hpriv = ap->host->private_data; 56 u8 mask; 57 58 /* check BIOS cable detect results */ 59 mask = 0x30 << (2 * ap->port_no); 60 if ((hpriv->saved_iocfg & mask) == 0) 61 return ATA_CBL_PATA40; 62 return ATA_CBL_PATA80; 63 } 64 65 /** 66 * rdc_pata_prereset - prereset for PATA host controller 67 * @link: Target link 68 * @deadline: deadline jiffies for the operation 69 * 70 * LOCKING: 71 * None (inherited from caller). 72 */ 73 static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline) 74 { 75 struct ata_port *ap = link->ap; 76 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 77 78 static const struct pci_bits rdc_enable_bits[] = { 79 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 80 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 81 }; 82 83 if (!pci_test_config_bits(pdev, &rdc_enable_bits[ap->port_no])) 84 return -ENOENT; 85 return ata_sff_prereset(link, deadline); 86 } 87 88 /** 89 * rdc_set_piomode - Initialize host controller PATA PIO timings 90 * @ap: Port whose timings we are configuring 91 * @adev: um 92 * 93 * Set PIO mode for device, in host controller PCI config space. 94 * 95 * LOCKING: 96 * None (inherited from caller). 97 */ 98 99 static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev) 100 { 101 unsigned int pio = adev->pio_mode - XFER_PIO_0; 102 struct pci_dev *dev = to_pci_dev(ap->host->dev); 103 unsigned int is_slave = (adev->devno != 0); 104 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 105 unsigned int slave_port = 0x44; 106 u16 master_data; 107 u8 slave_data; 108 u8 udma_enable; 109 int control = 0; 110 111 static const /* ISP RTC */ 112 u8 timings[][2] = { { 0, 0 }, 113 { 0, 0 }, 114 { 1, 0 }, 115 { 2, 1 }, 116 { 2, 3 }, }; 117 118 if (pio >= 2) 119 control |= 1; /* TIME1 enable */ 120 if (ata_pio_need_iordy(adev)) 121 control |= 2; /* IE enable */ 122 123 if (adev->class == ATA_DEV_ATA) 124 control |= 4; /* PPE enable */ 125 126 /* PIO configuration clears DTE unconditionally. It will be 127 * programmed in set_dmamode which is guaranteed to be called 128 * after set_piomode if any DMA mode is available. 129 */ 130 pci_read_config_word(dev, master_port, &master_data); 131 if (is_slave) { 132 /* clear TIME1|IE1|PPE1|DTE1 */ 133 master_data &= 0xff0f; 134 /* Enable SITRE (separate slave timing register) */ 135 master_data |= 0x4000; 136 /* enable PPE1, IE1 and TIME1 as needed */ 137 master_data |= (control << 4); 138 pci_read_config_byte(dev, slave_port, &slave_data); 139 slave_data &= (ap->port_no ? 0x0f : 0xf0); 140 /* Load the timing nibble for this slave */ 141 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 142 << (ap->port_no ? 4 : 0); 143 } else { 144 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 145 master_data &= 0xccf0; 146 /* Enable PPE, IE and TIME as appropriate */ 147 master_data |= control; 148 /* load ISP and RCT */ 149 master_data |= 150 (timings[pio][0] << 12) | 151 (timings[pio][1] << 8); 152 } 153 pci_write_config_word(dev, master_port, master_data); 154 if (is_slave) 155 pci_write_config_byte(dev, slave_port, slave_data); 156 157 /* Ensure the UDMA bit is off - it will be turned back on if 158 UDMA is selected */ 159 160 pci_read_config_byte(dev, 0x48, &udma_enable); 161 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 162 pci_write_config_byte(dev, 0x48, udma_enable); 163 } 164 165 /** 166 * rdc_set_dmamode - Initialize host controller PATA PIO timings 167 * @ap: Port whose timings we are configuring 168 * @adev: Drive in question 169 * 170 * Set UDMA mode for device, in host controller PCI config space. 171 * 172 * LOCKING: 173 * None (inherited from caller). 174 */ 175 176 static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev) 177 { 178 struct pci_dev *dev = to_pci_dev(ap->host->dev); 179 u8 master_port = ap->port_no ? 0x42 : 0x40; 180 u16 master_data; 181 u8 speed = adev->dma_mode; 182 int devid = adev->devno + 2 * ap->port_no; 183 u8 udma_enable = 0; 184 185 static const /* ISP RTC */ 186 u8 timings[][2] = { { 0, 0 }, 187 { 0, 0 }, 188 { 1, 0 }, 189 { 2, 1 }, 190 { 2, 3 }, }; 191 192 pci_read_config_word(dev, master_port, &master_data); 193 pci_read_config_byte(dev, 0x48, &udma_enable); 194 195 if (speed >= XFER_UDMA_0) { 196 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 197 u16 udma_timing; 198 u16 ideconf; 199 int u_clock, u_speed; 200 201 /* 202 * UDMA is handled by a combination of clock switching and 203 * selection of dividers 204 * 205 * Handy rule: Odd modes are UDMATIMx 01, even are 02 206 * except UDMA0 which is 00 207 */ 208 u_speed = min(2 - (udma & 1), udma); 209 if (udma == 5) 210 u_clock = 0x1000; /* 100Mhz */ 211 else if (udma > 2) 212 u_clock = 1; /* 66Mhz */ 213 else 214 u_clock = 0; /* 33Mhz */ 215 216 udma_enable |= (1 << devid); 217 218 /* Load the CT/RP selection */ 219 pci_read_config_word(dev, 0x4A, &udma_timing); 220 udma_timing &= ~(3 << (4 * devid)); 221 udma_timing |= u_speed << (4 * devid); 222 pci_write_config_word(dev, 0x4A, udma_timing); 223 224 /* Select a 33/66/100Mhz clock */ 225 pci_read_config_word(dev, 0x54, &ideconf); 226 ideconf &= ~(0x1001 << devid); 227 ideconf |= u_clock << devid; 228 pci_write_config_word(dev, 0x54, ideconf); 229 } else { 230 /* 231 * MWDMA is driven by the PIO timings. We must also enable 232 * IORDY unconditionally along with TIME1. PPE has already 233 * been set when the PIO timing was set. 234 */ 235 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 236 unsigned int control; 237 u8 slave_data; 238 const unsigned int needed_pio[3] = { 239 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 240 }; 241 int pio = needed_pio[mwdma] - XFER_PIO_0; 242 243 control = 3; /* IORDY|TIME1 */ 244 245 /* If the drive MWDMA is faster than it can do PIO then 246 we must force PIO into PIO0 */ 247 248 if (adev->pio_mode < needed_pio[mwdma]) 249 /* Enable DMA timing only */ 250 control |= 8; /* PIO cycles in PIO0 */ 251 252 if (adev->devno) { /* Slave */ 253 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 254 master_data |= control << 4; 255 pci_read_config_byte(dev, 0x44, &slave_data); 256 slave_data &= (ap->port_no ? 0x0f : 0xf0); 257 /* Load the matching timing */ 258 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 259 pci_write_config_byte(dev, 0x44, slave_data); 260 } else { /* Master */ 261 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 262 and master timing bits */ 263 master_data |= control; 264 master_data |= 265 (timings[pio][0] << 12) | 266 (timings[pio][1] << 8); 267 } 268 269 udma_enable &= ~(1 << devid); 270 pci_write_config_word(dev, master_port, master_data); 271 } 272 pci_write_config_byte(dev, 0x48, udma_enable); 273 } 274 275 static struct ata_port_operations rdc_pata_ops = { 276 .inherits = &ata_bmdma32_port_ops, 277 .cable_detect = rdc_pata_cable_detect, 278 .set_piomode = rdc_set_piomode, 279 .set_dmamode = rdc_set_dmamode, 280 .prereset = rdc_pata_prereset, 281 }; 282 283 static struct ata_port_info rdc_port_info = { 284 285 .flags = ATA_FLAG_SLAVE_POSS, 286 .pio_mask = ATA_PIO4, 287 .mwdma_mask = ATA_MWDMA12_ONLY, 288 .udma_mask = ATA_UDMA5, 289 .port_ops = &rdc_pata_ops, 290 }; 291 292 static struct scsi_host_template rdc_sht = { 293 ATA_BMDMA_SHT(DRV_NAME), 294 }; 295 296 /** 297 * rdc_init_one - Register PIIX ATA PCI device with kernel services 298 * @pdev: PCI device to register 299 * @ent: Entry in rdc_pci_tbl matching with @pdev 300 * 301 * Called from kernel PCI layer. We probe for combined mode (sigh), 302 * and then hand over control to libata, for it to do the rest. 303 * 304 * LOCKING: 305 * Inherited from PCI layer (may sleep). 306 * 307 * RETURNS: 308 * Zero on success, or -ERRNO value. 309 */ 310 311 static int __devinit rdc_init_one(struct pci_dev *pdev, 312 const struct pci_device_id *ent) 313 { 314 static int printed_version; 315 struct device *dev = &pdev->dev; 316 struct ata_port_info port_info[2]; 317 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 318 unsigned long port_flags; 319 struct ata_host *host; 320 struct rdc_host_priv *hpriv; 321 int rc; 322 323 if (!printed_version++) 324 dev_printk(KERN_DEBUG, &pdev->dev, 325 "version " DRV_VERSION "\n"); 326 327 port_info[0] = rdc_port_info; 328 port_info[1] = rdc_port_info; 329 330 port_flags = port_info[0].flags; 331 332 /* enable device and prepare host */ 333 rc = pcim_enable_device(pdev); 334 if (rc) 335 return rc; 336 337 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 338 if (!hpriv) 339 return -ENOMEM; 340 341 /* Save IOCFG, this will be used for cable detection, quirk 342 * detection and restoration on detach. 343 */ 344 pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg); 345 346 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 347 if (rc) 348 return rc; 349 host->private_data = hpriv; 350 351 pci_intx(pdev, 1); 352 353 host->flags |= ATA_HOST_PARALLEL_SCAN; 354 355 pci_set_master(pdev); 356 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &rdc_sht); 357 } 358 359 static void rdc_remove_one(struct pci_dev *pdev) 360 { 361 struct ata_host *host = dev_get_drvdata(&pdev->dev); 362 struct rdc_host_priv *hpriv = host->private_data; 363 364 pci_write_config_dword(pdev, 0x54, hpriv->saved_iocfg); 365 366 ata_pci_remove_one(pdev); 367 } 368 369 static const struct pci_device_id rdc_pci_tbl[] = { 370 { PCI_DEVICE(0x17F3, 0x1011), }, 371 { PCI_DEVICE(0x17F3, 0x1012), }, 372 { } /* terminate list */ 373 }; 374 375 static struct pci_driver rdc_pci_driver = { 376 .name = DRV_NAME, 377 .id_table = rdc_pci_tbl, 378 .probe = rdc_init_one, 379 .remove = rdc_remove_one, 380 }; 381 382 383 static int __init rdc_init(void) 384 { 385 return pci_register_driver(&rdc_pci_driver); 386 } 387 388 static void __exit rdc_exit(void) 389 { 390 pci_unregister_driver(&rdc_pci_driver); 391 } 392 393 module_init(rdc_init); 394 module_exit(rdc_exit); 395 396 MODULE_AUTHOR("Alan Cox (based on ata_piix)"); 397 MODULE_DESCRIPTION("SCSI low-level driver for RDC PATA controllers"); 398 MODULE_LICENSE("GPL"); 399 MODULE_DEVICE_TABLE(pci, rdc_pci_tbl); 400 MODULE_VERSION(DRV_VERSION); 401