1 /* 2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * Ported to libata by: 10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation 11 * 12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> 13 * Portions Copyright (C) 1999 Promise Technology, Inc. 14 * 15 * Author: Frank Tiernan (frankt@promise.com) 16 * Released under terms of General Public License 17 * 18 * 19 * libata documentation is available via 'make {ps|pdf}docs', 20 * as Documentation/DocBook/libata.* 21 * 22 * Hardware information only available under NDA. 23 * 24 */ 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include <linux/init.h> 29 #include <linux/blkdev.h> 30 #include <linux/delay.h> 31 #include <linux/device.h> 32 #include <scsi/scsi.h> 33 #include <scsi/scsi_host.h> 34 #include <scsi/scsi_cmnd.h> 35 #include <linux/libata.h> 36 37 #define DRV_NAME "pata_pdc2027x" 38 #define DRV_VERSION "1.0" 39 #undef PDC_DEBUG 40 41 #ifdef PDC_DEBUG 42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 43 #else 44 #define PDPRINTK(fmt, args...) 45 #endif 46 47 enum { 48 PDC_MMIO_BAR = 5, 49 50 PDC_UDMA_100 = 0, 51 PDC_UDMA_133 = 1, 52 53 PDC_100_MHZ = 100000000, 54 PDC_133_MHZ = 133333333, 55 56 PDC_SYS_CTL = 0x1100, 57 PDC_ATA_CTL = 0x1104, 58 PDC_GLOBAL_CTL = 0x1108, 59 PDC_CTCR0 = 0x110C, 60 PDC_CTCR1 = 0x1110, 61 PDC_BYTE_COUNT = 0x1120, 62 PDC_PLL_CTL = 0x1202, 63 }; 64 65 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 66 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline); 67 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev); 68 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev); 69 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc); 70 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask); 71 static int pdc2027x_cable_detect(struct ata_port *ap); 72 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed); 73 74 /* 75 * ATA Timing Tables based on 133MHz controller clock. 76 * These tables are only used when the controller is in 133MHz clock. 77 * If the controller is in 100MHz clock, the ASIC hardware will 78 * set the timing registers automatically when "set feature" command 79 * is issued to the device. However, if the controller clock is 133MHz, 80 * the following tables must be used. 81 */ 82 static struct pdc2027x_pio_timing { 83 u8 value0, value1, value2; 84 } pdc2027x_pio_timing_tbl [] = { 85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ 86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ 87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */ 88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ 89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ 90 }; 91 92 static struct pdc2027x_mdma_timing { 93 u8 value0, value1; 94 } pdc2027x_mdma_timing_tbl [] = { 95 { 0xdf, 0x5f }, /* MDMA mode 0 */ 96 { 0x6b, 0x27 }, /* MDMA mode 1 */ 97 { 0x69, 0x25 }, /* MDMA mode 2 */ 98 }; 99 100 static struct pdc2027x_udma_timing { 101 u8 value0, value1, value2; 102 } pdc2027x_udma_timing_tbl [] = { 103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ 104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ 105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ 106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ 107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ 108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ 109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ 110 }; 111 112 static const struct pci_device_id pdc2027x_pci_tbl[] = { 113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 }, 114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 }, 115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 }, 116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 }, 117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 }, 118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 }, 119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 }, 120 121 { } /* terminate list */ 122 }; 123 124 static struct pci_driver pdc2027x_pci_driver = { 125 .name = DRV_NAME, 126 .id_table = pdc2027x_pci_tbl, 127 .probe = pdc2027x_init_one, 128 .remove = ata_pci_remove_one, 129 }; 130 131 static struct scsi_host_template pdc2027x_sht = { 132 ATA_BMDMA_SHT(DRV_NAME), 133 }; 134 135 static struct ata_port_operations pdc2027x_pata100_ops = { 136 .inherits = &ata_bmdma_port_ops, 137 .check_atapi_dma = pdc2027x_check_atapi_dma, 138 .cable_detect = pdc2027x_cable_detect, 139 .prereset = pdc2027x_prereset, 140 }; 141 142 static struct ata_port_operations pdc2027x_pata133_ops = { 143 .inherits = &pdc2027x_pata100_ops, 144 .mode_filter = pdc2027x_mode_filter, 145 .set_piomode = pdc2027x_set_piomode, 146 .set_dmamode = pdc2027x_set_dmamode, 147 .set_mode = pdc2027x_set_mode, 148 }; 149 150 static struct ata_port_info pdc2027x_port_info[] = { 151 /* PDC_UDMA_100 */ 152 { 153 .flags = ATA_FLAG_SLAVE_POSS, 154 .pio_mask = ATA_PIO4, 155 .mwdma_mask = ATA_MWDMA2, 156 .udma_mask = ATA_UDMA5, 157 .port_ops = &pdc2027x_pata100_ops, 158 }, 159 /* PDC_UDMA_133 */ 160 { 161 .flags = ATA_FLAG_SLAVE_POSS, 162 .pio_mask = ATA_PIO4, 163 .mwdma_mask = ATA_MWDMA2, 164 .udma_mask = ATA_UDMA6, 165 .port_ops = &pdc2027x_pata133_ops, 166 }, 167 }; 168 169 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee"); 170 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277"); 171 MODULE_LICENSE("GPL"); 172 MODULE_VERSION(DRV_VERSION); 173 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); 174 175 /** 176 * port_mmio - Get the MMIO address of PDC2027x extended registers 177 * @ap: Port 178 * @offset: offset from mmio base 179 */ 180 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) 181 { 182 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; 183 } 184 185 /** 186 * dev_mmio - Get the MMIO address of PDC2027x extended registers 187 * @ap: Port 188 * @adev: device 189 * @offset: offset from mmio base 190 */ 191 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset) 192 { 193 u8 adj = (adev->devno) ? 0x08 : 0x00; 194 return port_mmio(ap, offset) + adj; 195 } 196 197 /** 198 * pdc2027x_pata_cable_detect - Probe host controller cable detect info 199 * @ap: Port for which cable detect info is desired 200 * 201 * Read 80c cable indicator from Promise extended register. 202 * This register is latched when the system is reset. 203 * 204 * LOCKING: 205 * None (inherited from caller). 206 */ 207 static int pdc2027x_cable_detect(struct ata_port *ap) 208 { 209 u32 cgcr; 210 211 /* check cable detect results */ 212 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL)); 213 if (cgcr & (1 << 26)) 214 goto cbl40; 215 216 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no); 217 218 return ATA_CBL_PATA80; 219 cbl40: 220 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no); 221 return ATA_CBL_PATA40; 222 } 223 224 /** 225 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled. 226 * @ap: Port to check 227 */ 228 static inline int pdc2027x_port_enabled(struct ata_port *ap) 229 { 230 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02; 231 } 232 233 /** 234 * pdc2027x_prereset - prereset for PATA host controller 235 * @link: Target link 236 * @deadline: deadline jiffies for the operation 237 * 238 * Probeinit including cable detection. 239 * 240 * LOCKING: 241 * None (inherited from caller). 242 */ 243 244 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline) 245 { 246 /* Check whether port enabled */ 247 if (!pdc2027x_port_enabled(link->ap)) 248 return -ENOENT; 249 return ata_sff_prereset(link, deadline); 250 } 251 252 /** 253 * pdc2720x_mode_filter - mode selection filter 254 * @adev: ATA device 255 * @mask: list of modes proposed 256 * 257 * Block UDMA on devices that cause trouble with this controller. 258 */ 259 260 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask) 261 { 262 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 263 struct ata_device *pair = ata_dev_pair(adev); 264 265 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL) 266 return mask; 267 268 /* Check for slave of a Maxtor at UDMA6 */ 269 ata_id_c_string(pair->id, model_num, ATA_ID_PROD, 270 ATA_ID_PROD_LEN + 1); 271 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */ 272 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6) 273 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA)); 274 275 return mask; 276 } 277 278 /** 279 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings 280 * @ap: Port to configure 281 * @adev: um 282 * 283 * Set PIO mode for device. 284 * 285 * LOCKING: 286 * None (inherited from caller). 287 */ 288 289 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev) 290 { 291 unsigned int pio = adev->pio_mode - XFER_PIO_0; 292 u32 ctcr0, ctcr1; 293 294 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode); 295 296 /* Sanity check */ 297 if (pio > 4) { 298 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio); 299 return; 300 301 } 302 303 /* Set the PIO timing registers using value table for 133MHz */ 304 PDPRINTK("Set pio regs... \n"); 305 306 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); 307 ctcr0 &= 0xffff0000; 308 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | 309 (pdc2027x_pio_timing_tbl[pio].value1 << 8); 310 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); 311 312 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 313 ctcr1 &= 0x00ffffff; 314 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); 315 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); 316 317 PDPRINTK("Set pio regs done\n"); 318 319 PDPRINTK("Set to pio mode[%u] \n", pio); 320 } 321 322 /** 323 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings 324 * @ap: Port to configure 325 * @adev: um 326 * 327 * Set UDMA mode for device. 328 * 329 * LOCKING: 330 * None (inherited from caller). 331 */ 332 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 333 { 334 unsigned int dma_mode = adev->dma_mode; 335 u32 ctcr0, ctcr1; 336 337 if ((dma_mode >= XFER_UDMA_0) && 338 (dma_mode <= XFER_UDMA_6)) { 339 /* Set the UDMA timing registers with value table for 133MHz */ 340 unsigned int udma_mode = dma_mode & 0x07; 341 342 if (dma_mode == XFER_UDMA_2) { 343 /* 344 * Turn off tHOLD. 345 * If tHOLD is '1', the hardware will add half clock for data hold time. 346 * This code segment seems to be no effect. tHOLD will be overwritten below. 347 */ 348 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 349 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1)); 350 } 351 352 PDPRINTK("Set udma regs... \n"); 353 354 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 355 ctcr1 &= 0xff000000; 356 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | 357 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) | 358 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); 359 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); 360 361 PDPRINTK("Set udma regs done\n"); 362 363 PDPRINTK("Set to udma mode[%u] \n", udma_mode); 364 365 } else if ((dma_mode >= XFER_MW_DMA_0) && 366 (dma_mode <= XFER_MW_DMA_2)) { 367 /* Set the MDMA timing registers with value table for 133MHz */ 368 unsigned int mdma_mode = dma_mode & 0x07; 369 370 PDPRINTK("Set mdma regs... \n"); 371 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); 372 373 ctcr0 &= 0x0000ffff; 374 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | 375 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24); 376 377 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); 378 PDPRINTK("Set mdma regs done\n"); 379 380 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); 381 } else { 382 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode); 383 } 384 } 385 386 /** 387 * pdc2027x_set_mode - Set the timing registers back to correct values. 388 * @link: link to configure 389 * @r_failed: Returned device for failure 390 * 391 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers 392 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL. 393 * This function overwrites the possibly incorrect values set by the hardware to be correct. 394 */ 395 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed) 396 { 397 struct ata_port *ap = link->ap; 398 struct ata_device *dev; 399 int rc; 400 401 rc = ata_do_set_mode(link, r_failed); 402 if (rc < 0) 403 return rc; 404 405 ata_for_each_dev(dev, link, ENABLED) { 406 pdc2027x_set_piomode(ap, dev); 407 408 /* 409 * Enable prefetch if the device support PIO only. 410 */ 411 if (dev->xfer_shift == ATA_SHIFT_PIO) { 412 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1)); 413 ctcr1 |= (1 << 25); 414 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1)); 415 416 PDPRINTK("Turn on prefetch\n"); 417 } else { 418 pdc2027x_set_dmamode(ap, dev); 419 } 420 } 421 return 0; 422 } 423 424 /** 425 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command 426 * @qc: Metadata associated with taskfile to check 427 * 428 * LOCKING: 429 * None (inherited from caller). 430 * 431 * RETURNS: 0 when ATAPI DMA can be used 432 * 1 otherwise 433 */ 434 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) 435 { 436 struct scsi_cmnd *cmd = qc->scsicmd; 437 u8 *scsicmd = cmd->cmnd; 438 int rc = 1; /* atapi dma off by default */ 439 440 /* 441 * This workaround is from Promise's GPL driver. 442 * If ATAPI DMA is used for commands not in the 443 * following white list, say MODE_SENSE and REQUEST_SENSE, 444 * pdc2027x might hit the irq lost problem. 445 */ 446 switch (scsicmd[0]) { 447 case READ_10: 448 case WRITE_10: 449 case READ_12: 450 case WRITE_12: 451 case READ_6: 452 case WRITE_6: 453 case 0xad: /* READ_DVD_STRUCTURE */ 454 case 0xbe: /* READ_CD */ 455 /* ATAPI DMA is ok */ 456 rc = 0; 457 break; 458 default: 459 ; 460 } 461 462 return rc; 463 } 464 465 /** 466 * pdc_read_counter - Read the ctr counter 467 * @host: target ATA host 468 */ 469 470 static long pdc_read_counter(struct ata_host *host) 471 { 472 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 473 long counter; 474 int retry = 1; 475 u32 bccrl, bccrh, bccrlv, bccrhv; 476 477 retry: 478 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 479 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 480 481 /* Read the counter values again for verification */ 482 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 483 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 484 485 counter = (bccrh << 15) | bccrl; 486 487 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl); 488 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); 489 490 /* 491 * The 30-bit decreasing counter are read by 2 pieces. 492 * Incorrect value may be read when both bccrh and bccrl are changing. 493 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read. 494 */ 495 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) { 496 retry--; 497 PDPRINTK("rereading counter\n"); 498 goto retry; 499 } 500 501 return counter; 502 } 503 504 /** 505 * adjust_pll - Adjust the PLL input clock in Hz. 506 * 507 * @pdc_controller: controller specific information 508 * @host: target ATA host 509 * @pll_clock: The input of PLL in HZ 510 */ 511 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx) 512 { 513 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 514 u16 pll_ctl; 515 long pll_clock_khz = pll_clock / 1000; 516 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; 517 long ratio = pout_required / pll_clock_khz; 518 int F, R; 519 520 /* Sanity check */ 521 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { 522 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz); 523 return; 524 } 525 526 #ifdef PDC_DEBUG 527 PDPRINTK("pout_required is %ld\n", pout_required); 528 529 /* Show the current clock value of PLL control register 530 * (maybe already configured by the firmware) 531 */ 532 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 533 534 PDPRINTK("pll_ctl[%X]\n", pll_ctl); 535 #endif 536 537 /* 538 * Calculate the ratio of F, R and OD 539 * POUT = (F + 2) / (( R + 2) * NO) 540 */ 541 if (ratio < 8600L) { /* 8.6x */ 542 /* Using NO = 0x01, R = 0x0D */ 543 R = 0x0d; 544 } else if (ratio < 12900L) { /* 12.9x */ 545 /* Using NO = 0x01, R = 0x08 */ 546 R = 0x08; 547 } else if (ratio < 16100L) { /* 16.1x */ 548 /* Using NO = 0x01, R = 0x06 */ 549 R = 0x06; 550 } else if (ratio < 64000L) { /* 64x */ 551 R = 0x00; 552 } else { 553 /* Invalid ratio */ 554 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio); 555 return; 556 } 557 558 F = (ratio * (R+2)) / 1000 - 2; 559 560 if (unlikely(F < 0 || F > 127)) { 561 /* Invalid F */ 562 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F); 563 return; 564 } 565 566 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); 567 568 pll_ctl = (R << 8) | F; 569 570 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); 571 572 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); 573 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ 574 575 /* Wait the PLL circuit to be stable */ 576 mdelay(30); 577 578 #ifdef PDC_DEBUG 579 /* 580 * Show the current clock value of PLL control register 581 * (maybe configured by the firmware) 582 */ 583 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 584 585 PDPRINTK("pll_ctl[%X]\n", pll_ctl); 586 #endif 587 588 return; 589 } 590 591 /** 592 * detect_pll_input_clock - Detect the PLL input clock in Hz. 593 * @host: target ATA host 594 * Ex. 16949000 on 33MHz PCI bus for pdc20275. 595 * Half of the PCI clock. 596 */ 597 static long pdc_detect_pll_input_clock(struct ata_host *host) 598 { 599 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 600 u32 scr; 601 long start_count, end_count; 602 struct timeval start_time, end_time; 603 long pll_clock, usec_elapsed; 604 605 /* Start the test mode */ 606 scr = ioread32(mmio_base + PDC_SYS_CTL); 607 PDPRINTK("scr[%X]\n", scr); 608 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL); 609 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ 610 611 /* Read current counter value */ 612 start_count = pdc_read_counter(host); 613 do_gettimeofday(&start_time); 614 615 /* Let the counter run for 100 ms. */ 616 mdelay(100); 617 618 /* Read the counter values again */ 619 end_count = pdc_read_counter(host); 620 do_gettimeofday(&end_time); 621 622 /* Stop the test mode */ 623 scr = ioread32(mmio_base + PDC_SYS_CTL); 624 PDPRINTK("scr[%X]\n", scr); 625 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL); 626 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ 627 628 /* calculate the input clock in Hz */ 629 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 + 630 (end_time.tv_usec - start_time.tv_usec); 631 632 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 * 633 (100000000 / usec_elapsed); 634 635 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count); 636 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock); 637 638 return pll_clock; 639 } 640 641 /** 642 * pdc_hardware_init - Initialize the hardware. 643 * @host: target ATA host 644 * @board_idx: board identifier 645 */ 646 static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx) 647 { 648 long pll_clock; 649 650 /* 651 * Detect PLL input clock rate. 652 * On some system, where PCI bus is running at non-standard clock rate. 653 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time. 654 * The pdc20275 controller employs PLL circuit to help correct timing registers setting. 655 */ 656 pll_clock = pdc_detect_pll_input_clock(host); 657 658 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); 659 660 /* Adjust PLL control register */ 661 pdc_adjust_pll(host, pll_clock, board_idx); 662 663 return 0; 664 } 665 666 /** 667 * pdc_ata_setup_port - setup the mmio address 668 * @port: ata ioports to setup 669 * @base: base address 670 */ 671 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) 672 { 673 port->cmd_addr = 674 port->data_addr = base; 675 port->feature_addr = 676 port->error_addr = base + 0x05; 677 port->nsect_addr = base + 0x0a; 678 port->lbal_addr = base + 0x0f; 679 port->lbam_addr = base + 0x10; 680 port->lbah_addr = base + 0x15; 681 port->device_addr = base + 0x1a; 682 port->command_addr = 683 port->status_addr = base + 0x1f; 684 port->altstatus_addr = 685 port->ctl_addr = base + 0x81a; 686 } 687 688 /** 689 * pdc2027x_init_one - PCI probe function 690 * Called when an instance of PCI adapter is inserted. 691 * This function checks whether the hardware is supported, 692 * initialize hardware and register an instance of ata_host to 693 * libata. (implements struct pci_driver.probe() ) 694 * 695 * @pdev: instance of pci_dev found 696 * @ent: matching entry in the id_tbl[] 697 */ 698 static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 699 { 700 static int printed_version; 701 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 }; 702 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 }; 703 unsigned int board_idx = (unsigned int) ent->driver_data; 704 const struct ata_port_info *ppi[] = 705 { &pdc2027x_port_info[board_idx], NULL }; 706 struct ata_host *host; 707 void __iomem *mmio_base; 708 int i, rc; 709 710 if (!printed_version++) 711 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 712 713 /* alloc host */ 714 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 715 if (!host) 716 return -ENOMEM; 717 718 /* acquire resources and fill host */ 719 rc = pcim_enable_device(pdev); 720 if (rc) 721 return rc; 722 723 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 724 if (rc) 725 return rc; 726 host->iomap = pcim_iomap_table(pdev); 727 728 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 729 if (rc) 730 return rc; 731 732 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 733 if (rc) 734 return rc; 735 736 mmio_base = host->iomap[PDC_MMIO_BAR]; 737 738 for (i = 0; i < 2; i++) { 739 struct ata_port *ap = host->ports[i]; 740 741 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]); 742 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i]; 743 744 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 745 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd"); 746 } 747 748 //pci_enable_intx(pdev); 749 750 /* initialize adapter */ 751 if (pdc_hardware_init(host, board_idx) != 0) 752 return -EIO; 753 754 pci_set_master(pdev); 755 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 756 IRQF_SHARED, &pdc2027x_sht); 757 } 758 759 /** 760 * pdc2027x_init - Called after this module is loaded into the kernel. 761 */ 762 static int __init pdc2027x_init(void) 763 { 764 return pci_register_driver(&pdc2027x_pci_driver); 765 } 766 767 /** 768 * pdc2027x_exit - Called before this module unloaded from the kernel 769 */ 770 static void __exit pdc2027x_exit(void) 771 { 772 pci_unregister_driver(&pdc2027x_pci_driver); 773 } 774 775 module_init(pdc2027x_init); 776 module_exit(pdc2027x_exit); 777