1 /* 2 * pata_ninja32.c - Ninja32 PATA for new ATA layer 3 * (C) 2007 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * Note: The controller like many controllers has shared timings for 7 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back 8 * in the dma_stop function. Thus we actually don't need a set_dmamode 9 * method as the PIO method is always called and will set the right PIO 10 * timing parameters. 11 * 12 * The Ninja32 Cardbus is not a generic SFF controller. Instead it is 13 * laid out as follows off BAR 0. This is based upon Mark Lord's delkin 14 * driver and the extensive analysis done by the BSD developers, notably 15 * ITOH Yasufumi. 16 * 17 * Base + 0x00 IRQ Status 18 * Base + 0x01 IRQ control 19 * Base + 0x02 Chipset control 20 * Base + 0x03 Unknown 21 * Base + 0x04 VDMA and reset control + wait bits 22 * Base + 0x08 BMIMBA 23 * Base + 0x0C DMA Length 24 * Base + 0x10 Taskfile 25 * Base + 0x18 BMDMA Status ? 26 * Base + 0x1C 27 * Base + 0x1D Bus master control 28 * bit 0 = enable 29 * bit 1 = 0 write/1 read 30 * bit 2 = 1 sgtable 31 * bit 3 = go 32 * bit 4-6 wait bits 33 * bit 7 = done 34 * Base + 0x1E AltStatus 35 * Base + 0x1F timing register 36 */ 37 38 #include <linux/kernel.h> 39 #include <linux/module.h> 40 #include <linux/pci.h> 41 #include <linux/init.h> 42 #include <linux/blkdev.h> 43 #include <linux/delay.h> 44 #include <scsi/scsi_host.h> 45 #include <linux/libata.h> 46 47 #define DRV_NAME "pata_ninja32" 48 #define DRV_VERSION "0.0.1" 49 50 51 /** 52 * ninja32_set_piomode - set initial PIO mode data 53 * @ap: ATA interface 54 * @adev: ATA device 55 * 56 * Called to do the PIO mode setup. Our timing registers are shared 57 * but we want to set the PIO timing by default. 58 */ 59 60 static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev) 61 { 62 static u16 pio_timing[5] = { 63 0xd6, 0x85, 0x44, 0x33, 0x13 64 }; 65 iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0], 66 ap->ioaddr.bmdma_addr + 0x1f); 67 ap->private_data = adev; 68 } 69 70 71 static void ninja32_dev_select(struct ata_port *ap, unsigned int device) 72 { 73 struct ata_device *adev = &ap->link.device[device]; 74 if (ap->private_data != adev) { 75 iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f); 76 ata_std_dev_select(ap, device); 77 ninja32_set_piomode(ap, adev); 78 } 79 } 80 81 static struct scsi_host_template ninja32_sht = { 82 .module = THIS_MODULE, 83 .name = DRV_NAME, 84 .ioctl = ata_scsi_ioctl, 85 .queuecommand = ata_scsi_queuecmd, 86 .can_queue = ATA_DEF_QUEUE, 87 .this_id = ATA_SHT_THIS_ID, 88 .sg_tablesize = LIBATA_MAX_PRD, 89 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 90 .emulated = ATA_SHT_EMULATED, 91 .use_clustering = ATA_SHT_USE_CLUSTERING, 92 .proc_name = DRV_NAME, 93 .dma_boundary = ATA_DMA_BOUNDARY, 94 .slave_configure = ata_scsi_slave_config, 95 .slave_destroy = ata_scsi_slave_destroy, 96 .bios_param = ata_std_bios_param, 97 }; 98 99 static struct ata_port_operations ninja32_port_ops = { 100 .set_piomode = ninja32_set_piomode, 101 .mode_filter = ata_pci_default_filter, 102 103 .tf_load = ata_tf_load, 104 .tf_read = ata_tf_read, 105 .check_status = ata_check_status, 106 .exec_command = ata_exec_command, 107 .dev_select = ninja32_dev_select, 108 109 .freeze = ata_bmdma_freeze, 110 .thaw = ata_bmdma_thaw, 111 .error_handler = ata_bmdma_error_handler, 112 .post_internal_cmd = ata_bmdma_post_internal_cmd, 113 .cable_detect = ata_cable_40wire, 114 115 .bmdma_setup = ata_bmdma_setup, 116 .bmdma_start = ata_bmdma_start, 117 .bmdma_stop = ata_bmdma_stop, 118 .bmdma_status = ata_bmdma_status, 119 120 .qc_prep = ata_qc_prep, 121 .qc_issue = ata_qc_issue_prot, 122 123 .data_xfer = ata_data_xfer, 124 125 .irq_handler = ata_interrupt, 126 .irq_clear = ata_bmdma_irq_clear, 127 .irq_on = ata_irq_on, 128 129 .port_start = ata_sff_port_start, 130 }; 131 132 static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) 133 { 134 struct ata_host *host; 135 struct ata_port *ap; 136 void __iomem *base; 137 int rc; 138 139 host = ata_host_alloc(&dev->dev, 1); 140 if (!host) 141 return -ENOMEM; 142 ap = host->ports[0]; 143 144 /* Set up the PCI device */ 145 rc = pcim_enable_device(dev); 146 if (rc) 147 return rc; 148 rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME); 149 if (rc == -EBUSY) 150 pcim_pin_device(dev); 151 if (rc) 152 return rc; 153 154 host->iomap = pcim_iomap_table(dev); 155 rc = pci_set_dma_mask(dev, ATA_DMA_MASK); 156 if (rc) 157 return rc; 158 rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK); 159 if (rc) 160 return rc; 161 pci_set_master(dev); 162 163 /* Set up the register mappings */ 164 base = host->iomap[0]; 165 if (!base) 166 return -ENOMEM; 167 ap->ops = &ninja32_port_ops; 168 ap->pio_mask = 0x1F; 169 ap->flags |= ATA_FLAG_SLAVE_POSS; 170 171 ap->ioaddr.cmd_addr = base + 0x10; 172 ap->ioaddr.ctl_addr = base + 0x1E; 173 ap->ioaddr.altstatus_addr = base + 0x1E; 174 ap->ioaddr.bmdma_addr = base; 175 ata_std_ports(&ap->ioaddr); 176 177 iowrite8(0x05, base + 0x01); /* Enable interrupt lines */ 178 iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */ 179 iowrite8(0x01, base + 0x03); /* Unknown */ 180 iowrite8(0x20, base + 0x04); /* WAIT0 */ 181 iowrite8(0x8f, base + 0x05); /* Unknown */ 182 iowrite8(0xa4, base + 0x1c); /* Unknown */ 183 iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */ 184 /* FIXME: Should we disable them at remove ? */ 185 return ata_host_activate(host, dev->irq, ata_interrupt, 186 IRQF_SHARED, &ninja32_sht); 187 } 188 189 static const struct pci_device_id ninja32[] = { 190 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 191 { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 192 { }, 193 }; 194 195 static struct pci_driver ninja32_pci_driver = { 196 .name = DRV_NAME, 197 .id_table = ninja32, 198 .probe = ninja32_init_one, 199 .remove = ata_pci_remove_one 200 }; 201 202 static int __init ninja32_init(void) 203 { 204 return pci_register_driver(&ninja32_pci_driver); 205 } 206 207 static void __exit ninja32_exit(void) 208 { 209 pci_unregister_driver(&ninja32_pci_driver); 210 } 211 212 MODULE_AUTHOR("Alan Cox"); 213 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA"); 214 MODULE_LICENSE("GPL"); 215 MODULE_DEVICE_TABLE(pci, ninja32); 216 MODULE_VERSION(DRV_VERSION); 217 218 module_init(ninja32_init); 219 module_exit(ninja32_exit); 220