1 /* 2 * drivers/ata/pata_mpc52xx.c 3 * 4 * libata driver for the Freescale MPC52xx on-chip IDE interface 5 * 6 * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com> 7 * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt 8 * 9 * UDMA support based on patches by Freescale (Bernard Kuhn, John Rigby), 10 * Domen Puncer and Tim Yamin. 11 * 12 * This file is licensed under the terms of the GNU General Public License 13 * version 2. This program is licensed "as is" without any warranty of any 14 * kind, whether express or implied. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/gfp.h> 20 #include <linux/delay.h> 21 #include <linux/libata.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/types.h> 26 27 #include <asm/cacheflush.h> 28 #include <asm/mpc52xx.h> 29 30 #include <linux/fsl/bestcomm/bestcomm.h> 31 #include <linux/fsl/bestcomm/bestcomm_priv.h> 32 #include <linux/fsl/bestcomm/ata.h> 33 34 #define DRV_NAME "mpc52xx_ata" 35 36 /* Private structures used by the driver */ 37 struct mpc52xx_ata_timings { 38 u32 pio1; 39 u32 pio2; 40 u32 mdma1; 41 u32 mdma2; 42 u32 udma1; 43 u32 udma2; 44 u32 udma3; 45 u32 udma4; 46 u32 udma5; 47 int using_udma; 48 }; 49 50 struct mpc52xx_ata_priv { 51 unsigned int ipb_period; 52 struct mpc52xx_ata __iomem *ata_regs; 53 phys_addr_t ata_regs_pa; 54 int ata_irq; 55 struct mpc52xx_ata_timings timings[2]; 56 int csel; 57 58 /* DMA */ 59 struct bcom_task *dmatsk; 60 const struct udmaspec *udmaspec; 61 const struct mdmaspec *mdmaspec; 62 int mpc52xx_ata_dma_last_write; 63 int waiting_for_dma; 64 }; 65 66 67 /* ATAPI-4 PIO specs (in ns) */ 68 static const u16 ataspec_t0[5] = {600, 383, 240, 180, 120}; 69 static const u16 ataspec_t1[5] = { 70, 50, 30, 30, 25}; 70 static const u16 ataspec_t2_8[5] = {290, 290, 290, 80, 70}; 71 static const u16 ataspec_t2_16[5] = {165, 125, 100, 80, 70}; 72 static const u16 ataspec_t2i[5] = { 0, 0, 0, 70, 25}; 73 static const u16 ataspec_t4[5] = { 30, 20, 15, 10, 10}; 74 static const u16 ataspec_ta[5] = { 35, 35, 35, 35, 35}; 75 76 #define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c))) 77 78 /* ======================================================================== */ 79 80 /* ATAPI-4 MDMA specs (in clocks) */ 81 struct mdmaspec { 82 u8 t0M; 83 u8 td; 84 u8 th; 85 u8 tj; 86 u8 tkw; 87 u8 tm; 88 u8 tn; 89 }; 90 91 static const struct mdmaspec mdmaspec66[3] = { 92 { .t0M = 32, .td = 15, .th = 2, .tj = 2, .tkw = 15, .tm = 4, .tn = 1 }, 93 { .t0M = 10, .td = 6, .th = 1, .tj = 1, .tkw = 4, .tm = 2, .tn = 1 }, 94 { .t0M = 8, .td = 5, .th = 1, .tj = 1, .tkw = 2, .tm = 2, .tn = 1 }, 95 }; 96 97 static const struct mdmaspec mdmaspec132[3] = { 98 { .t0M = 64, .td = 29, .th = 3, .tj = 3, .tkw = 29, .tm = 7, .tn = 2 }, 99 { .t0M = 20, .td = 11, .th = 2, .tj = 1, .tkw = 7, .tm = 4, .tn = 1 }, 100 { .t0M = 16, .td = 10, .th = 2, .tj = 1, .tkw = 4, .tm = 4, .tn = 1 }, 101 }; 102 103 /* ATAPI-4 UDMA specs (in clocks) */ 104 struct udmaspec { 105 u8 tcyc; 106 u8 t2cyc; 107 u8 tds; 108 u8 tdh; 109 u8 tdvs; 110 u8 tdvh; 111 u8 tfs; 112 u8 tli; 113 u8 tmli; 114 u8 taz; 115 u8 tzah; 116 u8 tenv; 117 u8 tsr; 118 u8 trfs; 119 u8 trp; 120 u8 tack; 121 u8 tss; 122 }; 123 124 static const struct udmaspec udmaspec66[6] = { 125 { .tcyc = 8, .t2cyc = 16, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1, 126 .tfs = 16, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, 127 .tsr = 3, .trfs = 5, .trp = 11, .tack = 2, .tss = 4, 128 }, 129 { .tcyc = 5, .t2cyc = 11, .tds = 1, .tdh = 1, .tdvs = 4, .tdvh = 1, 130 .tfs = 14, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, 131 .tsr = 2, .trfs = 5, .trp = 9, .tack = 2, .tss = 4, 132 }, 133 { .tcyc = 4, .t2cyc = 8, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1, 134 .tfs = 12, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, 135 .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4, 136 }, 137 { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 2, .tdvh = 1, 138 .tfs = 9, .tli = 7, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, 139 .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4, 140 }, 141 { .tcyc = 2, .t2cyc = 4, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1, 142 .tfs = 8, .tli = 8, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, 143 .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4, 144 }, 145 { .tcyc = 2, .t2cyc = 2, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1, 146 .tfs = 6, .tli = 5, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, 147 .tsr = 2, .trfs = 4, .trp = 6, .tack = 2, .tss = 4, 148 }, 149 }; 150 151 static const struct udmaspec udmaspec132[6] = { 152 { .tcyc = 15, .t2cyc = 31, .tds = 2, .tdh = 1, .tdvs = 10, .tdvh = 1, 153 .tfs = 30, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, 154 .tsr = 7, .trfs = 10, .trp = 22, .tack = 3, .tss = 7, 155 }, 156 { .tcyc = 10, .t2cyc = 21, .tds = 2, .tdh = 1, .tdvs = 7, .tdvh = 1, 157 .tfs = 27, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, 158 .tsr = 4, .trfs = 10, .trp = 17, .tack = 3, .tss = 7, 159 }, 160 { .tcyc = 6, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1, 161 .tfs = 23, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, 162 .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7, 163 }, 164 { .tcyc = 7, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1, 165 .tfs = 15, .tli = 13, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, 166 .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7, 167 }, 168 { .tcyc = 2, .t2cyc = 5, .tds = 0, .tdh = 0, .tdvs = 1, .tdvh = 1, 169 .tfs = 16, .tli = 14, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, 170 .tsr = 2, .trfs = 7, .trp = 13, .tack = 2, .tss = 6, 171 }, 172 { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1, 173 .tfs = 12, .tli = 10, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, 174 .tsr = 3, .trfs = 7, .trp = 12, .tack = 3, .tss = 7, 175 }, 176 }; 177 178 /* ======================================================================== */ 179 180 /* Bit definitions inside the registers */ 181 #define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */ 182 #define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ 183 #define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */ 184 #define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */ 185 186 #define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */ 187 #define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */ 188 #define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */ 189 #define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */ 190 191 #define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */ 192 #define MPC52xx_ATA_FIFOSTAT_ERROR 0x40 /* FIFO Error */ 193 194 #define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */ 195 #define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */ 196 #define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */ 197 #define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */ 198 #define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */ 199 #define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */ 200 #define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */ 201 202 #define MAX_DMA_BUFFERS 128 203 #define MAX_DMA_BUFFER_SIZE 0x20000u 204 205 /* Structure of the hardware registers */ 206 struct mpc52xx_ata { 207 208 /* Host interface registers */ 209 u32 config; /* ATA + 0x00 Host configuration */ 210 u32 host_status; /* ATA + 0x04 Host controller status */ 211 u32 pio1; /* ATA + 0x08 PIO Timing 1 */ 212 u32 pio2; /* ATA + 0x0c PIO Timing 2 */ 213 u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */ 214 u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */ 215 u32 udma1; /* ATA + 0x18 UDMA Timing 1 */ 216 u32 udma2; /* ATA + 0x1c UDMA Timing 2 */ 217 u32 udma3; /* ATA + 0x20 UDMA Timing 3 */ 218 u32 udma4; /* ATA + 0x24 UDMA Timing 4 */ 219 u32 udma5; /* ATA + 0x28 UDMA Timing 5 */ 220 u32 share_cnt; /* ATA + 0x2c ATA share counter */ 221 u32 reserved0[3]; 222 223 /* FIFO registers */ 224 u32 fifo_data; /* ATA + 0x3c */ 225 u8 fifo_status_frame; /* ATA + 0x40 */ 226 u8 fifo_status; /* ATA + 0x41 */ 227 u16 reserved7[1]; 228 u8 fifo_control; /* ATA + 0x44 */ 229 u8 reserved8[5]; 230 u16 fifo_alarm; /* ATA + 0x4a */ 231 u16 reserved9; 232 u16 fifo_rdp; /* ATA + 0x4e */ 233 u16 reserved10; 234 u16 fifo_wrp; /* ATA + 0x52 */ 235 u16 reserved11; 236 u16 fifo_lfrdp; /* ATA + 0x56 */ 237 u16 reserved12; 238 u16 fifo_lfwrp; /* ATA + 0x5a */ 239 240 /* Drive TaskFile registers */ 241 u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */ 242 u8 reserved13[3]; 243 u16 tf_data; /* ATA + 0x60 TASKFILE Data */ 244 u16 reserved14; 245 u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */ 246 u8 reserved15[3]; 247 u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */ 248 u8 reserved16[3]; 249 u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */ 250 u8 reserved17[3]; 251 u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */ 252 u8 reserved18[3]; 253 u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */ 254 u8 reserved19[3]; 255 u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */ 256 u8 reserved20[3]; 257 u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */ 258 u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */ 259 u8 reserved21[2]; 260 }; 261 262 263 /* ======================================================================== */ 264 /* Aux fns */ 265 /* ======================================================================== */ 266 267 268 /* MPC52xx low level hw control */ 269 static int 270 mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio) 271 { 272 struct mpc52xx_ata_timings *timing = &priv->timings[dev]; 273 unsigned int ipb_period = priv->ipb_period; 274 u32 t0, t1, t2_8, t2_16, t2i, t4, ta; 275 276 if ((pio < 0) || (pio > 4)) 277 return -EINVAL; 278 279 t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]); 280 t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]); 281 t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]); 282 t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]); 283 t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]); 284 t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]); 285 ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]); 286 287 timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i); 288 timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8); 289 290 return 0; 291 } 292 293 static int 294 mpc52xx_ata_compute_mdma_timings(struct mpc52xx_ata_priv *priv, int dev, 295 int speed) 296 { 297 struct mpc52xx_ata_timings *t = &priv->timings[dev]; 298 const struct mdmaspec *s = &priv->mdmaspec[speed]; 299 300 if (speed < 0 || speed > 2) 301 return -EINVAL; 302 303 t->mdma1 = ((u32)s->t0M << 24) | ((u32)s->td << 16) | ((u32)s->tkw << 8) | s->tm; 304 t->mdma2 = ((u32)s->th << 24) | ((u32)s->tj << 16) | ((u32)s->tn << 8); 305 t->using_udma = 0; 306 307 return 0; 308 } 309 310 static int 311 mpc52xx_ata_compute_udma_timings(struct mpc52xx_ata_priv *priv, int dev, 312 int speed) 313 { 314 struct mpc52xx_ata_timings *t = &priv->timings[dev]; 315 const struct udmaspec *s = &priv->udmaspec[speed]; 316 317 if (speed < 0 || speed > 2) 318 return -EINVAL; 319 320 t->udma1 = ((u32)s->t2cyc << 24) | ((u32)s->tcyc << 16) | ((u32)s->tds << 8) | s->tdh; 321 t->udma2 = ((u32)s->tdvs << 24) | ((u32)s->tdvh << 16) | ((u32)s->tfs << 8) | s->tli; 322 t->udma3 = ((u32)s->tmli << 24) | ((u32)s->taz << 16) | ((u32)s->tenv << 8) | s->tsr; 323 t->udma4 = ((u32)s->tss << 24) | ((u32)s->trfs << 16) | ((u32)s->trp << 8) | s->tack; 324 t->udma5 = (u32)s->tzah << 24; 325 t->using_udma = 1; 326 327 return 0; 328 } 329 330 static void 331 mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device) 332 { 333 struct mpc52xx_ata __iomem *regs = priv->ata_regs; 334 struct mpc52xx_ata_timings *timing = &priv->timings[device]; 335 336 out_be32(®s->pio1, timing->pio1); 337 out_be32(®s->pio2, timing->pio2); 338 out_be32(®s->mdma1, timing->mdma1); 339 out_be32(®s->mdma2, timing->mdma2); 340 out_be32(®s->udma1, timing->udma1); 341 out_be32(®s->udma2, timing->udma2); 342 out_be32(®s->udma3, timing->udma3); 343 out_be32(®s->udma4, timing->udma4); 344 out_be32(®s->udma5, timing->udma5); 345 priv->csel = device; 346 } 347 348 static int 349 mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv) 350 { 351 struct mpc52xx_ata __iomem *regs = priv->ata_regs; 352 int tslot; 353 354 /* Clear share_cnt (all sample code do this ...) */ 355 out_be32(®s->share_cnt, 0); 356 357 /* Configure and reset host */ 358 out_be32(®s->config, 359 MPC52xx_ATA_HOSTCONF_IE | 360 MPC52xx_ATA_HOSTCONF_IORDY | 361 MPC52xx_ATA_HOSTCONF_SMR | 362 MPC52xx_ATA_HOSTCONF_FR); 363 364 udelay(10); 365 366 out_be32(®s->config, 367 MPC52xx_ATA_HOSTCONF_IE | 368 MPC52xx_ATA_HOSTCONF_IORDY); 369 370 /* Set the time slot to 1us */ 371 tslot = CALC_CLKCYC(priv->ipb_period, 1000000); 372 out_be32(®s->share_cnt, tslot << 16); 373 374 /* Init timings to PIO0 */ 375 memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings)); 376 377 mpc52xx_ata_compute_pio_timings(priv, 0, 0); 378 mpc52xx_ata_compute_pio_timings(priv, 1, 0); 379 380 mpc52xx_ata_apply_timings(priv, 0); 381 382 return 0; 383 } 384 385 386 /* ======================================================================== */ 387 /* libata driver */ 388 /* ======================================================================== */ 389 390 static void 391 mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev) 392 { 393 struct mpc52xx_ata_priv *priv = ap->host->private_data; 394 int pio, rv; 395 396 pio = adev->pio_mode - XFER_PIO_0; 397 398 rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio); 399 400 if (rv) { 401 dev_err(ap->dev, "error: invalid PIO mode: %d\n", pio); 402 return; 403 } 404 405 mpc52xx_ata_apply_timings(priv, adev->devno); 406 } 407 408 static void 409 mpc52xx_ata_set_dmamode(struct ata_port *ap, struct ata_device *adev) 410 { 411 struct mpc52xx_ata_priv *priv = ap->host->private_data; 412 int rv; 413 414 if (adev->dma_mode >= XFER_UDMA_0) { 415 int dma = adev->dma_mode - XFER_UDMA_0; 416 rv = mpc52xx_ata_compute_udma_timings(priv, adev->devno, dma); 417 } else { 418 int dma = adev->dma_mode - XFER_MW_DMA_0; 419 rv = mpc52xx_ata_compute_mdma_timings(priv, adev->devno, dma); 420 } 421 422 if (rv) { 423 dev_alert(ap->dev, 424 "Trying to select invalid DMA mode %d\n", 425 adev->dma_mode); 426 return; 427 } 428 429 mpc52xx_ata_apply_timings(priv, adev->devno); 430 } 431 432 static void 433 mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device) 434 { 435 struct mpc52xx_ata_priv *priv = ap->host->private_data; 436 437 if (device != priv->csel) 438 mpc52xx_ata_apply_timings(priv, device); 439 440 ata_sff_dev_select(ap, device); 441 } 442 443 static int 444 mpc52xx_ata_build_dmatable(struct ata_queued_cmd *qc) 445 { 446 struct ata_port *ap = qc->ap; 447 struct mpc52xx_ata_priv *priv = ap->host->private_data; 448 struct bcom_ata_bd *bd; 449 unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si; 450 struct scatterlist *sg; 451 int count = 0; 452 453 if (read) 454 bcom_ata_rx_prepare(priv->dmatsk); 455 else 456 bcom_ata_tx_prepare(priv->dmatsk); 457 458 for_each_sg(qc->sg, sg, qc->n_elem, si) { 459 dma_addr_t cur_addr = sg_dma_address(sg); 460 u32 cur_len = sg_dma_len(sg); 461 462 while (cur_len) { 463 unsigned int tc = min(cur_len, MAX_DMA_BUFFER_SIZE); 464 bd = (struct bcom_ata_bd *) 465 bcom_prepare_next_buffer(priv->dmatsk); 466 467 if (read) { 468 bd->status = tc; 469 bd->src_pa = (__force u32) priv->ata_regs_pa + 470 offsetof(struct mpc52xx_ata, fifo_data); 471 bd->dst_pa = (__force u32) cur_addr; 472 } else { 473 bd->status = tc; 474 bd->src_pa = (__force u32) cur_addr; 475 bd->dst_pa = (__force u32) priv->ata_regs_pa + 476 offsetof(struct mpc52xx_ata, fifo_data); 477 } 478 479 bcom_submit_next_buffer(priv->dmatsk, NULL); 480 481 cur_addr += tc; 482 cur_len -= tc; 483 count++; 484 485 if (count > MAX_DMA_BUFFERS) { 486 dev_alert(ap->dev, "dma table" 487 "too small\n"); 488 goto use_pio_instead; 489 } 490 } 491 } 492 return 1; 493 494 use_pio_instead: 495 bcom_ata_reset_bd(priv->dmatsk); 496 return 0; 497 } 498 499 static void 500 mpc52xx_bmdma_setup(struct ata_queued_cmd *qc) 501 { 502 struct ata_port *ap = qc->ap; 503 struct mpc52xx_ata_priv *priv = ap->host->private_data; 504 struct mpc52xx_ata __iomem *regs = priv->ata_regs; 505 506 unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE); 507 u8 dma_mode; 508 509 if (!mpc52xx_ata_build_dmatable(qc)) 510 dev_alert(ap->dev, "%s: %i, return 1?\n", 511 __func__, __LINE__); 512 513 /* Check FIFO is OK... */ 514 if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) 515 dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n", 516 __func__, in_8(&priv->ata_regs->fifo_status)); 517 518 if (read) { 519 dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_READ | 520 MPC52xx_ATA_DMAMODE_FE; 521 522 /* Setup FIFO if direction changed */ 523 if (priv->mpc52xx_ata_dma_last_write != 0) { 524 priv->mpc52xx_ata_dma_last_write = 0; 525 526 /* Configure FIFO with granularity to 7 */ 527 out_8(®s->fifo_control, 7); 528 out_be16(®s->fifo_alarm, 128); 529 530 /* Set FIFO Reset bit (FR) */ 531 out_8(®s->dma_mode, MPC52xx_ATA_DMAMODE_FR); 532 } 533 } else { 534 dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_WRITE; 535 536 /* Setup FIFO if direction changed */ 537 if (priv->mpc52xx_ata_dma_last_write != 1) { 538 priv->mpc52xx_ata_dma_last_write = 1; 539 540 /* Configure FIFO with granularity to 4 */ 541 out_8(®s->fifo_control, 4); 542 out_be16(®s->fifo_alarm, 128); 543 } 544 } 545 546 if (priv->timings[qc->dev->devno].using_udma) 547 dma_mode |= MPC52xx_ATA_DMAMODE_UDMA; 548 549 out_8(®s->dma_mode, dma_mode); 550 priv->waiting_for_dma = ATA_DMA_ACTIVE; 551 552 ata_wait_idle(ap); 553 ap->ops->sff_exec_command(ap, &qc->tf); 554 } 555 556 static void 557 mpc52xx_bmdma_start(struct ata_queued_cmd *qc) 558 { 559 struct ata_port *ap = qc->ap; 560 struct mpc52xx_ata_priv *priv = ap->host->private_data; 561 562 bcom_set_task_auto_start(priv->dmatsk->tasknum, priv->dmatsk->tasknum); 563 bcom_enable(priv->dmatsk); 564 } 565 566 static void 567 mpc52xx_bmdma_stop(struct ata_queued_cmd *qc) 568 { 569 struct ata_port *ap = qc->ap; 570 struct mpc52xx_ata_priv *priv = ap->host->private_data; 571 572 bcom_disable(priv->dmatsk); 573 bcom_ata_reset_bd(priv->dmatsk); 574 priv->waiting_for_dma = 0; 575 576 /* Check FIFO is OK... */ 577 if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) 578 dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n", 579 __func__, in_8(&priv->ata_regs->fifo_status)); 580 } 581 582 static u8 583 mpc52xx_bmdma_status(struct ata_port *ap) 584 { 585 struct mpc52xx_ata_priv *priv = ap->host->private_data; 586 587 /* Check FIFO is OK... */ 588 if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) { 589 dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n", 590 __func__, in_8(&priv->ata_regs->fifo_status)); 591 return priv->waiting_for_dma | ATA_DMA_ERR; 592 } 593 594 return priv->waiting_for_dma; 595 } 596 597 static irqreturn_t 598 mpc52xx_ata_task_irq(int irq, void *vpriv) 599 { 600 struct mpc52xx_ata_priv *priv = vpriv; 601 while (bcom_buffer_done(priv->dmatsk)) 602 bcom_retrieve_buffer(priv->dmatsk, NULL, NULL); 603 604 priv->waiting_for_dma |= ATA_DMA_INTR; 605 606 return IRQ_HANDLED; 607 } 608 609 static const struct scsi_host_template mpc52xx_ata_sht = { 610 ATA_PIO_SHT(DRV_NAME), 611 }; 612 613 static struct ata_port_operations mpc52xx_ata_port_ops = { 614 .inherits = &ata_bmdma_port_ops, 615 .sff_dev_select = mpc52xx_ata_dev_select, 616 .set_piomode = mpc52xx_ata_set_piomode, 617 .set_dmamode = mpc52xx_ata_set_dmamode, 618 .bmdma_setup = mpc52xx_bmdma_setup, 619 .bmdma_start = mpc52xx_bmdma_start, 620 .bmdma_stop = mpc52xx_bmdma_stop, 621 .bmdma_status = mpc52xx_bmdma_status, 622 .qc_prep = ata_noop_qc_prep, 623 }; 624 625 static int mpc52xx_ata_init_one(struct device *dev, 626 struct mpc52xx_ata_priv *priv, 627 unsigned long raw_ata_regs, 628 int mwdma_mask, int udma_mask) 629 { 630 struct ata_host *host; 631 struct ata_port *ap; 632 struct ata_ioports *aio; 633 634 host = ata_host_alloc(dev, 1); 635 if (!host) 636 return -ENOMEM; 637 638 ap = host->ports[0]; 639 ap->flags |= ATA_FLAG_SLAVE_POSS; 640 ap->pio_mask = ATA_PIO4; 641 ap->mwdma_mask = mwdma_mask; 642 ap->udma_mask = udma_mask; 643 ap->ops = &mpc52xx_ata_port_ops; 644 host->private_data = priv; 645 646 aio = &ap->ioaddr; 647 aio->cmd_addr = NULL; /* Don't have a classic reg block */ 648 aio->altstatus_addr = &priv->ata_regs->tf_control; 649 aio->ctl_addr = &priv->ata_regs->tf_control; 650 aio->data_addr = &priv->ata_regs->tf_data; 651 aio->error_addr = &priv->ata_regs->tf_features; 652 aio->feature_addr = &priv->ata_regs->tf_features; 653 aio->nsect_addr = &priv->ata_regs->tf_sec_count; 654 aio->lbal_addr = &priv->ata_regs->tf_sec_num; 655 aio->lbam_addr = &priv->ata_regs->tf_cyl_low; 656 aio->lbah_addr = &priv->ata_regs->tf_cyl_high; 657 aio->device_addr = &priv->ata_regs->tf_dev_head; 658 aio->status_addr = &priv->ata_regs->tf_command; 659 aio->command_addr = &priv->ata_regs->tf_command; 660 661 ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs); 662 663 /* activate host */ 664 return ata_host_activate(host, priv->ata_irq, ata_bmdma_interrupt, 0, 665 &mpc52xx_ata_sht); 666 } 667 668 /* ======================================================================== */ 669 /* OF Platform driver */ 670 /* ======================================================================== */ 671 672 static int mpc52xx_ata_probe(struct platform_device *op) 673 { 674 unsigned int ipb_freq; 675 struct resource res_mem; 676 int ata_irq = 0; 677 struct mpc52xx_ata __iomem *ata_regs; 678 struct mpc52xx_ata_priv *priv = NULL; 679 int rv, task_irq; 680 int mwdma_mask = 0, udma_mask = 0; 681 const __be32 *prop; 682 int proplen; 683 struct bcom_task *dmatsk; 684 685 /* Get ipb frequency */ 686 ipb_freq = mpc5xxx_get_bus_frequency(&op->dev); 687 if (!ipb_freq) { 688 dev_err(&op->dev, "could not determine IPB bus frequency\n"); 689 return -ENODEV; 690 } 691 692 /* Get device base address from device tree, request the region 693 * and ioremap it. */ 694 rv = of_address_to_resource(op->dev.of_node, 0, &res_mem); 695 if (rv) { 696 dev_err(&op->dev, "could not determine device base address\n"); 697 return rv; 698 } 699 700 if (!devm_request_mem_region(&op->dev, res_mem.start, 701 sizeof(*ata_regs), DRV_NAME)) { 702 dev_err(&op->dev, "error requesting register region\n"); 703 return -EBUSY; 704 } 705 706 ata_regs = devm_ioremap(&op->dev, res_mem.start, sizeof(*ata_regs)); 707 if (!ata_regs) { 708 dev_err(&op->dev, "error mapping device registers\n"); 709 return -ENOMEM; 710 } 711 712 /* 713 * By default, all DMA modes are disabled for the MPC5200. Some 714 * boards don't have the required signals routed to make DMA work. 715 * Also, the MPC5200B has a silicon bug that causes data corruption 716 * with UDMA if it is used at the same time as the LocalPlus bus. 717 * 718 * Instead of trying to guess what modes are usable, check the 719 * ATA device tree node to find out what DMA modes work on the board. 720 * UDMA/MWDMA modes can also be forced by adding "libata.force=<mode>" 721 * to the kernel boot parameters. 722 * 723 * The MPC5200 ATA controller supports MWDMA modes 0, 1 and 2 and 724 * UDMA modes 0, 1 and 2. 725 */ 726 prop = of_get_property(op->dev.of_node, "mwdma-mode", &proplen); 727 if ((prop) && (proplen >= 4)) 728 mwdma_mask = ATA_MWDMA2 & ((1 << (*prop + 1)) - 1); 729 prop = of_get_property(op->dev.of_node, "udma-mode", &proplen); 730 if ((prop) && (proplen >= 4)) 731 udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1); 732 733 ata_irq = irq_of_parse_and_map(op->dev.of_node, 0); 734 if (!ata_irq) { 735 dev_err(&op->dev, "error mapping irq\n"); 736 return -EINVAL; 737 } 738 739 /* Prepare our private structure */ 740 priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_KERNEL); 741 if (!priv) { 742 rv = -ENOMEM; 743 goto err1; 744 } 745 746 priv->ipb_period = 1000000000 / (ipb_freq / 1000); 747 priv->ata_regs = ata_regs; 748 priv->ata_regs_pa = res_mem.start; 749 priv->ata_irq = ata_irq; 750 priv->csel = -1; 751 priv->mpc52xx_ata_dma_last_write = -1; 752 753 if (ipb_freq/1000000 == 66) { 754 priv->mdmaspec = mdmaspec66; 755 priv->udmaspec = udmaspec66; 756 } else { 757 priv->mdmaspec = mdmaspec132; 758 priv->udmaspec = udmaspec132; 759 } 760 761 /* Allocate a BestComm task for DMA */ 762 dmatsk = bcom_ata_init(MAX_DMA_BUFFERS, MAX_DMA_BUFFER_SIZE); 763 if (!dmatsk) { 764 dev_err(&op->dev, "bestcomm initialization failed\n"); 765 rv = -ENOMEM; 766 goto err1; 767 } 768 769 task_irq = bcom_get_task_irq(dmatsk); 770 rv = devm_request_irq(&op->dev, task_irq, &mpc52xx_ata_task_irq, 0, 771 "ATA task", priv); 772 if (rv) { 773 dev_err(&op->dev, "error requesting DMA IRQ\n"); 774 goto err2; 775 } 776 priv->dmatsk = dmatsk; 777 778 /* Init the hw */ 779 rv = mpc52xx_ata_hw_init(priv); 780 if (rv) { 781 dev_err(&op->dev, "error initializing hardware\n"); 782 goto err2; 783 } 784 785 /* Register ourselves to libata */ 786 rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start, 787 mwdma_mask, udma_mask); 788 if (rv) { 789 dev_err(&op->dev, "error registering with ATA layer\n"); 790 goto err2; 791 } 792 793 return 0; 794 795 err2: 796 irq_dispose_mapping(task_irq); 797 bcom_ata_release(dmatsk); 798 err1: 799 irq_dispose_mapping(ata_irq); 800 return rv; 801 } 802 803 static int 804 mpc52xx_ata_remove(struct platform_device *op) 805 { 806 struct ata_host *host = platform_get_drvdata(op); 807 struct mpc52xx_ata_priv *priv = host->private_data; 808 int task_irq; 809 810 /* Deregister the ATA interface */ 811 ata_platform_remove_one(op); 812 813 /* Clean up DMA */ 814 task_irq = bcom_get_task_irq(priv->dmatsk); 815 irq_dispose_mapping(task_irq); 816 bcom_ata_release(priv->dmatsk); 817 irq_dispose_mapping(priv->ata_irq); 818 819 return 0; 820 } 821 822 #ifdef CONFIG_PM_SLEEP 823 static int 824 mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state) 825 { 826 struct ata_host *host = platform_get_drvdata(op); 827 828 ata_host_suspend(host, state); 829 return 0; 830 } 831 832 static int 833 mpc52xx_ata_resume(struct platform_device *op) 834 { 835 struct ata_host *host = platform_get_drvdata(op); 836 struct mpc52xx_ata_priv *priv = host->private_data; 837 int rv; 838 839 rv = mpc52xx_ata_hw_init(priv); 840 if (rv) { 841 dev_err(host->dev, "error initializing hardware\n"); 842 return rv; 843 } 844 845 ata_host_resume(host); 846 847 return 0; 848 } 849 #endif 850 851 static const struct of_device_id mpc52xx_ata_of_match[] = { 852 { .compatible = "fsl,mpc5200-ata", }, 853 { .compatible = "mpc5200-ata", }, 854 { /* sentinel */ } 855 }; 856 857 858 static struct platform_driver mpc52xx_ata_of_platform_driver = { 859 .probe = mpc52xx_ata_probe, 860 .remove = mpc52xx_ata_remove, 861 #ifdef CONFIG_PM_SLEEP 862 .suspend = mpc52xx_ata_suspend, 863 .resume = mpc52xx_ata_resume, 864 #endif 865 .driver = { 866 .name = DRV_NAME, 867 .of_match_table = mpc52xx_ata_of_match, 868 }, 869 }; 870 871 module_platform_driver(mpc52xx_ata_of_platform_driver); 872 873 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); 874 MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver"); 875 MODULE_LICENSE("GPL"); 876 MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match); 877 878