1 /* 2 * pata-legacy.c - Legacy port PATA/SATA controller driver. 3 * Copyright 2005/2006 Red Hat, all rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; see the file COPYING. If not, write to 17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * An ATA driver for the legacy ATA ports. 20 * 21 * Data Sources: 22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 23 * HT6560 series: 24 * Promise 20230/20620: 25 * http://www.ryston.cz/petr/vlb/pdc20230b.html 26 * http://www.ryston.cz/petr/vlb/pdc20230c.html 27 * http://www.ryston.cz/petr/vlb/pdc20630.html 28 * QDI65x0: 29 * http://www.ryston.cz/petr/vlb/qd6500.html 30 * http://www.ryston.cz/petr/vlb/qd6580.html 31 * 32 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c 33 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by 34 * Samuel Thibault <samuel.thibault@ens-lyon.org> 35 * 36 * Unsupported but docs exist: 37 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 38 * 39 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 40 * on PC class systems. There are three hybrid devices that are exceptions 41 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 42 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 43 * 44 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 45 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A 46 * 47 * Support for the Winbond 83759A when operating in advanced mode. 48 * Multichip mode is not currently supported. 49 * 50 * Use the autospeed and pio_mask options with: 51 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 52 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 53 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 54 * Winbond W83759A, Promise PDC20230-B 55 * 56 * For now use autospeed and pio_mask as above with the W83759A. This may 57 * change. 58 * 59 */ 60 61 #include <linux/async.h> 62 #include <linux/kernel.h> 63 #include <linux/module.h> 64 #include <linux/pci.h> 65 #include <linux/init.h> 66 #include <linux/blkdev.h> 67 #include <linux/delay.h> 68 #include <scsi/scsi_host.h> 69 #include <linux/ata.h> 70 #include <linux/libata.h> 71 #include <linux/platform_device.h> 72 73 #define DRV_NAME "pata_legacy" 74 #define DRV_VERSION "0.6.5" 75 76 #define NR_HOST 6 77 78 static int all; 79 module_param(all, int, 0444); 80 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); 81 82 struct legacy_data { 83 unsigned long timing; 84 u8 clock[2]; 85 u8 last; 86 int fast; 87 struct platform_device *platform_dev; 88 89 }; 90 91 enum controller { 92 BIOS = 0, 93 SNOOP = 1, 94 PDC20230 = 2, 95 HT6560A = 3, 96 HT6560B = 4, 97 OPTI611A = 5, 98 OPTI46X = 6, 99 QDI6500 = 7, 100 QDI6580 = 8, 101 QDI6580DP = 9, /* Dual channel mode is different */ 102 W83759A = 10, 103 104 UNKNOWN = -1 105 }; 106 107 108 struct legacy_probe { 109 unsigned char *name; 110 unsigned long port; 111 unsigned int irq; 112 unsigned int slot; 113 enum controller type; 114 unsigned long private; 115 }; 116 117 struct legacy_controller { 118 const char *name; 119 struct ata_port_operations *ops; 120 unsigned int pio_mask; 121 unsigned int flags; 122 unsigned int pflags; 123 int (*setup)(struct platform_device *, struct legacy_probe *probe, 124 struct legacy_data *data); 125 }; 126 127 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 128 129 static struct legacy_probe probe_list[NR_HOST]; 130 static struct legacy_data legacy_data[NR_HOST]; 131 static struct ata_host *legacy_host[NR_HOST]; 132 static int nr_legacy_host; 133 134 135 static int probe_all; /* Set to check all ISA port ranges */ 136 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ 137 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ 138 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ 139 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ 140 static int qdi; /* Set to probe QDI controllers */ 141 static int autospeed; /* Chip present which snoops speed changes */ 142 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */ 143 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ 144 145 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE 146 static int winbond = 1; /* Set to probe Winbond controllers, 147 give I/O port if non standard */ 148 #else 149 static int winbond; /* Set to probe Winbond controllers, 150 give I/O port if non standard */ 151 #endif 152 153 /** 154 * legacy_probe_add - Add interface to probe list 155 * @port: Controller port 156 * @irq: IRQ number 157 * @type: Controller type 158 * @private: Controller specific info 159 * 160 * Add an entry into the probe list for ATA controllers. This is used 161 * to add the default ISA slots and then to build up the table 162 * further according to other ISA/VLB/Weird device scans 163 * 164 * An I/O port list is used to keep ordering stable and sane, as we 165 * don't have any good way to talk about ordering otherwise 166 */ 167 168 static int legacy_probe_add(unsigned long port, unsigned int irq, 169 enum controller type, unsigned long private) 170 { 171 struct legacy_probe *lp = &probe_list[0]; 172 int i; 173 struct legacy_probe *free = NULL; 174 175 for (i = 0; i < NR_HOST; i++) { 176 if (lp->port == 0 && free == NULL) 177 free = lp; 178 /* Matching port, or the correct slot for ordering */ 179 if (lp->port == port || legacy_port[i] == port) { 180 free = lp; 181 break; 182 } 183 lp++; 184 } 185 if (free == NULL) { 186 printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); 187 return -1; 188 } 189 /* Fill in the entry for later probing */ 190 free->port = port; 191 free->irq = irq; 192 free->type = type; 193 free->private = private; 194 return 0; 195 } 196 197 198 /** 199 * legacy_set_mode - mode setting 200 * @link: IDE link 201 * @unused: Device that failed when error is returned 202 * 203 * Use a non standard set_mode function. We don't want to be tuned. 204 * 205 * The BIOS configured everything. Our job is not to fiddle. Just use 206 * whatever PIO the hardware is using and leave it at that. When we 207 * get some kind of nice user driven API for control then we can 208 * expand on this as per hdparm in the base kernel. 209 */ 210 211 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) 212 { 213 struct ata_device *dev; 214 215 ata_for_each_dev(dev, link, ENABLED) { 216 ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); 217 dev->pio_mode = XFER_PIO_0; 218 dev->xfer_mode = XFER_PIO_0; 219 dev->xfer_shift = ATA_SHIFT_PIO; 220 dev->flags |= ATA_DFLAG_PIO; 221 } 222 return 0; 223 } 224 225 static struct scsi_host_template legacy_sht = { 226 ATA_PIO_SHT(DRV_NAME), 227 }; 228 229 static const struct ata_port_operations legacy_base_port_ops = { 230 .inherits = &ata_sff_port_ops, 231 .cable_detect = ata_cable_40wire, 232 }; 233 234 /* 235 * These ops are used if the user indicates the hardware 236 * snoops the commands to decide on the mode and handles the 237 * mode selection "magically" itself. Several legacy controllers 238 * do this. The mode range can be set if it is not 0x1F by setting 239 * pio_mask as well. 240 */ 241 242 static struct ata_port_operations simple_port_ops = { 243 .inherits = &legacy_base_port_ops, 244 .sff_data_xfer = ata_sff_data_xfer_noirq, 245 }; 246 247 static struct ata_port_operations legacy_port_ops = { 248 .inherits = &legacy_base_port_ops, 249 .sff_data_xfer = ata_sff_data_xfer_noirq, 250 .set_mode = legacy_set_mode, 251 }; 252 253 /* 254 * Promise 20230C and 20620 support 255 * 256 * This controller supports PIO0 to PIO2. We set PIO timings 257 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA 258 * support is weird being DMA to controller and PIO'd to the host 259 * and not supported. 260 */ 261 262 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 263 { 264 int tries = 5; 265 int pio = adev->pio_mode - XFER_PIO_0; 266 u8 rt; 267 unsigned long flags; 268 269 /* Safe as UP only. Force I/Os to occur together */ 270 271 local_irq_save(flags); 272 273 /* Unlock the control interface */ 274 do { 275 inb(0x1F5); 276 outb(inb(0x1F2) | 0x80, 0x1F2); 277 inb(0x1F2); 278 inb(0x3F6); 279 inb(0x3F6); 280 inb(0x1F2); 281 inb(0x1F2); 282 } 283 while ((inb(0x1F2) & 0x80) && --tries); 284 285 local_irq_restore(flags); 286 287 outb(inb(0x1F4) & 0x07, 0x1F4); 288 289 rt = inb(0x1F3); 290 rt &= 0x07 << (3 * adev->devno); 291 if (pio) 292 rt |= (1 + 3 * pio) << (3 * adev->devno); 293 294 udelay(100); 295 outb(inb(0x1F2) | 0x01, 0x1F2); 296 udelay(100); 297 inb(0x1F5); 298 299 } 300 301 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev, 302 unsigned char *buf, unsigned int buflen, int rw) 303 { 304 int slop = buflen & 3; 305 struct ata_port *ap = dev->link->ap; 306 307 /* 32bit I/O capable *and* we need to write a whole number of dwords */ 308 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) 309 && (ap->pflags & ATA_PFLAG_PIO32)) { 310 unsigned long flags; 311 312 local_irq_save(flags); 313 314 /* Perform the 32bit I/O synchronization sequence */ 315 ioread8(ap->ioaddr.nsect_addr); 316 ioread8(ap->ioaddr.nsect_addr); 317 ioread8(ap->ioaddr.nsect_addr); 318 319 /* Now the data */ 320 if (rw == READ) 321 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 322 else 323 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 324 325 if (unlikely(slop)) { 326 __le32 pad; 327 if (rw == READ) { 328 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 329 memcpy(buf + buflen - slop, &pad, slop); 330 } else { 331 memcpy(&pad, buf + buflen - slop, slop); 332 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 333 } 334 buflen += 4 - slop; 335 } 336 local_irq_restore(flags); 337 } else 338 buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw); 339 340 return buflen; 341 } 342 343 static struct ata_port_operations pdc20230_port_ops = { 344 .inherits = &legacy_base_port_ops, 345 .set_piomode = pdc20230_set_piomode, 346 .sff_data_xfer = pdc_data_xfer_vlb, 347 }; 348 349 /* 350 * Holtek 6560A support 351 * 352 * This controller supports PIO0 to PIO2 (no IORDY even though higher 353 * timings can be loaded). 354 */ 355 356 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 357 { 358 u8 active, recover; 359 struct ata_timing t; 360 361 /* Get the timing data in cycles. For now play safe at 50Mhz */ 362 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 363 364 active = clamp_val(t.active, 2, 15); 365 recover = clamp_val(t.recover, 4, 15); 366 367 inb(0x3E6); 368 inb(0x3E6); 369 inb(0x3E6); 370 inb(0x3E6); 371 372 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 373 ioread8(ap->ioaddr.status_addr); 374 } 375 376 static struct ata_port_operations ht6560a_port_ops = { 377 .inherits = &legacy_base_port_ops, 378 .set_piomode = ht6560a_set_piomode, 379 }; 380 381 /* 382 * Holtek 6560B support 383 * 384 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO 385 * setting unless we see an ATAPI device in which case we force it off. 386 * 387 * FIXME: need to implement 2nd channel support. 388 */ 389 390 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 391 { 392 u8 active, recover; 393 struct ata_timing t; 394 395 /* Get the timing data in cycles. For now play safe at 50Mhz */ 396 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 397 398 active = clamp_val(t.active, 2, 15); 399 recover = clamp_val(t.recover, 2, 16); 400 recover &= 0x15; 401 402 inb(0x3E6); 403 inb(0x3E6); 404 inb(0x3E6); 405 inb(0x3E6); 406 407 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 408 409 if (adev->class != ATA_DEV_ATA) { 410 u8 rconf = inb(0x3E6); 411 if (rconf & 0x24) { 412 rconf &= ~0x24; 413 outb(rconf, 0x3E6); 414 } 415 } 416 ioread8(ap->ioaddr.status_addr); 417 } 418 419 static struct ata_port_operations ht6560b_port_ops = { 420 .inherits = &legacy_base_port_ops, 421 .set_piomode = ht6560b_set_piomode, 422 }; 423 424 /* 425 * Opti core chipset helpers 426 */ 427 428 /** 429 * opti_syscfg - read OPTI chipset configuration 430 * @reg: Configuration register to read 431 * 432 * Returns the value of an OPTI system board configuration register. 433 */ 434 435 static u8 opti_syscfg(u8 reg) 436 { 437 unsigned long flags; 438 u8 r; 439 440 /* Uniprocessor chipset and must force cycles adjancent */ 441 local_irq_save(flags); 442 outb(reg, 0x22); 443 r = inb(0x24); 444 local_irq_restore(flags); 445 return r; 446 } 447 448 /* 449 * Opti 82C611A 450 * 451 * This controller supports PIO0 to PIO3. 452 */ 453 454 static void opti82c611a_set_piomode(struct ata_port *ap, 455 struct ata_device *adev) 456 { 457 u8 active, recover, setup; 458 struct ata_timing t; 459 struct ata_device *pair = ata_dev_pair(adev); 460 int clock; 461 int khz[4] = { 50000, 40000, 33000, 25000 }; 462 u8 rc; 463 464 /* Enter configuration mode */ 465 ioread16(ap->ioaddr.error_addr); 466 ioread16(ap->ioaddr.error_addr); 467 iowrite8(3, ap->ioaddr.nsect_addr); 468 469 /* Read VLB clock strapping */ 470 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 471 472 /* Get the timing data in cycles */ 473 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 474 475 /* Setup timing is shared */ 476 if (pair) { 477 struct ata_timing tp; 478 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 479 480 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 481 } 482 483 active = clamp_val(t.active, 2, 17) - 2; 484 recover = clamp_val(t.recover, 1, 16) - 1; 485 setup = clamp_val(t.setup, 1, 4) - 1; 486 487 /* Select the right timing bank for write timing */ 488 rc = ioread8(ap->ioaddr.lbal_addr); 489 rc &= 0x7F; 490 rc |= (adev->devno << 7); 491 iowrite8(rc, ap->ioaddr.lbal_addr); 492 493 /* Write the timings */ 494 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 495 496 /* Select the right bank for read timings, also 497 load the shared timings for address */ 498 rc = ioread8(ap->ioaddr.device_addr); 499 rc &= 0xC0; 500 rc |= adev->devno; /* Index select */ 501 rc |= (setup << 4) | 0x04; 502 iowrite8(rc, ap->ioaddr.device_addr); 503 504 /* Load the read timings */ 505 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 506 507 /* Ensure the timing register mode is right */ 508 rc = ioread8(ap->ioaddr.lbal_addr); 509 rc &= 0x73; 510 rc |= 0x84; 511 iowrite8(rc, ap->ioaddr.lbal_addr); 512 513 /* Exit command mode */ 514 iowrite8(0x83, ap->ioaddr.nsect_addr); 515 } 516 517 518 static struct ata_port_operations opti82c611a_port_ops = { 519 .inherits = &legacy_base_port_ops, 520 .set_piomode = opti82c611a_set_piomode, 521 }; 522 523 /* 524 * Opti 82C465MV 525 * 526 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 527 * version is dual channel but doesn't have a lot of unique registers. 528 */ 529 530 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 531 { 532 u8 active, recover, setup; 533 struct ata_timing t; 534 struct ata_device *pair = ata_dev_pair(adev); 535 int clock; 536 int khz[4] = { 50000, 40000, 33000, 25000 }; 537 u8 rc; 538 u8 sysclk; 539 540 /* Get the clock */ 541 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ 542 543 /* Enter configuration mode */ 544 ioread16(ap->ioaddr.error_addr); 545 ioread16(ap->ioaddr.error_addr); 546 iowrite8(3, ap->ioaddr.nsect_addr); 547 548 /* Read VLB clock strapping */ 549 clock = 1000000000 / khz[sysclk]; 550 551 /* Get the timing data in cycles */ 552 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 553 554 /* Setup timing is shared */ 555 if (pair) { 556 struct ata_timing tp; 557 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 558 559 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 560 } 561 562 active = clamp_val(t.active, 2, 17) - 2; 563 recover = clamp_val(t.recover, 1, 16) - 1; 564 setup = clamp_val(t.setup, 1, 4) - 1; 565 566 /* Select the right timing bank for write timing */ 567 rc = ioread8(ap->ioaddr.lbal_addr); 568 rc &= 0x7F; 569 rc |= (adev->devno << 7); 570 iowrite8(rc, ap->ioaddr.lbal_addr); 571 572 /* Write the timings */ 573 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 574 575 /* Select the right bank for read timings, also 576 load the shared timings for address */ 577 rc = ioread8(ap->ioaddr.device_addr); 578 rc &= 0xC0; 579 rc |= adev->devno; /* Index select */ 580 rc |= (setup << 4) | 0x04; 581 iowrite8(rc, ap->ioaddr.device_addr); 582 583 /* Load the read timings */ 584 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 585 586 /* Ensure the timing register mode is right */ 587 rc = ioread8(ap->ioaddr.lbal_addr); 588 rc &= 0x73; 589 rc |= 0x84; 590 iowrite8(rc, ap->ioaddr.lbal_addr); 591 592 /* Exit command mode */ 593 iowrite8(0x83, ap->ioaddr.nsect_addr); 594 595 /* We need to know this for quad device on the MVB */ 596 ap->host->private_data = ap; 597 } 598 599 /** 600 * opt82c465mv_qc_issue - command issue 601 * @qc: command pending 602 * 603 * Called when the libata layer is about to issue a command. We wrap 604 * this interface so that we can load the correct ATA timings. The 605 * MVB has a single set of timing registers and these are shared 606 * across channels. As there are two registers we really ought to 607 * track the last two used values as a sort of register window. For 608 * now we just reload on a channel switch. On the single channel 609 * setup this condition never fires so we do nothing extra. 610 * 611 * FIXME: dual channel needs ->serialize support 612 */ 613 614 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) 615 { 616 struct ata_port *ap = qc->ap; 617 struct ata_device *adev = qc->dev; 618 619 /* If timings are set and for the wrong channel (2nd test is 620 due to a libata shortcoming and will eventually go I hope) */ 621 if (ap->host->private_data != ap->host 622 && ap->host->private_data != NULL) 623 opti82c46x_set_piomode(ap, adev); 624 625 return ata_sff_qc_issue(qc); 626 } 627 628 static struct ata_port_operations opti82c46x_port_ops = { 629 .inherits = &legacy_base_port_ops, 630 .set_piomode = opti82c46x_set_piomode, 631 .qc_issue = opti82c46x_qc_issue, 632 }; 633 634 static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev) 635 { 636 struct ata_timing t; 637 struct legacy_data *ld_qdi = ap->host->private_data; 638 int active, recovery; 639 u8 timing; 640 641 /* Get the timing data in cycles */ 642 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 643 644 if (ld_qdi->fast) { 645 active = 8 - clamp_val(t.active, 1, 8); 646 recovery = 18 - clamp_val(t.recover, 3, 18); 647 } else { 648 active = 9 - clamp_val(t.active, 2, 9); 649 recovery = 15 - clamp_val(t.recover, 0, 15); 650 } 651 timing = (recovery << 4) | active | 0x08; 652 653 ld_qdi->clock[adev->devno] = timing; 654 655 outb(timing, ld_qdi->timing); 656 } 657 658 /** 659 * qdi6580dp_set_piomode - PIO setup for dual channel 660 * @ap: Port 661 * @adev: Device 662 * 663 * In dual channel mode the 6580 has one clock per channel and we have 664 * to software clockswitch in qc_issue. 665 */ 666 667 static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev) 668 { 669 struct ata_timing t; 670 struct legacy_data *ld_qdi = ap->host->private_data; 671 int active, recovery; 672 u8 timing; 673 674 /* Get the timing data in cycles */ 675 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 676 677 if (ld_qdi->fast) { 678 active = 8 - clamp_val(t.active, 1, 8); 679 recovery = 18 - clamp_val(t.recover, 3, 18); 680 } else { 681 active = 9 - clamp_val(t.active, 2, 9); 682 recovery = 15 - clamp_val(t.recover, 0, 15); 683 } 684 timing = (recovery << 4) | active | 0x08; 685 686 ld_qdi->clock[adev->devno] = timing; 687 688 outb(timing, ld_qdi->timing + 2 * ap->port_no); 689 /* Clear the FIFO */ 690 if (adev->class != ATA_DEV_ATA) 691 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); 692 } 693 694 /** 695 * qdi6580_set_piomode - PIO setup for single channel 696 * @ap: Port 697 * @adev: Device 698 * 699 * In single channel mode the 6580 has one clock per device and we can 700 * avoid the requirement to clock switch. We also have to load the timing 701 * into the right clock according to whether we are master or slave. 702 */ 703 704 static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev) 705 { 706 struct ata_timing t; 707 struct legacy_data *ld_qdi = ap->host->private_data; 708 int active, recovery; 709 u8 timing; 710 711 /* Get the timing data in cycles */ 712 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 713 714 if (ld_qdi->fast) { 715 active = 8 - clamp_val(t.active, 1, 8); 716 recovery = 18 - clamp_val(t.recover, 3, 18); 717 } else { 718 active = 9 - clamp_val(t.active, 2, 9); 719 recovery = 15 - clamp_val(t.recover, 0, 15); 720 } 721 timing = (recovery << 4) | active | 0x08; 722 ld_qdi->clock[adev->devno] = timing; 723 outb(timing, ld_qdi->timing + 2 * adev->devno); 724 /* Clear the FIFO */ 725 if (adev->class != ATA_DEV_ATA) 726 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); 727 } 728 729 /** 730 * qdi_qc_issue - command issue 731 * @qc: command pending 732 * 733 * Called when the libata layer is about to issue a command. We wrap 734 * this interface so that we can load the correct ATA timings. 735 */ 736 737 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) 738 { 739 struct ata_port *ap = qc->ap; 740 struct ata_device *adev = qc->dev; 741 struct legacy_data *ld_qdi = ap->host->private_data; 742 743 if (ld_qdi->clock[adev->devno] != ld_qdi->last) { 744 if (adev->pio_mode) { 745 ld_qdi->last = ld_qdi->clock[adev->devno]; 746 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + 747 2 * ap->port_no); 748 } 749 } 750 return ata_sff_qc_issue(qc); 751 } 752 753 static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf, 754 unsigned int buflen, int rw) 755 { 756 struct ata_port *ap = adev->link->ap; 757 int slop = buflen & 3; 758 759 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) 760 && (ap->pflags & ATA_PFLAG_PIO32)) { 761 if (rw == WRITE) 762 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 763 else 764 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 765 766 if (unlikely(slop)) { 767 __le32 pad; 768 if (rw == WRITE) { 769 memcpy(&pad, buf + buflen - slop, slop); 770 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 771 } else { 772 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 773 memcpy(buf + buflen - slop, &pad, slop); 774 } 775 } 776 return (buflen + 3) & ~3; 777 } else 778 return ata_sff_data_xfer(adev, buf, buflen, rw); 779 } 780 781 static int qdi_port(struct platform_device *dev, 782 struct legacy_probe *lp, struct legacy_data *ld) 783 { 784 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) 785 return -EBUSY; 786 ld->timing = lp->private; 787 return 0; 788 } 789 790 static struct ata_port_operations qdi6500_port_ops = { 791 .inherits = &legacy_base_port_ops, 792 .set_piomode = qdi6500_set_piomode, 793 .qc_issue = qdi_qc_issue, 794 .sff_data_xfer = vlb32_data_xfer, 795 }; 796 797 static struct ata_port_operations qdi6580_port_ops = { 798 .inherits = &legacy_base_port_ops, 799 .set_piomode = qdi6580_set_piomode, 800 .sff_data_xfer = vlb32_data_xfer, 801 }; 802 803 static struct ata_port_operations qdi6580dp_port_ops = { 804 .inherits = &legacy_base_port_ops, 805 .set_piomode = qdi6580dp_set_piomode, 806 .qc_issue = qdi_qc_issue, 807 .sff_data_xfer = vlb32_data_xfer, 808 }; 809 810 static DEFINE_SPINLOCK(winbond_lock); 811 812 static void winbond_writecfg(unsigned long port, u8 reg, u8 val) 813 { 814 unsigned long flags; 815 spin_lock_irqsave(&winbond_lock, flags); 816 outb(reg, port + 0x01); 817 outb(val, port + 0x02); 818 spin_unlock_irqrestore(&winbond_lock, flags); 819 } 820 821 static u8 winbond_readcfg(unsigned long port, u8 reg) 822 { 823 u8 val; 824 825 unsigned long flags; 826 spin_lock_irqsave(&winbond_lock, flags); 827 outb(reg, port + 0x01); 828 val = inb(port + 0x02); 829 spin_unlock_irqrestore(&winbond_lock, flags); 830 831 return val; 832 } 833 834 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) 835 { 836 struct ata_timing t; 837 struct legacy_data *ld_winbond = ap->host->private_data; 838 int active, recovery; 839 u8 reg; 840 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); 841 842 reg = winbond_readcfg(ld_winbond->timing, 0x81); 843 844 /* Get the timing data in cycles */ 845 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ 846 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 847 else 848 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 849 850 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; 851 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; 852 timing = (active << 4) | recovery; 853 winbond_writecfg(ld_winbond->timing, timing, reg); 854 855 /* Load the setup timing */ 856 857 reg = 0x35; 858 if (adev->class != ATA_DEV_ATA) 859 reg |= 0x08; /* FIFO off */ 860 if (!ata_pio_need_iordy(adev)) 861 reg |= 0x02; /* IORDY off */ 862 reg |= (clamp_val(t.setup, 0, 3) << 6); 863 winbond_writecfg(ld_winbond->timing, timing + 1, reg); 864 } 865 866 static int winbond_port(struct platform_device *dev, 867 struct legacy_probe *lp, struct legacy_data *ld) 868 { 869 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) 870 return -EBUSY; 871 ld->timing = lp->private; 872 return 0; 873 } 874 875 static struct ata_port_operations winbond_port_ops = { 876 .inherits = &legacy_base_port_ops, 877 .set_piomode = winbond_set_piomode, 878 .sff_data_xfer = vlb32_data_xfer, 879 }; 880 881 static struct legacy_controller controllers[] = { 882 {"BIOS", &legacy_port_ops, 0x1F, 883 ATA_FLAG_NO_IORDY, 0, NULL }, 884 {"Snooping", &simple_port_ops, 0x1F, 885 0, 0, NULL }, 886 {"PDC20230", &pdc20230_port_ops, 0x7, 887 ATA_FLAG_NO_IORDY, 888 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, 889 {"HT6560A", &ht6560a_port_ops, 0x07, 890 ATA_FLAG_NO_IORDY, 0, NULL }, 891 {"HT6560B", &ht6560b_port_ops, 0x1F, 892 ATA_FLAG_NO_IORDY, 0, NULL }, 893 {"OPTI82C611A", &opti82c611a_port_ops, 0x0F, 894 0, 0, NULL }, 895 {"OPTI82C46X", &opti82c46x_port_ops, 0x0F, 896 0, 0, NULL }, 897 {"QDI6500", &qdi6500_port_ops, 0x07, 898 ATA_FLAG_NO_IORDY, 899 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 900 {"QDI6580", &qdi6580_port_ops, 0x1F, 901 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 902 {"QDI6580DP", &qdi6580dp_port_ops, 0x1F, 903 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 904 {"W83759A", &winbond_port_ops, 0x1F, 905 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, 906 winbond_port } 907 }; 908 909 /** 910 * probe_chip_type - Discover controller 911 * @probe: Probe entry to check 912 * 913 * Probe an ATA port and identify the type of controller. We don't 914 * check if the controller appears to be driveless at this point. 915 */ 916 917 static __init int probe_chip_type(struct legacy_probe *probe) 918 { 919 int mask = 1 << probe->slot; 920 921 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { 922 u8 reg = winbond_readcfg(winbond, 0x81); 923 reg |= 0x80; /* jumpered mode off */ 924 winbond_writecfg(winbond, 0x81, reg); 925 reg = winbond_readcfg(winbond, 0x83); 926 reg |= 0xF0; /* local control */ 927 winbond_writecfg(winbond, 0x83, reg); 928 reg = winbond_readcfg(winbond, 0x85); 929 reg |= 0xF0; /* programmable timing */ 930 winbond_writecfg(winbond, 0x85, reg); 931 932 reg = winbond_readcfg(winbond, 0x81); 933 934 if (reg & mask) 935 return W83759A; 936 } 937 if (probe->port == 0x1F0) { 938 unsigned long flags; 939 local_irq_save(flags); 940 /* Probes */ 941 outb(inb(0x1F2) | 0x80, 0x1F2); 942 inb(0x1F5); 943 inb(0x1F2); 944 inb(0x3F6); 945 inb(0x3F6); 946 inb(0x1F2); 947 inb(0x1F2); 948 949 if ((inb(0x1F2) & 0x80) == 0) { 950 /* PDC20230c or 20630 ? */ 951 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" 952 " detected.\n"); 953 udelay(100); 954 inb(0x1F5); 955 local_irq_restore(flags); 956 return PDC20230; 957 } else { 958 outb(0x55, 0x1F2); 959 inb(0x1F2); 960 inb(0x1F2); 961 if (inb(0x1F2) == 0x00) 962 printk(KERN_INFO "PDC20230-B VLB ATA " 963 "controller detected.\n"); 964 local_irq_restore(flags); 965 return BIOS; 966 } 967 local_irq_restore(flags); 968 } 969 970 if (ht6560a & mask) 971 return HT6560A; 972 if (ht6560b & mask) 973 return HT6560B; 974 if (opti82c611a & mask) 975 return OPTI611A; 976 if (opti82c46x & mask) 977 return OPTI46X; 978 if (autospeed & mask) 979 return SNOOP; 980 return BIOS; 981 } 982 983 984 /** 985 * legacy_init_one - attach a legacy interface 986 * @pl: probe record 987 * 988 * Register an ISA bus IDE interface. Such interfaces are PIO and we 989 * assume do not support IRQ sharing. 990 */ 991 992 static __init int legacy_init_one(struct legacy_probe *probe) 993 { 994 struct legacy_controller *controller = &controllers[probe->type]; 995 int pio_modes = controller->pio_mask; 996 unsigned long io = probe->port; 997 u32 mask = (1 << probe->slot); 998 struct ata_port_operations *ops = controller->ops; 999 struct legacy_data *ld = &legacy_data[probe->slot]; 1000 struct ata_host *host = NULL; 1001 struct ata_port *ap; 1002 struct platform_device *pdev; 1003 struct ata_device *dev; 1004 void __iomem *io_addr, *ctrl_addr; 1005 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 1006 int ret; 1007 1008 iordy |= controller->flags; 1009 1010 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); 1011 if (IS_ERR(pdev)) 1012 return PTR_ERR(pdev); 1013 1014 ret = -EBUSY; 1015 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 1016 devm_request_region(&pdev->dev, io + 0x0206, 1, 1017 "pata_legacy") == NULL) 1018 goto fail; 1019 1020 ret = -ENOMEM; 1021 io_addr = devm_ioport_map(&pdev->dev, io, 8); 1022 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); 1023 if (!io_addr || !ctrl_addr) 1024 goto fail; 1025 if (controller->setup) 1026 if (controller->setup(pdev, probe, ld) < 0) 1027 goto fail; 1028 host = ata_host_alloc(&pdev->dev, 1); 1029 if (!host) 1030 goto fail; 1031 ap = host->ports[0]; 1032 1033 ap->ops = ops; 1034 ap->pio_mask = pio_modes; 1035 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 1036 ap->pflags |= controller->pflags; 1037 ap->ioaddr.cmd_addr = io_addr; 1038 ap->ioaddr.altstatus_addr = ctrl_addr; 1039 ap->ioaddr.ctl_addr = ctrl_addr; 1040 ata_sff_std_ports(&ap->ioaddr); 1041 ap->host->private_data = ld; 1042 1043 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); 1044 1045 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, 1046 &legacy_sht); 1047 if (ret) 1048 goto fail; 1049 async_synchronize_full(); 1050 ld->platform_dev = pdev; 1051 1052 /* Nothing found means we drop the port as its probably not there */ 1053 1054 ret = -ENODEV; 1055 ata_for_each_dev(dev, &ap->link, ALL) { 1056 if (!ata_dev_absent(dev)) { 1057 legacy_host[probe->slot] = host; 1058 ld->platform_dev = pdev; 1059 return 0; 1060 } 1061 } 1062 ata_host_detach(host); 1063 fail: 1064 platform_device_unregister(pdev); 1065 return ret; 1066 } 1067 1068 /** 1069 * legacy_check_special_cases - ATA special cases 1070 * @p: PCI device to check 1071 * @master: set this if we find an ATA master 1072 * @master: set this if we find an ATA secondary 1073 * 1074 * A small number of vendors implemented early PCI ATA interfaces 1075 * on bridge logic without the ATA interface being PCI visible. 1076 * Where we have a matching PCI driver we must skip the relevant 1077 * device here. If we don't know about it then the legacy driver 1078 * is the right driver anyway. 1079 */ 1080 1081 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, 1082 int *secondary) 1083 { 1084 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 1085 if (p->vendor == 0x1078 && p->device == 0x0000) { 1086 *primary = *secondary = 1; 1087 return; 1088 } 1089 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 1090 if (p->vendor == 0x1078 && p->device == 0x0002) { 1091 *primary = *secondary = 1; 1092 return; 1093 } 1094 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 1095 if (p->vendor == 0x8086 && p->device == 0x1234) { 1096 u16 r; 1097 pci_read_config_word(p, 0x6C, &r); 1098 if (r & 0x8000) { 1099 /* ATA port enabled */ 1100 if (r & 0x4000) 1101 *secondary = 1; 1102 else 1103 *primary = 1; 1104 } 1105 return; 1106 } 1107 } 1108 1109 static __init void probe_opti_vlb(void) 1110 { 1111 /* If an OPTI 82C46X is present find out where the channels are */ 1112 static const char *optis[4] = { 1113 "3/463MV", "5MV", 1114 "5MVA", "5MVB" 1115 }; 1116 u8 chans = 1; 1117 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 1118 1119 opti82c46x = 3; /* Assume master and slave first */ 1120 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", 1121 optis[ctrl]); 1122 if (ctrl == 3) 1123 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 1124 ctrl = opti_syscfg(0xAC); 1125 /* Check enabled and this port is the 465MV port. On the 1126 MVB we may have two channels */ 1127 if (ctrl & 8) { 1128 if (chans == 2) { 1129 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1130 legacy_probe_add(0x170, 15, OPTI46X, 0); 1131 } 1132 if (ctrl & 4) 1133 legacy_probe_add(0x170, 15, OPTI46X, 0); 1134 else 1135 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1136 } else 1137 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1138 } 1139 1140 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) 1141 { 1142 static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; 1143 /* Check card type */ 1144 if ((r & 0xF0) == 0xC0) { 1145 /* QD6500: single channel */ 1146 if (r & 8) 1147 /* Disabled ? */ 1148 return; 1149 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1150 QDI6500, port); 1151 } 1152 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { 1153 /* QD6580: dual channel */ 1154 if (!request_region(port + 2 , 2, "pata_qdi")) { 1155 release_region(port, 2); 1156 return; 1157 } 1158 res = inb(port + 3); 1159 /* Single channel mode ? */ 1160 if (res & 1) 1161 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1162 QDI6580, port); 1163 else { /* Dual channel mode */ 1164 legacy_probe_add(0x1F0, 14, QDI6580DP, port); 1165 /* port + 0x02, r & 0x04 */ 1166 legacy_probe_add(0x170, 15, QDI6580DP, port + 2); 1167 } 1168 release_region(port + 2, 2); 1169 } 1170 } 1171 1172 static __init void probe_qdi_vlb(void) 1173 { 1174 unsigned long flags; 1175 static const unsigned long qd_port[2] = { 0x30, 0xB0 }; 1176 int i; 1177 1178 /* 1179 * Check each possible QD65xx base address 1180 */ 1181 1182 for (i = 0; i < 2; i++) { 1183 unsigned long port = qd_port[i]; 1184 u8 r, res; 1185 1186 1187 if (request_region(port, 2, "pata_qdi")) { 1188 /* Check for a card */ 1189 local_irq_save(flags); 1190 /* I have no h/w that needs this delay but it 1191 is present in the historic code */ 1192 r = inb(port); 1193 udelay(1); 1194 outb(0x19, port); 1195 udelay(1); 1196 res = inb(port); 1197 udelay(1); 1198 outb(r, port); 1199 udelay(1); 1200 local_irq_restore(flags); 1201 1202 /* Fail */ 1203 if (res == 0x19) { 1204 release_region(port, 2); 1205 continue; 1206 } 1207 /* Passes the presence test */ 1208 r = inb(port + 1); 1209 udelay(1); 1210 /* Check port agrees with port set */ 1211 if ((r & 2) >> 1 == i) 1212 qdi65_identify_port(r, res, port); 1213 release_region(port, 2); 1214 } 1215 } 1216 } 1217 1218 /** 1219 * legacy_init - attach legacy interfaces 1220 * 1221 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 1222 * Right now we do not scan the ide0 and ide1 address but should do so 1223 * for non PCI systems or systems with no PCI IDE legacy mode devices. 1224 * If you fix that note there are special cases to consider like VLB 1225 * drivers and CS5510/20. 1226 */ 1227 1228 static __init int legacy_init(void) 1229 { 1230 int i; 1231 int ct = 0; 1232 int primary = 0; 1233 int secondary = 0; 1234 int pci_present = 0; 1235 struct legacy_probe *pl = &probe_list[0]; 1236 int slot = 0; 1237 1238 struct pci_dev *p = NULL; 1239 1240 for_each_pci_dev(p) { 1241 int r; 1242 /* Check for any overlap of the system ATA mappings. Native 1243 mode controllers stuck on these addresses or some devices 1244 in 'raid' mode won't be found by the storage class test */ 1245 for (r = 0; r < 6; r++) { 1246 if (pci_resource_start(p, r) == 0x1f0) 1247 primary = 1; 1248 if (pci_resource_start(p, r) == 0x170) 1249 secondary = 1; 1250 } 1251 /* Check for special cases */ 1252 legacy_check_special_cases(p, &primary, &secondary); 1253 1254 /* If PCI bus is present then don't probe for tertiary 1255 legacy ports */ 1256 pci_present = 1; 1257 } 1258 1259 if (winbond == 1) 1260 winbond = 0x130; /* Default port, alt is 1B0 */ 1261 1262 if (primary == 0 || all) 1263 legacy_probe_add(0x1F0, 14, UNKNOWN, 0); 1264 if (secondary == 0 || all) 1265 legacy_probe_add(0x170, 15, UNKNOWN, 0); 1266 1267 if (probe_all || !pci_present) { 1268 /* ISA/VLB extra ports */ 1269 legacy_probe_add(0x1E8, 11, UNKNOWN, 0); 1270 legacy_probe_add(0x168, 10, UNKNOWN, 0); 1271 legacy_probe_add(0x1E0, 8, UNKNOWN, 0); 1272 legacy_probe_add(0x160, 12, UNKNOWN, 0); 1273 } 1274 1275 if (opti82c46x) 1276 probe_opti_vlb(); 1277 if (qdi) 1278 probe_qdi_vlb(); 1279 1280 for (i = 0; i < NR_HOST; i++, pl++) { 1281 if (pl->port == 0) 1282 continue; 1283 if (pl->type == UNKNOWN) 1284 pl->type = probe_chip_type(pl); 1285 pl->slot = slot++; 1286 if (legacy_init_one(pl) == 0) 1287 ct++; 1288 } 1289 if (ct != 0) 1290 return 0; 1291 return -ENODEV; 1292 } 1293 1294 static __exit void legacy_exit(void) 1295 { 1296 int i; 1297 1298 for (i = 0; i < nr_legacy_host; i++) { 1299 struct legacy_data *ld = &legacy_data[i]; 1300 ata_host_detach(legacy_host[i]); 1301 platform_device_unregister(ld->platform_dev); 1302 } 1303 } 1304 1305 MODULE_AUTHOR("Alan Cox"); 1306 MODULE_DESCRIPTION("low-level driver for legacy ATA"); 1307 MODULE_LICENSE("GPL"); 1308 MODULE_VERSION(DRV_VERSION); 1309 MODULE_ALIAS("pata_winbond"); 1310 1311 module_param(probe_all, int, 0); 1312 module_param(autospeed, int, 0); 1313 module_param(ht6560a, int, 0); 1314 module_param(ht6560b, int, 0); 1315 module_param(opti82c611a, int, 0); 1316 module_param(opti82c46x, int, 0); 1317 module_param(qdi, int, 0); 1318 module_param(winbond, int, 0); 1319 module_param(pio_mask, int, 0); 1320 module_param(iordy_mask, int, 0); 1321 1322 module_init(legacy_init); 1323 module_exit(legacy_exit); 1324