1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pata-legacy.c - Legacy port PATA/SATA controller driver. 4 * Copyright 2005/2006 Red Hat, all rights reserved. 5 * 6 * An ATA driver for the legacy ATA ports. 7 * 8 * Data Sources: 9 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 10 * HT6560 series: 11 * Promise 20230/20620: 12 * http://www.ryston.cz/petr/vlb/pdc20230b.html 13 * http://www.ryston.cz/petr/vlb/pdc20230c.html 14 * http://www.ryston.cz/petr/vlb/pdc20630.html 15 * QDI65x0: 16 * http://www.ryston.cz/petr/vlb/qd6500.html 17 * http://www.ryston.cz/petr/vlb/qd6580.html 18 * 19 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c 20 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by 21 * Samuel Thibault <samuel.thibault@ens-lyon.org> 22 * 23 * Unsupported but docs exist: 24 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 25 * 26 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 27 * on PC class systems. There are three hybrid devices that are exceptions 28 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 29 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 30 * 31 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 32 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A 33 * 34 * Support for the Winbond 83759A when operating in advanced mode. 35 * Multichip mode is not currently supported. 36 * 37 * Use the autospeed and pio_mask options with: 38 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 39 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 40 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 41 * Winbond W83759A, Promise PDC20230-B 42 * 43 * For now use autospeed and pio_mask as above with the W83759A. This may 44 * change. 45 */ 46 47 #include <linux/async.h> 48 #include <linux/kernel.h> 49 #include <linux/module.h> 50 #include <linux/pci.h> 51 #include <linux/init.h> 52 #include <linux/blkdev.h> 53 #include <linux/delay.h> 54 #include <scsi/scsi_host.h> 55 #include <linux/ata.h> 56 #include <linux/libata.h> 57 #include <linux/platform_device.h> 58 59 #define DRV_NAME "pata_legacy" 60 #define DRV_VERSION "0.6.5" 61 62 #define NR_HOST 6 63 64 static int all; 65 module_param(all, int, 0444); 66 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); 67 68 enum controller { 69 BIOS = 0, 70 SNOOP = 1, 71 PDC20230 = 2, 72 HT6560A = 3, 73 HT6560B = 4, 74 OPTI611A = 5, 75 OPTI46X = 6, 76 QDI6500 = 7, 77 QDI6580 = 8, 78 QDI6580DP = 9, /* Dual channel mode is different */ 79 W83759A = 10, 80 81 UNKNOWN = -1 82 }; 83 84 struct legacy_data { 85 unsigned long timing; 86 u8 clock[2]; 87 u8 last; 88 int fast; 89 enum controller type; 90 struct platform_device *platform_dev; 91 }; 92 93 struct legacy_probe { 94 unsigned char *name; 95 unsigned long port; 96 unsigned int irq; 97 unsigned int slot; 98 enum controller type; 99 unsigned long private; 100 }; 101 102 struct legacy_controller { 103 const char *name; 104 struct ata_port_operations *ops; 105 unsigned int pio_mask; 106 unsigned int flags; 107 unsigned int pflags; 108 int (*setup)(struct platform_device *, struct legacy_probe *probe, 109 struct legacy_data *data); 110 }; 111 112 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 113 114 static struct legacy_probe probe_list[NR_HOST]; 115 static struct legacy_data legacy_data[NR_HOST]; 116 static struct ata_host *legacy_host[NR_HOST]; 117 static int nr_legacy_host; 118 119 120 static int probe_all; /* Set to check all ISA port ranges */ 121 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ 122 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ 123 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ 124 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ 125 static int autospeed; /* Chip present which snoops speed changes */ 126 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */ 127 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ 128 129 /* Set to probe QDI controllers */ 130 #ifdef CONFIG_PATA_QDI_MODULE 131 static int qdi = 1; 132 #else 133 static int qdi; 134 #endif 135 136 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE 137 static int winbond = 1; /* Set to probe Winbond controllers, 138 give I/O port if non standard */ 139 #else 140 static int winbond; /* Set to probe Winbond controllers, 141 give I/O port if non standard */ 142 #endif 143 144 /** 145 * legacy_probe_add - Add interface to probe list 146 * @port: Controller port 147 * @irq: IRQ number 148 * @type: Controller type 149 * @private: Controller specific info 150 * 151 * Add an entry into the probe list for ATA controllers. This is used 152 * to add the default ISA slots and then to build up the table 153 * further according to other ISA/VLB/Weird device scans 154 * 155 * An I/O port list is used to keep ordering stable and sane, as we 156 * don't have any good way to talk about ordering otherwise 157 */ 158 159 static int legacy_probe_add(unsigned long port, unsigned int irq, 160 enum controller type, unsigned long private) 161 { 162 struct legacy_probe *lp = &probe_list[0]; 163 int i; 164 struct legacy_probe *free = NULL; 165 166 for (i = 0; i < NR_HOST; i++) { 167 if (lp->port == 0 && free == NULL) 168 free = lp; 169 /* Matching port, or the correct slot for ordering */ 170 if (lp->port == port || legacy_port[i] == port) { 171 free = lp; 172 break; 173 } 174 lp++; 175 } 176 if (free == NULL) { 177 printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); 178 return -1; 179 } 180 /* Fill in the entry for later probing */ 181 free->port = port; 182 free->irq = irq; 183 free->type = type; 184 free->private = private; 185 return 0; 186 } 187 188 189 /** 190 * legacy_set_mode - mode setting 191 * @link: IDE link 192 * @unused: Device that failed when error is returned 193 * 194 * Use a non standard set_mode function. We don't want to be tuned. 195 * 196 * The BIOS configured everything. Our job is not to fiddle. Just use 197 * whatever PIO the hardware is using and leave it at that. When we 198 * get some kind of nice user driven API for control then we can 199 * expand on this as per hdparm in the base kernel. 200 */ 201 202 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) 203 { 204 struct ata_device *dev; 205 206 ata_for_each_dev(dev, link, ENABLED) { 207 ata_dev_info(dev, "configured for PIO\n"); 208 dev->pio_mode = XFER_PIO_0; 209 dev->xfer_mode = XFER_PIO_0; 210 dev->xfer_shift = ATA_SHIFT_PIO; 211 dev->flags |= ATA_DFLAG_PIO; 212 } 213 return 0; 214 } 215 216 static struct scsi_host_template legacy_sht = { 217 ATA_PIO_SHT(DRV_NAME), 218 }; 219 220 static const struct ata_port_operations legacy_base_port_ops = { 221 .inherits = &ata_sff_port_ops, 222 .cable_detect = ata_cable_40wire, 223 }; 224 225 /* 226 * These ops are used if the user indicates the hardware 227 * snoops the commands to decide on the mode and handles the 228 * mode selection "magically" itself. Several legacy controllers 229 * do this. The mode range can be set if it is not 0x1F by setting 230 * pio_mask as well. 231 */ 232 233 static struct ata_port_operations simple_port_ops = { 234 .inherits = &legacy_base_port_ops, 235 .sff_data_xfer = ata_sff_data_xfer32, 236 }; 237 238 static struct ata_port_operations legacy_port_ops = { 239 .inherits = &legacy_base_port_ops, 240 .sff_data_xfer = ata_sff_data_xfer32, 241 .set_mode = legacy_set_mode, 242 }; 243 244 /* 245 * Promise 20230C and 20620 support 246 * 247 * This controller supports PIO0 to PIO2. We set PIO timings 248 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA 249 * support is weird being DMA to controller and PIO'd to the host 250 * and not supported. 251 */ 252 253 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 254 { 255 int tries = 5; 256 int pio = adev->pio_mode - XFER_PIO_0; 257 u8 rt; 258 unsigned long flags; 259 260 /* Safe as UP only. Force I/Os to occur together */ 261 262 local_irq_save(flags); 263 264 /* Unlock the control interface */ 265 do { 266 inb(0x1F5); 267 outb(inb(0x1F2) | 0x80, 0x1F2); 268 inb(0x1F2); 269 inb(0x3F6); 270 inb(0x3F6); 271 inb(0x1F2); 272 inb(0x1F2); 273 } 274 while ((inb(0x1F2) & 0x80) && --tries); 275 276 local_irq_restore(flags); 277 278 outb(inb(0x1F4) & 0x07, 0x1F4); 279 280 rt = inb(0x1F3); 281 rt &= 0x07 << (3 * adev->devno); 282 if (pio) 283 rt |= (1 + 3 * pio) << (3 * adev->devno); 284 285 udelay(100); 286 outb(inb(0x1F2) | 0x01, 0x1F2); 287 udelay(100); 288 inb(0x1F5); 289 290 } 291 292 static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, 293 unsigned char *buf, unsigned int buflen, int rw) 294 { 295 struct ata_device *dev = qc->dev; 296 struct ata_port *ap = dev->link->ap; 297 int slop = buflen & 3; 298 299 /* 32bit I/O capable *and* we need to write a whole number of dwords */ 300 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) 301 && (ap->pflags & ATA_PFLAG_PIO32)) { 302 unsigned long flags; 303 304 local_irq_save(flags); 305 306 /* Perform the 32bit I/O synchronization sequence */ 307 ioread8(ap->ioaddr.nsect_addr); 308 ioread8(ap->ioaddr.nsect_addr); 309 ioread8(ap->ioaddr.nsect_addr); 310 311 /* Now the data */ 312 if (rw == READ) 313 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 314 else 315 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 316 317 if (unlikely(slop)) { 318 __le32 pad; 319 if (rw == READ) { 320 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 321 memcpy(buf + buflen - slop, &pad, slop); 322 } else { 323 memcpy(&pad, buf + buflen - slop, slop); 324 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 325 } 326 buflen += 4 - slop; 327 } 328 local_irq_restore(flags); 329 } else 330 buflen = ata_sff_data_xfer32(qc, buf, buflen, rw); 331 332 return buflen; 333 } 334 335 static struct ata_port_operations pdc20230_port_ops = { 336 .inherits = &legacy_base_port_ops, 337 .set_piomode = pdc20230_set_piomode, 338 .sff_data_xfer = pdc_data_xfer_vlb, 339 }; 340 341 /* 342 * Holtek 6560A support 343 * 344 * This controller supports PIO0 to PIO2 (no IORDY even though higher 345 * timings can be loaded). 346 */ 347 348 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 349 { 350 u8 active, recover; 351 struct ata_timing t; 352 353 /* Get the timing data in cycles. For now play safe at 50Mhz */ 354 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 355 356 active = clamp_val(t.active, 2, 15); 357 recover = clamp_val(t.recover, 4, 15); 358 359 inb(0x3E6); 360 inb(0x3E6); 361 inb(0x3E6); 362 inb(0x3E6); 363 364 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 365 ioread8(ap->ioaddr.status_addr); 366 } 367 368 static struct ata_port_operations ht6560a_port_ops = { 369 .inherits = &legacy_base_port_ops, 370 .set_piomode = ht6560a_set_piomode, 371 }; 372 373 /* 374 * Holtek 6560B support 375 * 376 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO 377 * setting unless we see an ATAPI device in which case we force it off. 378 * 379 * FIXME: need to implement 2nd channel support. 380 */ 381 382 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 383 { 384 u8 active, recover; 385 struct ata_timing t; 386 387 /* Get the timing data in cycles. For now play safe at 50Mhz */ 388 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 389 390 active = clamp_val(t.active, 2, 15); 391 recover = clamp_val(t.recover, 2, 16) & 0x0F; 392 393 inb(0x3E6); 394 inb(0x3E6); 395 inb(0x3E6); 396 inb(0x3E6); 397 398 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 399 400 if (adev->class != ATA_DEV_ATA) { 401 u8 rconf = inb(0x3E6); 402 if (rconf & 0x24) { 403 rconf &= ~0x24; 404 outb(rconf, 0x3E6); 405 } 406 } 407 ioread8(ap->ioaddr.status_addr); 408 } 409 410 static struct ata_port_operations ht6560b_port_ops = { 411 .inherits = &legacy_base_port_ops, 412 .set_piomode = ht6560b_set_piomode, 413 }; 414 415 /* 416 * Opti core chipset helpers 417 */ 418 419 /** 420 * opti_syscfg - read OPTI chipset configuration 421 * @reg: Configuration register to read 422 * 423 * Returns the value of an OPTI system board configuration register. 424 */ 425 426 static u8 opti_syscfg(u8 reg) 427 { 428 unsigned long flags; 429 u8 r; 430 431 /* Uniprocessor chipset and must force cycles adjancent */ 432 local_irq_save(flags); 433 outb(reg, 0x22); 434 r = inb(0x24); 435 local_irq_restore(flags); 436 return r; 437 } 438 439 /* 440 * Opti 82C611A 441 * 442 * This controller supports PIO0 to PIO3. 443 */ 444 445 static void opti82c611a_set_piomode(struct ata_port *ap, 446 struct ata_device *adev) 447 { 448 u8 active, recover, setup; 449 struct ata_timing t; 450 struct ata_device *pair = ata_dev_pair(adev); 451 int clock; 452 int khz[4] = { 50000, 40000, 33000, 25000 }; 453 u8 rc; 454 455 /* Enter configuration mode */ 456 ioread16(ap->ioaddr.error_addr); 457 ioread16(ap->ioaddr.error_addr); 458 iowrite8(3, ap->ioaddr.nsect_addr); 459 460 /* Read VLB clock strapping */ 461 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 462 463 /* Get the timing data in cycles */ 464 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 465 466 /* Setup timing is shared */ 467 if (pair) { 468 struct ata_timing tp; 469 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 470 471 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 472 } 473 474 active = clamp_val(t.active, 2, 17) - 2; 475 recover = clamp_val(t.recover, 1, 16) - 1; 476 setup = clamp_val(t.setup, 1, 4) - 1; 477 478 /* Select the right timing bank for write timing */ 479 rc = ioread8(ap->ioaddr.lbal_addr); 480 rc &= 0x7F; 481 rc |= (adev->devno << 7); 482 iowrite8(rc, ap->ioaddr.lbal_addr); 483 484 /* Write the timings */ 485 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 486 487 /* Select the right bank for read timings, also 488 load the shared timings for address */ 489 rc = ioread8(ap->ioaddr.device_addr); 490 rc &= 0xC0; 491 rc |= adev->devno; /* Index select */ 492 rc |= (setup << 4) | 0x04; 493 iowrite8(rc, ap->ioaddr.device_addr); 494 495 /* Load the read timings */ 496 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 497 498 /* Ensure the timing register mode is right */ 499 rc = ioread8(ap->ioaddr.lbal_addr); 500 rc &= 0x73; 501 rc |= 0x84; 502 iowrite8(rc, ap->ioaddr.lbal_addr); 503 504 /* Exit command mode */ 505 iowrite8(0x83, ap->ioaddr.nsect_addr); 506 } 507 508 509 static struct ata_port_operations opti82c611a_port_ops = { 510 .inherits = &legacy_base_port_ops, 511 .set_piomode = opti82c611a_set_piomode, 512 }; 513 514 /* 515 * Opti 82C465MV 516 * 517 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 518 * version is dual channel but doesn't have a lot of unique registers. 519 */ 520 521 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 522 { 523 u8 active, recover, setup; 524 struct ata_timing t; 525 struct ata_device *pair = ata_dev_pair(adev); 526 int clock; 527 int khz[4] = { 50000, 40000, 33000, 25000 }; 528 u8 rc; 529 u8 sysclk; 530 531 /* Get the clock */ 532 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */ 533 534 /* Enter configuration mode */ 535 ioread16(ap->ioaddr.error_addr); 536 ioread16(ap->ioaddr.error_addr); 537 iowrite8(3, ap->ioaddr.nsect_addr); 538 539 /* Read VLB clock strapping */ 540 clock = 1000000000 / khz[sysclk]; 541 542 /* Get the timing data in cycles */ 543 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 544 545 /* Setup timing is shared */ 546 if (pair) { 547 struct ata_timing tp; 548 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 549 550 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 551 } 552 553 active = clamp_val(t.active, 2, 17) - 2; 554 recover = clamp_val(t.recover, 1, 16) - 1; 555 setup = clamp_val(t.setup, 1, 4) - 1; 556 557 /* Select the right timing bank for write timing */ 558 rc = ioread8(ap->ioaddr.lbal_addr); 559 rc &= 0x7F; 560 rc |= (adev->devno << 7); 561 iowrite8(rc, ap->ioaddr.lbal_addr); 562 563 /* Write the timings */ 564 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 565 566 /* Select the right bank for read timings, also 567 load the shared timings for address */ 568 rc = ioread8(ap->ioaddr.device_addr); 569 rc &= 0xC0; 570 rc |= adev->devno; /* Index select */ 571 rc |= (setup << 4) | 0x04; 572 iowrite8(rc, ap->ioaddr.device_addr); 573 574 /* Load the read timings */ 575 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 576 577 /* Ensure the timing register mode is right */ 578 rc = ioread8(ap->ioaddr.lbal_addr); 579 rc &= 0x73; 580 rc |= 0x84; 581 iowrite8(rc, ap->ioaddr.lbal_addr); 582 583 /* Exit command mode */ 584 iowrite8(0x83, ap->ioaddr.nsect_addr); 585 586 /* We need to know this for quad device on the MVB */ 587 ap->host->private_data = ap; 588 } 589 590 /** 591 * opt82c465mv_qc_issue - command issue 592 * @qc: command pending 593 * 594 * Called when the libata layer is about to issue a command. We wrap 595 * this interface so that we can load the correct ATA timings. The 596 * MVB has a single set of timing registers and these are shared 597 * across channels. As there are two registers we really ought to 598 * track the last two used values as a sort of register window. For 599 * now we just reload on a channel switch. On the single channel 600 * setup this condition never fires so we do nothing extra. 601 * 602 * FIXME: dual channel needs ->serialize support 603 */ 604 605 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) 606 { 607 struct ata_port *ap = qc->ap; 608 struct ata_device *adev = qc->dev; 609 610 /* If timings are set and for the wrong channel (2nd test is 611 due to a libata shortcoming and will eventually go I hope) */ 612 if (ap->host->private_data != ap->host 613 && ap->host->private_data != NULL) 614 opti82c46x_set_piomode(ap, adev); 615 616 return ata_sff_qc_issue(qc); 617 } 618 619 static struct ata_port_operations opti82c46x_port_ops = { 620 .inherits = &legacy_base_port_ops, 621 .set_piomode = opti82c46x_set_piomode, 622 .qc_issue = opti82c46x_qc_issue, 623 }; 624 625 /** 626 * qdi65x0_set_piomode - PIO setup for QDI65x0 627 * @ap: Port 628 * @adev: Device 629 * 630 * In single channel mode the 6580 has one clock per device and we can 631 * avoid the requirement to clock switch. We also have to load the timing 632 * into the right clock according to whether we are master or slave. 633 * 634 * In dual channel mode the 6580 has one clock per channel and we have 635 * to software clockswitch in qc_issue. 636 */ 637 638 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) 639 { 640 struct ata_timing t; 641 struct legacy_data *ld_qdi = ap->host->private_data; 642 int active, recovery; 643 u8 timing; 644 645 /* Get the timing data in cycles */ 646 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 647 648 if (ld_qdi->fast) { 649 active = 8 - clamp_val(t.active, 1, 8); 650 recovery = 18 - clamp_val(t.recover, 3, 18); 651 } else { 652 active = 9 - clamp_val(t.active, 2, 9); 653 recovery = 15 - clamp_val(t.recover, 0, 15); 654 } 655 timing = (recovery << 4) | active | 0x08; 656 ld_qdi->clock[adev->devno] = timing; 657 658 if (ld_qdi->type == QDI6580) 659 outb(timing, ld_qdi->timing + 2 * adev->devno); 660 else 661 outb(timing, ld_qdi->timing + 2 * ap->port_no); 662 663 /* Clear the FIFO */ 664 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) 665 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); 666 } 667 668 /** 669 * qdi_qc_issue - command issue 670 * @qc: command pending 671 * 672 * Called when the libata layer is about to issue a command. We wrap 673 * this interface so that we can load the correct ATA timings. 674 */ 675 676 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) 677 { 678 struct ata_port *ap = qc->ap; 679 struct ata_device *adev = qc->dev; 680 struct legacy_data *ld_qdi = ap->host->private_data; 681 682 if (ld_qdi->clock[adev->devno] != ld_qdi->last) { 683 if (adev->pio_mode) { 684 ld_qdi->last = ld_qdi->clock[adev->devno]; 685 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + 686 2 * ap->port_no); 687 } 688 } 689 return ata_sff_qc_issue(qc); 690 } 691 692 static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, 693 unsigned char *buf, 694 unsigned int buflen, int rw) 695 { 696 struct ata_device *adev = qc->dev; 697 struct ata_port *ap = adev->link->ap; 698 int slop = buflen & 3; 699 700 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) 701 && (ap->pflags & ATA_PFLAG_PIO32)) { 702 if (rw == WRITE) 703 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 704 else 705 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 706 707 if (unlikely(slop)) { 708 __le32 pad; 709 if (rw == WRITE) { 710 memcpy(&pad, buf + buflen - slop, slop); 711 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 712 } else { 713 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 714 memcpy(buf + buflen - slop, &pad, slop); 715 } 716 } 717 return (buflen + 3) & ~3; 718 } else 719 return ata_sff_data_xfer(qc, buf, buflen, rw); 720 } 721 722 static int qdi_port(struct platform_device *dev, 723 struct legacy_probe *lp, struct legacy_data *ld) 724 { 725 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) 726 return -EBUSY; 727 ld->timing = lp->private; 728 return 0; 729 } 730 731 static struct ata_port_operations qdi6500_port_ops = { 732 .inherits = &legacy_base_port_ops, 733 .set_piomode = qdi65x0_set_piomode, 734 .qc_issue = qdi_qc_issue, 735 .sff_data_xfer = vlb32_data_xfer, 736 }; 737 738 static struct ata_port_operations qdi6580_port_ops = { 739 .inherits = &legacy_base_port_ops, 740 .set_piomode = qdi65x0_set_piomode, 741 .sff_data_xfer = vlb32_data_xfer, 742 }; 743 744 static struct ata_port_operations qdi6580dp_port_ops = { 745 .inherits = &legacy_base_port_ops, 746 .set_piomode = qdi65x0_set_piomode, 747 .qc_issue = qdi_qc_issue, 748 .sff_data_xfer = vlb32_data_xfer, 749 }; 750 751 static DEFINE_SPINLOCK(winbond_lock); 752 753 static void winbond_writecfg(unsigned long port, u8 reg, u8 val) 754 { 755 unsigned long flags; 756 spin_lock_irqsave(&winbond_lock, flags); 757 outb(reg, port + 0x01); 758 outb(val, port + 0x02); 759 spin_unlock_irqrestore(&winbond_lock, flags); 760 } 761 762 static u8 winbond_readcfg(unsigned long port, u8 reg) 763 { 764 u8 val; 765 766 unsigned long flags; 767 spin_lock_irqsave(&winbond_lock, flags); 768 outb(reg, port + 0x01); 769 val = inb(port + 0x02); 770 spin_unlock_irqrestore(&winbond_lock, flags); 771 772 return val; 773 } 774 775 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) 776 { 777 struct ata_timing t; 778 struct legacy_data *ld_winbond = ap->host->private_data; 779 int active, recovery; 780 u8 reg; 781 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); 782 783 reg = winbond_readcfg(ld_winbond->timing, 0x81); 784 785 /* Get the timing data in cycles */ 786 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ 787 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 788 else 789 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 790 791 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; 792 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; 793 timing = (active << 4) | recovery; 794 winbond_writecfg(ld_winbond->timing, timing, reg); 795 796 /* Load the setup timing */ 797 798 reg = 0x35; 799 if (adev->class != ATA_DEV_ATA) 800 reg |= 0x08; /* FIFO off */ 801 if (!ata_pio_need_iordy(adev)) 802 reg |= 0x02; /* IORDY off */ 803 reg |= (clamp_val(t.setup, 0, 3) << 6); 804 winbond_writecfg(ld_winbond->timing, timing + 1, reg); 805 } 806 807 static int winbond_port(struct platform_device *dev, 808 struct legacy_probe *lp, struct legacy_data *ld) 809 { 810 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) 811 return -EBUSY; 812 ld->timing = lp->private; 813 return 0; 814 } 815 816 static struct ata_port_operations winbond_port_ops = { 817 .inherits = &legacy_base_port_ops, 818 .set_piomode = winbond_set_piomode, 819 .sff_data_xfer = vlb32_data_xfer, 820 }; 821 822 static struct legacy_controller controllers[] = { 823 {"BIOS", &legacy_port_ops, ATA_PIO4, 824 ATA_FLAG_NO_IORDY, 0, NULL }, 825 {"Snooping", &simple_port_ops, ATA_PIO4, 826 0, 0, NULL }, 827 {"PDC20230", &pdc20230_port_ops, ATA_PIO2, 828 ATA_FLAG_NO_IORDY, 829 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, 830 {"HT6560A", &ht6560a_port_ops, ATA_PIO2, 831 ATA_FLAG_NO_IORDY, 0, NULL }, 832 {"HT6560B", &ht6560b_port_ops, ATA_PIO4, 833 ATA_FLAG_NO_IORDY, 0, NULL }, 834 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3, 835 0, 0, NULL }, 836 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3, 837 0, 0, NULL }, 838 {"QDI6500", &qdi6500_port_ops, ATA_PIO2, 839 ATA_FLAG_NO_IORDY, 840 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 841 {"QDI6580", &qdi6580_port_ops, ATA_PIO4, 842 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 843 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4, 844 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 845 {"W83759A", &winbond_port_ops, ATA_PIO4, 846 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, 847 winbond_port } 848 }; 849 850 /** 851 * probe_chip_type - Discover controller 852 * @probe: Probe entry to check 853 * 854 * Probe an ATA port and identify the type of controller. We don't 855 * check if the controller appears to be driveless at this point. 856 */ 857 858 static __init int probe_chip_type(struct legacy_probe *probe) 859 { 860 int mask = 1 << probe->slot; 861 862 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { 863 u8 reg = winbond_readcfg(winbond, 0x81); 864 reg |= 0x80; /* jumpered mode off */ 865 winbond_writecfg(winbond, 0x81, reg); 866 reg = winbond_readcfg(winbond, 0x83); 867 reg |= 0xF0; /* local control */ 868 winbond_writecfg(winbond, 0x83, reg); 869 reg = winbond_readcfg(winbond, 0x85); 870 reg |= 0xF0; /* programmable timing */ 871 winbond_writecfg(winbond, 0x85, reg); 872 873 reg = winbond_readcfg(winbond, 0x81); 874 875 if (reg & mask) 876 return W83759A; 877 } 878 if (probe->port == 0x1F0) { 879 unsigned long flags; 880 local_irq_save(flags); 881 /* Probes */ 882 outb(inb(0x1F2) | 0x80, 0x1F2); 883 inb(0x1F5); 884 inb(0x1F2); 885 inb(0x3F6); 886 inb(0x3F6); 887 inb(0x1F2); 888 inb(0x1F2); 889 890 if ((inb(0x1F2) & 0x80) == 0) { 891 /* PDC20230c or 20630 ? */ 892 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" 893 " detected.\n"); 894 udelay(100); 895 inb(0x1F5); 896 local_irq_restore(flags); 897 return PDC20230; 898 } else { 899 outb(0x55, 0x1F2); 900 inb(0x1F2); 901 inb(0x1F2); 902 if (inb(0x1F2) == 0x00) 903 printk(KERN_INFO "PDC20230-B VLB ATA " 904 "controller detected.\n"); 905 local_irq_restore(flags); 906 return BIOS; 907 } 908 } 909 910 if (ht6560a & mask) 911 return HT6560A; 912 if (ht6560b & mask) 913 return HT6560B; 914 if (opti82c611a & mask) 915 return OPTI611A; 916 if (opti82c46x & mask) 917 return OPTI46X; 918 if (autospeed & mask) 919 return SNOOP; 920 return BIOS; 921 } 922 923 924 /** 925 * legacy_init_one - attach a legacy interface 926 * @pl: probe record 927 * 928 * Register an ISA bus IDE interface. Such interfaces are PIO and we 929 * assume do not support IRQ sharing. 930 */ 931 932 static __init int legacy_init_one(struct legacy_probe *probe) 933 { 934 struct legacy_controller *controller = &controllers[probe->type]; 935 int pio_modes = controller->pio_mask; 936 unsigned long io = probe->port; 937 u32 mask = (1 << probe->slot); 938 struct ata_port_operations *ops = controller->ops; 939 struct legacy_data *ld = &legacy_data[probe->slot]; 940 struct ata_host *host = NULL; 941 struct ata_port *ap; 942 struct platform_device *pdev; 943 struct ata_device *dev; 944 void __iomem *io_addr, *ctrl_addr; 945 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 946 int ret; 947 948 iordy |= controller->flags; 949 950 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); 951 if (IS_ERR(pdev)) 952 return PTR_ERR(pdev); 953 954 ret = -EBUSY; 955 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 956 devm_request_region(&pdev->dev, io + 0x0206, 1, 957 "pata_legacy") == NULL) 958 goto fail; 959 960 ret = -ENOMEM; 961 io_addr = devm_ioport_map(&pdev->dev, io, 8); 962 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); 963 if (!io_addr || !ctrl_addr) 964 goto fail; 965 ld->type = probe->type; 966 if (controller->setup) 967 if (controller->setup(pdev, probe, ld) < 0) 968 goto fail; 969 host = ata_host_alloc(&pdev->dev, 1); 970 if (!host) 971 goto fail; 972 ap = host->ports[0]; 973 974 ap->ops = ops; 975 ap->pio_mask = pio_modes; 976 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 977 ap->pflags |= controller->pflags; 978 ap->ioaddr.cmd_addr = io_addr; 979 ap->ioaddr.altstatus_addr = ctrl_addr; 980 ap->ioaddr.ctl_addr = ctrl_addr; 981 ata_sff_std_ports(&ap->ioaddr); 982 ap->host->private_data = ld; 983 984 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); 985 986 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, 987 &legacy_sht); 988 if (ret) 989 goto fail; 990 async_synchronize_full(); 991 ld->platform_dev = pdev; 992 993 /* Nothing found means we drop the port as its probably not there */ 994 995 ret = -ENODEV; 996 ata_for_each_dev(dev, &ap->link, ALL) { 997 if (!ata_dev_absent(dev)) { 998 legacy_host[probe->slot] = host; 999 ld->platform_dev = pdev; 1000 return 0; 1001 } 1002 } 1003 ata_host_detach(host); 1004 fail: 1005 platform_device_unregister(pdev); 1006 return ret; 1007 } 1008 1009 /** 1010 * legacy_check_special_cases - ATA special cases 1011 * @p: PCI device to check 1012 * @master: set this if we find an ATA master 1013 * @master: set this if we find an ATA secondary 1014 * 1015 * A small number of vendors implemented early PCI ATA interfaces 1016 * on bridge logic without the ATA interface being PCI visible. 1017 * Where we have a matching PCI driver we must skip the relevant 1018 * device here. If we don't know about it then the legacy driver 1019 * is the right driver anyway. 1020 */ 1021 1022 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, 1023 int *secondary) 1024 { 1025 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 1026 if (p->vendor == 0x1078 && p->device == 0x0000) { 1027 *primary = *secondary = 1; 1028 return; 1029 } 1030 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 1031 if (p->vendor == 0x1078 && p->device == 0x0002) { 1032 *primary = *secondary = 1; 1033 return; 1034 } 1035 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 1036 if (p->vendor == 0x8086 && p->device == 0x1234) { 1037 u16 r; 1038 pci_read_config_word(p, 0x6C, &r); 1039 if (r & 0x8000) { 1040 /* ATA port enabled */ 1041 if (r & 0x4000) 1042 *secondary = 1; 1043 else 1044 *primary = 1; 1045 } 1046 return; 1047 } 1048 } 1049 1050 static __init void probe_opti_vlb(void) 1051 { 1052 /* If an OPTI 82C46X is present find out where the channels are */ 1053 static const char *optis[4] = { 1054 "3/463MV", "5MV", 1055 "5MVA", "5MVB" 1056 }; 1057 u8 chans = 1; 1058 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 1059 1060 opti82c46x = 3; /* Assume master and slave first */ 1061 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", 1062 optis[ctrl]); 1063 if (ctrl == 3) 1064 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 1065 ctrl = opti_syscfg(0xAC); 1066 /* Check enabled and this port is the 465MV port. On the 1067 MVB we may have two channels */ 1068 if (ctrl & 8) { 1069 if (chans == 2) { 1070 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1071 legacy_probe_add(0x170, 15, OPTI46X, 0); 1072 } 1073 if (ctrl & 4) 1074 legacy_probe_add(0x170, 15, OPTI46X, 0); 1075 else 1076 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1077 } else 1078 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1079 } 1080 1081 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) 1082 { 1083 static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; 1084 /* Check card type */ 1085 if ((r & 0xF0) == 0xC0) { 1086 /* QD6500: single channel */ 1087 if (r & 8) 1088 /* Disabled ? */ 1089 return; 1090 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1091 QDI6500, port); 1092 } 1093 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { 1094 /* QD6580: dual channel */ 1095 if (!request_region(port + 2 , 2, "pata_qdi")) { 1096 release_region(port, 2); 1097 return; 1098 } 1099 res = inb(port + 3); 1100 /* Single channel mode ? */ 1101 if (res & 1) 1102 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1103 QDI6580, port); 1104 else { /* Dual channel mode */ 1105 legacy_probe_add(0x1F0, 14, QDI6580DP, port); 1106 /* port + 0x02, r & 0x04 */ 1107 legacy_probe_add(0x170, 15, QDI6580DP, port + 2); 1108 } 1109 release_region(port + 2, 2); 1110 } 1111 } 1112 1113 static __init void probe_qdi_vlb(void) 1114 { 1115 unsigned long flags; 1116 static const unsigned long qd_port[2] = { 0x30, 0xB0 }; 1117 int i; 1118 1119 /* 1120 * Check each possible QD65xx base address 1121 */ 1122 1123 for (i = 0; i < 2; i++) { 1124 unsigned long port = qd_port[i]; 1125 u8 r, res; 1126 1127 1128 if (request_region(port, 2, "pata_qdi")) { 1129 /* Check for a card */ 1130 local_irq_save(flags); 1131 /* I have no h/w that needs this delay but it 1132 is present in the historic code */ 1133 r = inb(port); 1134 udelay(1); 1135 outb(0x19, port); 1136 udelay(1); 1137 res = inb(port); 1138 udelay(1); 1139 outb(r, port); 1140 udelay(1); 1141 local_irq_restore(flags); 1142 1143 /* Fail */ 1144 if (res == 0x19) { 1145 release_region(port, 2); 1146 continue; 1147 } 1148 /* Passes the presence test */ 1149 r = inb(port + 1); 1150 udelay(1); 1151 /* Check port agrees with port set */ 1152 if ((r & 2) >> 1 == i) 1153 qdi65_identify_port(r, res, port); 1154 release_region(port, 2); 1155 } 1156 } 1157 } 1158 1159 /** 1160 * legacy_init - attach legacy interfaces 1161 * 1162 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 1163 * Right now we do not scan the ide0 and ide1 address but should do so 1164 * for non PCI systems or systems with no PCI IDE legacy mode devices. 1165 * If you fix that note there are special cases to consider like VLB 1166 * drivers and CS5510/20. 1167 */ 1168 1169 static __init int legacy_init(void) 1170 { 1171 int i; 1172 int ct = 0; 1173 int primary = 0; 1174 int secondary = 0; 1175 int pci_present = 0; 1176 struct legacy_probe *pl = &probe_list[0]; 1177 int slot = 0; 1178 1179 struct pci_dev *p = NULL; 1180 1181 for_each_pci_dev(p) { 1182 int r; 1183 /* Check for any overlap of the system ATA mappings. Native 1184 mode controllers stuck on these addresses or some devices 1185 in 'raid' mode won't be found by the storage class test */ 1186 for (r = 0; r < 6; r++) { 1187 if (pci_resource_start(p, r) == 0x1f0) 1188 primary = 1; 1189 if (pci_resource_start(p, r) == 0x170) 1190 secondary = 1; 1191 } 1192 /* Check for special cases */ 1193 legacy_check_special_cases(p, &primary, &secondary); 1194 1195 /* If PCI bus is present then don't probe for tertiary 1196 legacy ports */ 1197 pci_present = 1; 1198 } 1199 1200 if (winbond == 1) 1201 winbond = 0x130; /* Default port, alt is 1B0 */ 1202 1203 if (primary == 0 || all) 1204 legacy_probe_add(0x1F0, 14, UNKNOWN, 0); 1205 if (secondary == 0 || all) 1206 legacy_probe_add(0x170, 15, UNKNOWN, 0); 1207 1208 if (probe_all || !pci_present) { 1209 /* ISA/VLB extra ports */ 1210 legacy_probe_add(0x1E8, 11, UNKNOWN, 0); 1211 legacy_probe_add(0x168, 10, UNKNOWN, 0); 1212 legacy_probe_add(0x1E0, 8, UNKNOWN, 0); 1213 legacy_probe_add(0x160, 12, UNKNOWN, 0); 1214 } 1215 1216 if (opti82c46x) 1217 probe_opti_vlb(); 1218 if (qdi) 1219 probe_qdi_vlb(); 1220 1221 for (i = 0; i < NR_HOST; i++, pl++) { 1222 if (pl->port == 0) 1223 continue; 1224 if (pl->type == UNKNOWN) 1225 pl->type = probe_chip_type(pl); 1226 pl->slot = slot++; 1227 if (legacy_init_one(pl) == 0) 1228 ct++; 1229 } 1230 if (ct != 0) 1231 return 0; 1232 return -ENODEV; 1233 } 1234 1235 static __exit void legacy_exit(void) 1236 { 1237 int i; 1238 1239 for (i = 0; i < nr_legacy_host; i++) { 1240 struct legacy_data *ld = &legacy_data[i]; 1241 ata_host_detach(legacy_host[i]); 1242 platform_device_unregister(ld->platform_dev); 1243 } 1244 } 1245 1246 MODULE_AUTHOR("Alan Cox"); 1247 MODULE_DESCRIPTION("low-level driver for legacy ATA"); 1248 MODULE_LICENSE("GPL"); 1249 MODULE_VERSION(DRV_VERSION); 1250 MODULE_ALIAS("pata_qdi"); 1251 MODULE_ALIAS("pata_winbond"); 1252 1253 module_param(probe_all, int, 0); 1254 module_param(autospeed, int, 0); 1255 module_param(ht6560a, int, 0); 1256 module_param(ht6560b, int, 0); 1257 module_param(opti82c611a, int, 0); 1258 module_param(opti82c46x, int, 0); 1259 module_param(qdi, int, 0); 1260 module_param(winbond, int, 0); 1261 module_param(pio_mask, int, 0); 1262 module_param(iordy_mask, int, 0); 1263 1264 module_init(legacy_init); 1265 module_exit(legacy_exit); 1266