1 #include <linux/kernel.h> 2 #include <linux/module.h> 3 #include <linux/init.h> 4 #include <linux/blkdev.h> 5 #include <scsi/scsi_host.h> 6 #include <linux/ata.h> 7 #include <linux/libata.h> 8 9 #include <asm/dma.h> 10 #include <asm/ecard.h> 11 12 #define DRV_NAME "pata_icside" 13 14 #define ICS_IDENT_OFFSET 0x2280 15 16 #define ICS_ARCIN_V5_INTRSTAT 0x0000 17 #define ICS_ARCIN_V5_INTROFFSET 0x0004 18 19 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200 20 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290 21 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 22 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290 23 24 struct portinfo { 25 unsigned int dataoffset; 26 unsigned int ctrloffset; 27 unsigned int stepping; 28 }; 29 30 static const struct portinfo pata_icside_portinfo_v5 = { 31 .dataoffset = 0x2800, 32 .ctrloffset = 0x2b80, 33 .stepping = 6, 34 }; 35 36 static const struct portinfo pata_icside_portinfo_v6_1 = { 37 .dataoffset = 0x2000, 38 .ctrloffset = 0x2380, 39 .stepping = 6, 40 }; 41 42 static const struct portinfo pata_icside_portinfo_v6_2 = { 43 .dataoffset = 0x3000, 44 .ctrloffset = 0x3380, 45 .stepping = 6, 46 }; 47 48 #define PATA_ICSIDE_MAX_SG 128 49 50 struct pata_icside_state { 51 void __iomem *irq_port; 52 void __iomem *ioc_base; 53 unsigned int type; 54 unsigned int dma; 55 struct { 56 u8 port_sel; 57 u8 disabled; 58 unsigned int speed[ATA_MAX_DEVICES]; 59 } port[2]; 60 struct scatterlist sg[PATA_ICSIDE_MAX_SG]; 61 }; 62 63 struct pata_icside_info { 64 struct pata_icside_state *state; 65 struct expansion_card *ec; 66 void __iomem *base; 67 void __iomem *irqaddr; 68 unsigned int irqmask; 69 const expansioncard_ops_t *irqops; 70 unsigned int mwdma_mask; 71 unsigned int nr_ports; 72 const struct portinfo *port[2]; 73 unsigned long raw_base; 74 unsigned long raw_ioc_base; 75 }; 76 77 #define ICS_TYPE_A3IN 0 78 #define ICS_TYPE_A3USER 1 79 #define ICS_TYPE_V6 3 80 #define ICS_TYPE_V5 15 81 #define ICS_TYPE_NOTYPE ((unsigned int)-1) 82 83 /* ---------------- Version 5 PCB Support Functions --------------------- */ 84 /* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) 85 * Purpose : enable interrupts from card 86 */ 87 static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) 88 { 89 struct pata_icside_state *state = ec->irq_data; 90 91 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); 92 } 93 94 /* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) 95 * Purpose : disable interrupts from card 96 */ 97 static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) 98 { 99 struct pata_icside_state *state = ec->irq_data; 100 101 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); 102 } 103 104 static const expansioncard_ops_t pata_icside_ops_arcin_v5 = { 105 .irqenable = pata_icside_irqenable_arcin_v5, 106 .irqdisable = pata_icside_irqdisable_arcin_v5, 107 }; 108 109 110 /* ---------------- Version 6 PCB Support Functions --------------------- */ 111 /* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) 112 * Purpose : enable interrupts from card 113 */ 114 static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) 115 { 116 struct pata_icside_state *state = ec->irq_data; 117 void __iomem *base = state->irq_port; 118 119 if (!state->port[0].disabled) 120 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); 121 if (!state->port[1].disabled) 122 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); 123 } 124 125 /* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) 126 * Purpose : disable interrupts from card 127 */ 128 static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) 129 { 130 struct pata_icside_state *state = ec->irq_data; 131 132 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); 133 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); 134 } 135 136 /* Prototype: pata_icside_irqprobe(struct expansion_card *ec) 137 * Purpose : detect an active interrupt from card 138 */ 139 static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec) 140 { 141 struct pata_icside_state *state = ec->irq_data; 142 143 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || 144 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; 145 } 146 147 static const expansioncard_ops_t pata_icside_ops_arcin_v6 = { 148 .irqenable = pata_icside_irqenable_arcin_v6, 149 .irqdisable = pata_icside_irqdisable_arcin_v6, 150 .irqpending = pata_icside_irqpending_arcin_v6, 151 }; 152 153 154 /* 155 * SG-DMA support. 156 * 157 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers. 158 * There is only one DMA controller per card, which means that only 159 * one drive can be accessed at one time. NOTE! We do not enforce that 160 * here, but we rely on the main IDE driver spotting that both 161 * interfaces use the same IRQ, which should guarantee this. 162 */ 163 164 /* 165 * Configure the IOMD to give the appropriate timings for the transfer 166 * mode being requested. We take the advice of the ATA standards, and 167 * calculate the cycle time based on the transfer mode, and the EIDE 168 * MW DMA specs that the drive provides in the IDENTIFY command. 169 * 170 * We have the following IOMD DMA modes to choose from: 171 * 172 * Type Active Recovery Cycle 173 * A 250 (250) 312 (550) 562 (800) 174 * B 187 (200) 250 (550) 437 (750) 175 * C 125 (125) 125 (375) 250 (500) 176 * D 62 (50) 125 (375) 187 (425) 177 * 178 * (figures in brackets are actual measured timings on DIOR/DIOW) 179 * 180 * However, we also need to take care of the read/write active and 181 * recovery timings: 182 * 183 * Read Write 184 * Mode Active -- Recovery -- Cycle IOMD type 185 * MW0 215 50 215 480 A 186 * MW1 80 50 50 150 C 187 * MW2 70 25 25 120 C 188 */ 189 static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev) 190 { 191 struct pata_icside_state *state = ap->host->private_data; 192 struct ata_timing t; 193 unsigned int cycle; 194 char iomd_type; 195 196 /* 197 * DMA is based on a 16MHz clock 198 */ 199 if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1)) 200 return; 201 202 /* 203 * Choose the IOMD cycle timing which ensure that the interface 204 * satisfies the measured active, recovery and cycle times. 205 */ 206 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) 207 iomd_type = 'D', cycle = 187; 208 else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) 209 iomd_type = 'C', cycle = 250; 210 else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) 211 iomd_type = 'B', cycle = 437; 212 else 213 iomd_type = 'A', cycle = 562; 214 215 ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n", 216 t.active, t.recover, t.cycle, iomd_type); 217 218 state->port[ap->port_no].speed[adev->devno] = cycle; 219 } 220 221 static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc) 222 { 223 struct ata_port *ap = qc->ap; 224 struct pata_icside_state *state = ap->host->private_data; 225 struct scatterlist *sg, *rsg = state->sg; 226 unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE; 227 unsigned int si; 228 229 /* 230 * We are simplex; BUG if we try to fiddle with DMA 231 * while it's active. 232 */ 233 BUG_ON(dma_channel_active(state->dma)); 234 235 /* 236 * Copy ATAs scattered sg list into a contiguous array of sg 237 */ 238 for_each_sg(qc->sg, sg, qc->n_elem, si) { 239 memcpy(rsg, sg, sizeof(*sg)); 240 rsg++; 241 } 242 243 /* 244 * Route the DMA signals to the correct interface 245 */ 246 writeb(state->port[ap->port_no].port_sel, state->ioc_base); 247 248 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); 249 set_dma_sg(state->dma, state->sg, rsg - state->sg); 250 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); 251 252 /* issue r/w command */ 253 ap->ops->exec_command(ap, &qc->tf); 254 } 255 256 static void pata_icside_bmdma_start(struct ata_queued_cmd *qc) 257 { 258 struct ata_port *ap = qc->ap; 259 struct pata_icside_state *state = ap->host->private_data; 260 261 BUG_ON(dma_channel_active(state->dma)); 262 enable_dma(state->dma); 263 } 264 265 static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc) 266 { 267 struct ata_port *ap = qc->ap; 268 struct pata_icside_state *state = ap->host->private_data; 269 270 disable_dma(state->dma); 271 272 /* see ata_bmdma_stop */ 273 ata_altstatus(ap); 274 } 275 276 static u8 pata_icside_bmdma_status(struct ata_port *ap) 277 { 278 struct pata_icside_state *state = ap->host->private_data; 279 void __iomem *irq_port; 280 281 irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 : 282 ICS_ARCIN_V6_INTRSTAT_1); 283 284 return readb(irq_port) & 1 ? ATA_DMA_INTR : 0; 285 } 286 287 static int icside_dma_init(struct pata_icside_info *info) 288 { 289 struct pata_icside_state *state = info->state; 290 struct expansion_card *ec = info->ec; 291 int i; 292 293 for (i = 0; i < ATA_MAX_DEVICES; i++) { 294 state->port[0].speed[i] = 480; 295 state->port[1].speed[i] = 480; 296 } 297 298 if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) { 299 state->dma = ec->dma; 300 info->mwdma_mask = 0x07; /* MW0..2 */ 301 } 302 303 return 0; 304 } 305 306 307 static struct scsi_host_template pata_icside_sht = { 308 .module = THIS_MODULE, 309 .name = DRV_NAME, 310 .ioctl = ata_scsi_ioctl, 311 .queuecommand = ata_scsi_queuecmd, 312 .can_queue = ATA_DEF_QUEUE, 313 .this_id = ATA_SHT_THIS_ID, 314 .sg_tablesize = PATA_ICSIDE_MAX_SG, 315 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 316 .emulated = ATA_SHT_EMULATED, 317 .use_clustering = ATA_SHT_USE_CLUSTERING, 318 .proc_name = DRV_NAME, 319 .dma_boundary = ~0, /* no dma boundaries */ 320 .slave_configure = ata_scsi_slave_config, 321 .slave_destroy = ata_scsi_slave_destroy, 322 .bios_param = ata_std_bios_param, 323 }; 324 325 /* wish this was exported from libata-core */ 326 static void ata_dummy_noret(struct ata_port *port) 327 { 328 } 329 330 static void pata_icside_postreset(struct ata_link *link, unsigned int *classes) 331 { 332 struct ata_port *ap = link->ap; 333 struct pata_icside_state *state = ap->host->private_data; 334 335 if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE) 336 return ata_std_postreset(link, classes); 337 338 state->port[ap->port_no].disabled = 1; 339 340 if (state->type == ICS_TYPE_V6) { 341 /* 342 * Disable interrupts from this port, otherwise we 343 * receive spurious interrupts from the floating 344 * interrupt line. 345 */ 346 void __iomem *irq_port = state->irq_port + 347 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1); 348 readb(irq_port); 349 } 350 } 351 352 static void pata_icside_error_handler(struct ata_port *ap) 353 { 354 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL, 355 pata_icside_postreset); 356 } 357 358 static struct ata_port_operations pata_icside_port_ops = { 359 .set_dmamode = pata_icside_set_dmamode, 360 361 .tf_load = ata_tf_load, 362 .tf_read = ata_tf_read, 363 .exec_command = ata_exec_command, 364 .check_status = ata_check_status, 365 .dev_select = ata_std_dev_select, 366 367 .cable_detect = ata_cable_40wire, 368 369 .bmdma_setup = pata_icside_bmdma_setup, 370 .bmdma_start = pata_icside_bmdma_start, 371 372 .data_xfer = ata_data_xfer_noirq, 373 374 /* no need to build any PRD tables for DMA */ 375 .qc_prep = ata_noop_qc_prep, 376 .qc_issue = ata_qc_issue_prot, 377 378 .freeze = ata_bmdma_freeze, 379 .thaw = ata_bmdma_thaw, 380 .error_handler = pata_icside_error_handler, 381 .post_internal_cmd = pata_icside_bmdma_stop, 382 383 .irq_clear = ata_dummy_noret, 384 .irq_on = ata_irq_on, 385 386 .bmdma_stop = pata_icside_bmdma_stop, 387 .bmdma_status = pata_icside_bmdma_status, 388 }; 389 390 static void __devinit 391 pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base, 392 struct pata_icside_info *info, 393 const struct portinfo *port) 394 { 395 struct ata_ioports *ioaddr = &ap->ioaddr; 396 void __iomem *cmd = base + port->dataoffset; 397 398 ioaddr->cmd_addr = cmd; 399 ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping); 400 ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping); 401 ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping); 402 ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping); 403 ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping); 404 ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping); 405 ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping); 406 ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping); 407 ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping); 408 ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping); 409 410 ioaddr->ctl_addr = base + port->ctrloffset; 411 ioaddr->altstatus_addr = ioaddr->ctl_addr; 412 413 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", 414 info->raw_base + port->dataoffset, 415 info->raw_base + port->ctrloffset); 416 417 if (info->raw_ioc_base) 418 ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base); 419 } 420 421 static int __devinit pata_icside_register_v5(struct pata_icside_info *info) 422 { 423 struct pata_icside_state *state = info->state; 424 void __iomem *base; 425 426 base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0); 427 if (!base) 428 return -ENOMEM; 429 430 state->irq_port = base; 431 432 info->base = base; 433 info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; 434 info->irqmask = 1; 435 info->irqops = &pata_icside_ops_arcin_v5; 436 info->nr_ports = 1; 437 info->port[0] = &pata_icside_portinfo_v5; 438 439 info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC); 440 441 return 0; 442 } 443 444 static int __devinit pata_icside_register_v6(struct pata_icside_info *info) 445 { 446 struct pata_icside_state *state = info->state; 447 struct expansion_card *ec = info->ec; 448 void __iomem *ioc_base, *easi_base; 449 unsigned int sel = 0; 450 451 ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 452 if (!ioc_base) 453 return -ENOMEM; 454 455 easi_base = ioc_base; 456 457 if (ecard_resource_flags(ec, ECARD_RES_EASI)) { 458 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); 459 if (!easi_base) 460 return -ENOMEM; 461 462 /* 463 * Enable access to the EASI region. 464 */ 465 sel = 1 << 5; 466 } 467 468 writeb(sel, ioc_base); 469 470 state->irq_port = easi_base; 471 state->ioc_base = ioc_base; 472 state->port[0].port_sel = sel; 473 state->port[1].port_sel = sel | 1; 474 475 info->base = easi_base; 476 info->irqops = &pata_icside_ops_arcin_v6; 477 info->nr_ports = 2; 478 info->port[0] = &pata_icside_portinfo_v6_1; 479 info->port[1] = &pata_icside_portinfo_v6_2; 480 481 info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI); 482 info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST); 483 484 return icside_dma_init(info); 485 } 486 487 static int __devinit pata_icside_add_ports(struct pata_icside_info *info) 488 { 489 struct expansion_card *ec = info->ec; 490 struct ata_host *host; 491 int i; 492 493 if (info->irqaddr) { 494 ec->irqaddr = info->irqaddr; 495 ec->irqmask = info->irqmask; 496 } 497 if (info->irqops) 498 ecard_setirq(ec, info->irqops, info->state); 499 500 /* 501 * Be on the safe side - disable interrupts 502 */ 503 ec->ops->irqdisable(ec, ec->irq); 504 505 host = ata_host_alloc(&ec->dev, info->nr_ports); 506 if (!host) 507 return -ENOMEM; 508 509 host->private_data = info->state; 510 host->flags = ATA_HOST_SIMPLEX; 511 512 for (i = 0; i < info->nr_ports; i++) { 513 struct ata_port *ap = host->ports[i]; 514 515 ap->pio_mask = 0x1f; 516 ap->mwdma_mask = info->mwdma_mask; 517 ap->flags |= ATA_FLAG_SLAVE_POSS; 518 ap->ops = &pata_icside_port_ops; 519 520 pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]); 521 } 522 523 return ata_host_activate(host, ec->irq, ata_interrupt, 0, 524 &pata_icside_sht); 525 } 526 527 static int __devinit 528 pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) 529 { 530 struct pata_icside_state *state; 531 struct pata_icside_info info; 532 void __iomem *idmem; 533 int ret; 534 535 ret = ecard_request_resources(ec); 536 if (ret) 537 goto out; 538 539 state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL); 540 if (!state) { 541 ret = -ENOMEM; 542 goto release; 543 } 544 545 state->type = ICS_TYPE_NOTYPE; 546 state->dma = NO_DMA; 547 548 idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); 549 if (idmem) { 550 unsigned int type; 551 552 type = readb(idmem + ICS_IDENT_OFFSET) & 1; 553 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; 554 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; 555 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; 556 ecardm_iounmap(ec, idmem); 557 558 state->type = type; 559 } 560 561 memset(&info, 0, sizeof(info)); 562 info.state = state; 563 info.ec = ec; 564 565 switch (state->type) { 566 case ICS_TYPE_A3IN: 567 dev_warn(&ec->dev, "A3IN unsupported\n"); 568 ret = -ENODEV; 569 break; 570 571 case ICS_TYPE_A3USER: 572 dev_warn(&ec->dev, "A3USER unsupported\n"); 573 ret = -ENODEV; 574 break; 575 576 case ICS_TYPE_V5: 577 ret = pata_icside_register_v5(&info); 578 break; 579 580 case ICS_TYPE_V6: 581 ret = pata_icside_register_v6(&info); 582 break; 583 584 default: 585 dev_warn(&ec->dev, "unknown interface type\n"); 586 ret = -ENODEV; 587 break; 588 } 589 590 if (ret == 0) 591 ret = pata_icside_add_ports(&info); 592 593 if (ret == 0) 594 goto out; 595 596 release: 597 ecard_release_resources(ec); 598 out: 599 return ret; 600 } 601 602 static void pata_icside_shutdown(struct expansion_card *ec) 603 { 604 struct ata_host *host = ecard_get_drvdata(ec); 605 unsigned long flags; 606 607 /* 608 * Disable interrupts from this card. We need to do 609 * this before disabling EASI since we may be accessing 610 * this register via that region. 611 */ 612 local_irq_save(flags); 613 ec->ops->irqdisable(ec, ec->irq); 614 local_irq_restore(flags); 615 616 /* 617 * Reset the ROM pointer so that we can read the ROM 618 * after a soft reboot. This also disables access to 619 * the IDE taskfile via the EASI region. 620 */ 621 if (host) { 622 struct pata_icside_state *state = host->private_data; 623 if (state->ioc_base) 624 writeb(0, state->ioc_base); 625 } 626 } 627 628 static void __devexit pata_icside_remove(struct expansion_card *ec) 629 { 630 struct ata_host *host = ecard_get_drvdata(ec); 631 struct pata_icside_state *state = host->private_data; 632 633 ata_host_detach(host); 634 635 pata_icside_shutdown(ec); 636 637 /* 638 * don't NULL out the drvdata - devres/libata wants it 639 * to free the ata_host structure. 640 */ 641 if (state->dma != NO_DMA) 642 free_dma(state->dma); 643 644 ecard_release_resources(ec); 645 } 646 647 static const struct ecard_id pata_icside_ids[] = { 648 { MANU_ICS, PROD_ICS_IDE }, 649 { MANU_ICS2, PROD_ICS2_IDE }, 650 { 0xffff, 0xffff } 651 }; 652 653 static struct ecard_driver pata_icside_driver = { 654 .probe = pata_icside_probe, 655 .remove = __devexit_p(pata_icside_remove), 656 .shutdown = pata_icside_shutdown, 657 .id_table = pata_icside_ids, 658 .drv = { 659 .name = DRV_NAME, 660 }, 661 }; 662 663 static int __init pata_icside_init(void) 664 { 665 return ecard_register_driver(&pata_icside_driver); 666 } 667 668 static void __exit pata_icside_exit(void) 669 { 670 ecard_remove_driver(&pata_icside_driver); 671 } 672 673 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); 674 MODULE_LICENSE("GPL"); 675 MODULE_DESCRIPTION("ICS PATA driver"); 676 677 module_init(pata_icside_init); 678 module_exit(pata_icside_exit); 679