1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers. 4 * 5 * This driver is heavily based upon: 6 * 7 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 8 * 9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 10 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 11 * Portions Copyright (C) 2003 Red Hat Inc 12 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. 13 * 14 * 15 * TODO 16 * Work out best PLL policy 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/blkdev.h> 22 #include <linux/delay.h> 23 #include <scsi/scsi_host.h> 24 #include <linux/libata.h> 25 26 #define DRV_NAME "pata_hpt3x2n" 27 #define DRV_VERSION "0.3.18" 28 29 enum { 30 PCI66 = (1 << 1), 31 USE_DPLL = (1 << 0) 32 }; 33 34 struct hpt_clock { 35 u8 xfer_speed; 36 u32 timing; 37 }; 38 39 /* key for bus clock timings 40 * bit 41 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 42 * cycles = value + 1 43 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 44 * cycles = value + 1 45 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 46 * register access. 47 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 48 * register access. 49 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 50 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. 51 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. 52 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file 53 * register access. 54 * 28 UDMA enable. 55 * 29 DMA enable. 56 * 30 PIO_MST enable. If set, the chip is in bus master mode during 57 * PIO xfer. 58 * 31 FIFO enable. Only for PIO. 59 */ 60 61 /* 66MHz DPLL clocks */ 62 63 static struct hpt_clock hpt3x2n_clocks[] = { 64 { XFER_UDMA_7, 0x1c869c62 }, 65 { XFER_UDMA_6, 0x1c869c62 }, 66 { XFER_UDMA_5, 0x1c8a9c62 }, 67 { XFER_UDMA_4, 0x1c8a9c62 }, 68 { XFER_UDMA_3, 0x1c8e9c62 }, 69 { XFER_UDMA_2, 0x1c929c62 }, 70 { XFER_UDMA_1, 0x1c9a9c62 }, 71 { XFER_UDMA_0, 0x1c829c62 }, 72 73 { XFER_MW_DMA_2, 0x2c829c62 }, 74 { XFER_MW_DMA_1, 0x2c829c66 }, 75 { XFER_MW_DMA_0, 0x2c829d2e }, 76 77 { XFER_PIO_4, 0x0c829c62 }, 78 { XFER_PIO_3, 0x0c829c84 }, 79 { XFER_PIO_2, 0x0c829ca6 }, 80 { XFER_PIO_1, 0x0d029d26 }, 81 { XFER_PIO_0, 0x0d029d5e }, 82 }; 83 84 /** 85 * hpt3x2n_find_mode - reset the hpt3x2n bus 86 * @ap: ATA port 87 * @speed: transfer mode 88 * 89 * Return the 32bit register programming information for this channel 90 * that matches the speed provided. For the moment the clocks table 91 * is hard coded but easy to change. This will be needed if we use 92 * different DPLLs 93 */ 94 95 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) 96 { 97 struct hpt_clock *clocks = hpt3x2n_clocks; 98 99 while (clocks->xfer_speed) { 100 if (clocks->xfer_speed == speed) 101 return clocks->timing; 102 clocks++; 103 } 104 BUG(); 105 return 0xffffffffU; /* silence compiler warning */ 106 } 107 108 /** 109 * hpt372n_filter - mode selection filter 110 * @adev: ATA device 111 * @mask: mode mask 112 * 113 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 114 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 115 */ 116 static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask) 117 { 118 if (ata_id_is_sata(adev->id)) 119 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); 120 121 return mask; 122 } 123 124 /** 125 * hpt3x2n_cable_detect - Detect the cable type 126 * @ap: ATA port to detect on 127 * 128 * Return the cable type attached to this port 129 */ 130 131 static int hpt3x2n_cable_detect(struct ata_port *ap) 132 { 133 u8 scr2, ata66; 134 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 135 136 pci_read_config_byte(pdev, 0x5B, &scr2); 137 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 138 139 udelay(10); /* debounce */ 140 141 /* Cable register now active */ 142 pci_read_config_byte(pdev, 0x5A, &ata66); 143 /* Restore state */ 144 pci_write_config_byte(pdev, 0x5B, scr2); 145 146 if (ata66 & (2 >> ap->port_no)) 147 return ATA_CBL_PATA40; 148 else 149 return ATA_CBL_PATA80; 150 } 151 152 /** 153 * hpt3x2n_pre_reset - reset the hpt3x2n bus 154 * @link: ATA link to reset 155 * @deadline: deadline jiffies for the operation 156 * 157 * Perform the initial reset handling for the 3x2n series controllers. 158 * Reset the hardware and state machine, 159 */ 160 161 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) 162 { 163 struct ata_port *ap = link->ap; 164 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 165 static const struct pci_bits hpt3x2n_enable_bits[] = { 166 { 0x50, 1, 0x04, 0x04 }, 167 { 0x54, 1, 0x04, 0x04 } 168 }; 169 u8 mcr2; 170 171 if (!pci_test_config_bits(pdev, &hpt3x2n_enable_bits[ap->port_no])) 172 return -ENOENT; 173 174 /* Reset the state machine */ 175 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 176 udelay(100); 177 178 /* Fast interrupt prediction disable, hold off interrupt disable */ 179 pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2); 180 mcr2 &= ~0x07; 181 pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2); 182 183 return ata_sff_prereset(link, deadline); 184 } 185 186 static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, 187 u8 mode) 188 { 189 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 190 int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 191 u32 reg, timing, mask; 192 193 /* Determine timing mask and find matching mode entry */ 194 if (mode < XFER_MW_DMA_0) 195 mask = 0xcfc3ffff; 196 else if (mode < XFER_UDMA_0) 197 mask = 0x31c001ff; 198 else 199 mask = 0x303c0000; 200 201 timing = hpt3x2n_find_mode(ap, mode); 202 203 pci_read_config_dword(pdev, addr, ®); 204 reg = (reg & ~mask) | (timing & mask); 205 pci_write_config_dword(pdev, addr, reg); 206 } 207 208 /** 209 * hpt3x2n_set_piomode - PIO setup 210 * @ap: ATA interface 211 * @adev: device on the interface 212 * 213 * Perform PIO mode setup. 214 */ 215 216 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) 217 { 218 hpt3x2n_set_mode(ap, adev, adev->pio_mode); 219 } 220 221 /** 222 * hpt3x2n_set_dmamode - DMA timing setup 223 * @ap: ATA interface 224 * @adev: Device being configured 225 * 226 * Set up the channel for MWDMA or UDMA modes. 227 */ 228 229 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) 230 { 231 hpt3x2n_set_mode(ap, adev, adev->dma_mode); 232 } 233 234 /** 235 * hpt3x2n_bmdma_stop - DMA engine stop 236 * @qc: ATA command 237 * 238 * Clean up after the HPT3x2n and later DMA engine 239 */ 240 241 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) 242 { 243 struct ata_port *ap = qc->ap; 244 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 245 int mscreg = 0x50 + 4 * ap->port_no; 246 u8 bwsr_stat, msc_stat; 247 248 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 249 pci_read_config_byte(pdev, mscreg, &msc_stat); 250 if (bwsr_stat & (1 << ap->port_no)) 251 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 252 ata_bmdma_stop(qc); 253 } 254 255 /** 256 * hpt3x2n_set_clock - clock control 257 * @ap: ATA port 258 * @source: 0x21 or 0x23 for PLL or PCI sourced clock 259 * 260 * Switch the ATA bus clock between the PLL and PCI clock sources 261 * while correctly isolating the bus and resetting internal logic 262 * 263 * We must use the DPLL for 264 * - writing 265 * - second channel UDMA7 (SATA ports) or higher 266 * - 66MHz PCI 267 * 268 * or we will underclock the device and get reduced performance. 269 */ 270 271 static void hpt3x2n_set_clock(struct ata_port *ap, int source) 272 { 273 void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; 274 275 /* Tristate the bus */ 276 iowrite8(0x80, bmdma+0x73); 277 iowrite8(0x80, bmdma+0x77); 278 279 /* Switch clock and reset channels */ 280 iowrite8(source, bmdma+0x7B); 281 iowrite8(0xC0, bmdma+0x79); 282 283 /* Reset state machines, avoid enabling the disabled channels */ 284 iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); 285 iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); 286 287 /* Complete reset */ 288 iowrite8(0x00, bmdma+0x79); 289 290 /* Reconnect channels to bus */ 291 iowrite8(0x00, bmdma+0x73); 292 iowrite8(0x00, bmdma+0x77); 293 } 294 295 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) 296 { 297 long flags = (long)ap->host->private_data; 298 299 /* See if we should use the DPLL */ 300 if (writing) 301 return USE_DPLL; /* Needed for write */ 302 if (flags & PCI66) 303 return USE_DPLL; /* Needed at 66Mhz */ 304 return 0; 305 } 306 307 static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) 308 { 309 struct ata_port *ap = qc->ap; 310 struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; 311 int rc, flags = (long)ap->host->private_data; 312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); 313 314 /* First apply the usual rules */ 315 rc = ata_std_qc_defer(qc); 316 if (rc != 0) 317 return rc; 318 319 if ((flags & USE_DPLL) != dpll && alt->qc_active) 320 return ATA_DEFER_PORT; 321 return 0; 322 } 323 324 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) 325 { 326 struct ata_port *ap = qc->ap; 327 int flags = (long)ap->host->private_data; 328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); 329 330 if ((flags & USE_DPLL) != dpll) { 331 flags &= ~USE_DPLL; 332 flags |= dpll; 333 ap->host->private_data = (void *)(long)flags; 334 335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); 336 } 337 return ata_bmdma_qc_issue(qc); 338 } 339 340 static struct scsi_host_template hpt3x2n_sht = { 341 ATA_BMDMA_SHT(DRV_NAME), 342 }; 343 344 /* 345 * Configuration for HPT302N/371N. 346 */ 347 348 static struct ata_port_operations hpt3xxn_port_ops = { 349 .inherits = &ata_bmdma_port_ops, 350 351 .bmdma_stop = hpt3x2n_bmdma_stop, 352 353 .qc_defer = hpt3x2n_qc_defer, 354 .qc_issue = hpt3x2n_qc_issue, 355 356 .cable_detect = hpt3x2n_cable_detect, 357 .set_piomode = hpt3x2n_set_piomode, 358 .set_dmamode = hpt3x2n_set_dmamode, 359 .prereset = hpt3x2n_pre_reset, 360 }; 361 362 /* 363 * Configuration for HPT372N. Same as 302N/371N but we have a mode filter. 364 */ 365 366 static struct ata_port_operations hpt372n_port_ops = { 367 .inherits = &hpt3xxn_port_ops, 368 .mode_filter = &hpt372n_filter, 369 }; 370 371 /** 372 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop 373 * @dev: PCI device 374 * 375 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this 376 * succeeds 377 */ 378 379 static int hpt3xn_calibrate_dpll(struct pci_dev *dev) 380 { 381 u8 reg5b; 382 u32 reg5c; 383 int tries; 384 385 for (tries = 0; tries < 0x5000; tries++) { 386 udelay(50); 387 pci_read_config_byte(dev, 0x5b, ®5b); 388 if (reg5b & 0x80) { 389 /* See if it stays set */ 390 for (tries = 0; tries < 0x1000; tries++) { 391 pci_read_config_byte(dev, 0x5b, ®5b); 392 /* Failed ? */ 393 if ((reg5b & 0x80) == 0) 394 return 0; 395 } 396 /* Turn off tuning, we have the DPLL set */ 397 pci_read_config_dword(dev, 0x5c, ®5c); 398 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); 399 return 1; 400 } 401 } 402 /* Never went stable */ 403 return 0; 404 } 405 406 static int hpt3x2n_pci_clock(struct pci_dev *pdev) 407 { 408 unsigned long freq; 409 u32 fcnt; 410 unsigned long iobase = pci_resource_start(pdev, 4); 411 412 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ 413 if ((fcnt >> 12) != 0xABCDE) { 414 int i; 415 u16 sr; 416 u32 total = 0; 417 418 dev_warn(&pdev->dev, "BIOS clock data not set\n"); 419 420 /* This is the process the HPT371 BIOS is reported to use */ 421 for (i = 0; i < 128; i++) { 422 pci_read_config_word(pdev, 0x78, &sr); 423 total += sr & 0x1FF; 424 udelay(15); 425 } 426 fcnt = total / 128; 427 } 428 fcnt &= 0x1FF; 429 430 freq = (fcnt * 77) / 192; 431 432 /* Clamp to bands */ 433 if (freq < 40) 434 return 33; 435 if (freq < 45) 436 return 40; 437 if (freq < 55) 438 return 50; 439 return 66; 440 } 441 442 /** 443 * hpt3x2n_init_one - Initialise an HPT37X/302 444 * @dev: PCI device 445 * @id: Entry in match table 446 * 447 * Initialise an HPT3x2n device. There are some interesting complications 448 * here. Firstly the chip may report 366 and be one of several variants. 449 * Secondly all the timings depend on the clock for the chip which we must 450 * detect and look up 451 * 452 * This is the known chip mappings. It may be missing a couple of later 453 * releases. 454 * 455 * Chip version PCI Rev Notes 456 * HPT372 4 (HPT366) 5 Other driver 457 * HPT372N 4 (HPT366) 6 UDMA133 458 * HPT372 5 (HPT372) 1 Other driver 459 * HPT372N 5 (HPT372) 2 UDMA133 460 * HPT302 6 (HPT302) * Other driver 461 * HPT302N 6 (HPT302) > 1 UDMA133 462 * HPT371 7 (HPT371) * Other driver 463 * HPT371N 7 (HPT371) > 1 UDMA133 464 * HPT374 8 (HPT374) * Other driver 465 * HPT372N 9 (HPT372N) * UDMA133 466 * 467 * (1) UDMA133 support depends on the bus clock 468 */ 469 470 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) 471 { 472 /* HPT372N - UDMA133 */ 473 static const struct ata_port_info info_hpt372n = { 474 .flags = ATA_FLAG_SLAVE_POSS, 475 .pio_mask = ATA_PIO4, 476 .mwdma_mask = ATA_MWDMA2, 477 .udma_mask = ATA_UDMA6, 478 .port_ops = &hpt372n_port_ops 479 }; 480 /* HPT302N and HPT371N - UDMA133 */ 481 static const struct ata_port_info info_hpt3xxn = { 482 .flags = ATA_FLAG_SLAVE_POSS, 483 .pio_mask = ATA_PIO4, 484 .mwdma_mask = ATA_MWDMA2, 485 .udma_mask = ATA_UDMA6, 486 .port_ops = &hpt3xxn_port_ops 487 }; 488 const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL }; 489 u8 rev = dev->revision; 490 u8 irqmask; 491 unsigned int pci_mhz; 492 unsigned int f_low, f_high; 493 int adjust; 494 unsigned long iobase = pci_resource_start(dev, 4); 495 void *hpriv = (void *)USE_DPLL; 496 int rc; 497 498 rc = pcim_enable_device(dev); 499 if (rc) 500 return rc; 501 502 switch (dev->device) { 503 case PCI_DEVICE_ID_TTI_HPT366: 504 /* 372N if rev >= 6 */ 505 if (rev < 6) 506 return -ENODEV; 507 goto hpt372n; 508 case PCI_DEVICE_ID_TTI_HPT371: 509 /* 371N if rev >= 2 */ 510 if (rev < 2) 511 return -ENODEV; 512 break; 513 case PCI_DEVICE_ID_TTI_HPT372: 514 /* 372N if rev >= 2 */ 515 if (rev < 2) 516 return -ENODEV; 517 goto hpt372n; 518 case PCI_DEVICE_ID_TTI_HPT302: 519 /* 302N if rev >= 2 */ 520 if (rev < 2) 521 return -ENODEV; 522 break; 523 case PCI_DEVICE_ID_TTI_HPT372N: 524 hpt372n: 525 ppi[0] = &info_hpt372n; 526 break; 527 default: 528 dev_err(&dev->dev,"PCI table is bogus, please report (%d)\n", 529 dev->device); 530 return -ENODEV; 531 } 532 533 /* Ok so this is a chip we support */ 534 535 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 536 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 537 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 538 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 539 540 pci_read_config_byte(dev, 0x5A, &irqmask); 541 irqmask &= ~0x10; 542 pci_write_config_byte(dev, 0x5a, irqmask); 543 544 /* 545 * HPT371 chips physically have only one channel, the secondary one, 546 * but the primary channel registers do exist! Go figure... 547 * So, we manually disable the non-existing channel here 548 * (if the BIOS hasn't done this already). 549 */ 550 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { 551 u8 mcr1; 552 pci_read_config_byte(dev, 0x50, &mcr1); 553 mcr1 &= ~0x04; 554 pci_write_config_byte(dev, 0x50, mcr1); 555 } 556 557 /* 558 * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or 559 * 50 for UDMA100. Right now we always use 66 560 */ 561 562 pci_mhz = hpt3x2n_pci_clock(dev); 563 564 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ 565 f_high = f_low + 2; /* Tolerance */ 566 567 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); 568 /* PLL clock */ 569 pci_write_config_byte(dev, 0x5B, 0x21); 570 571 /* Unlike the 37x we don't try jiggling the frequency */ 572 for (adjust = 0; adjust < 8; adjust++) { 573 if (hpt3xn_calibrate_dpll(dev)) 574 break; 575 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); 576 } 577 if (adjust == 8) { 578 dev_err(&dev->dev, "DPLL did not stabilize!\n"); 579 return -ENODEV; 580 } 581 582 dev_info(&dev->dev, "bus clock %dMHz, using 66MHz DPLL\n", pci_mhz); 583 584 /* 585 * Set our private data up. We only need a few flags 586 * so we use it directly. 587 */ 588 if (pci_mhz > 60) 589 hpriv = (void *)(PCI66 | USE_DPLL); 590 591 /* 592 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 593 * the MISC. register to stretch the UltraDMA Tss timing. 594 * NOTE: This register is only writeable via I/O space. 595 */ 596 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) 597 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); 598 599 /* Now kick off ATA set up */ 600 return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0); 601 } 602 603 static const struct pci_device_id hpt3x2n[] = { 604 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 605 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 606 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 607 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 608 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, 609 610 { }, 611 }; 612 613 static struct pci_driver hpt3x2n_pci_driver = { 614 .name = DRV_NAME, 615 .id_table = hpt3x2n, 616 .probe = hpt3x2n_init_one, 617 .remove = ata_pci_remove_one 618 }; 619 620 module_pci_driver(hpt3x2n_pci_driver); 621 622 MODULE_AUTHOR("Alan Cox"); 623 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN"); 624 MODULE_LICENSE("GPL"); 625 MODULE_DEVICE_TABLE(pci, hpt3x2n); 626 MODULE_VERSION(DRV_VERSION); 627