1 /* 2 * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers. 3 * 4 * This driver is heavily based upon: 5 * 6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 7 * 8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 10 * Portions Copyright (C) 2003 Red Hat Inc 11 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. 12 * 13 * 14 * TODO 15 * Work out best PLL policy 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <scsi/scsi_host.h> 26 #include <linux/libata.h> 27 28 #define DRV_NAME "pata_hpt3x2n" 29 #define DRV_VERSION "0.3.15" 30 31 enum { 32 HPT_PCI_FAST = (1 << 31), 33 PCI66 = (1 << 1), 34 USE_DPLL = (1 << 0) 35 }; 36 37 struct hpt_clock { 38 u8 xfer_speed; 39 u32 timing; 40 }; 41 42 struct hpt_chip { 43 const char *name; 44 struct hpt_clock *clocks[3]; 45 }; 46 47 /* key for bus clock timings 48 * bit 49 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 50 * cycles = value + 1 51 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 52 * cycles = value + 1 53 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 54 * register access. 55 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 56 * register access. 57 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 58 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. 59 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. 60 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file 61 * register access. 62 * 28 UDMA enable. 63 * 29 DMA enable. 64 * 30 PIO_MST enable. If set, the chip is in bus master mode during 65 * PIO xfer. 66 * 31 FIFO enable. Only for PIO. 67 */ 68 69 /* 66MHz DPLL clocks */ 70 71 static struct hpt_clock hpt3x2n_clocks[] = { 72 { XFER_UDMA_7, 0x1c869c62 }, 73 { XFER_UDMA_6, 0x1c869c62 }, 74 { XFER_UDMA_5, 0x1c8a9c62 }, 75 { XFER_UDMA_4, 0x1c8a9c62 }, 76 { XFER_UDMA_3, 0x1c8e9c62 }, 77 { XFER_UDMA_2, 0x1c929c62 }, 78 { XFER_UDMA_1, 0x1c9a9c62 }, 79 { XFER_UDMA_0, 0x1c829c62 }, 80 81 { XFER_MW_DMA_2, 0x2c829c62 }, 82 { XFER_MW_DMA_1, 0x2c829c66 }, 83 { XFER_MW_DMA_0, 0x2c829d2e }, 84 85 { XFER_PIO_4, 0x0c829c62 }, 86 { XFER_PIO_3, 0x0c829c84 }, 87 { XFER_PIO_2, 0x0c829ca6 }, 88 { XFER_PIO_1, 0x0d029d26 }, 89 { XFER_PIO_0, 0x0d029d5e }, 90 }; 91 92 /** 93 * hpt3x2n_find_mode - reset the hpt3x2n bus 94 * @ap: ATA port 95 * @speed: transfer mode 96 * 97 * Return the 32bit register programming information for this channel 98 * that matches the speed provided. For the moment the clocks table 99 * is hard coded but easy to change. This will be needed if we use 100 * different DPLLs 101 */ 102 103 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) 104 { 105 struct hpt_clock *clocks = hpt3x2n_clocks; 106 107 while (clocks->xfer_speed) { 108 if (clocks->xfer_speed == speed) 109 return clocks->timing; 110 clocks++; 111 } 112 BUG(); 113 return 0xffffffffU; /* silence compiler warning */ 114 } 115 116 /** 117 * hpt372n_filter - mode selection filter 118 * @adev: ATA device 119 * @mask: mode mask 120 * 121 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 122 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 123 */ 124 static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask) 125 { 126 if (ata_id_is_sata(adev->id)) 127 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); 128 129 return mask; 130 } 131 132 /** 133 * hpt3x2n_cable_detect - Detect the cable type 134 * @ap: ATA port to detect on 135 * 136 * Return the cable type attached to this port 137 */ 138 139 static int hpt3x2n_cable_detect(struct ata_port *ap) 140 { 141 u8 scr2, ata66; 142 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 143 144 pci_read_config_byte(pdev, 0x5B, &scr2); 145 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 146 147 udelay(10); /* debounce */ 148 149 /* Cable register now active */ 150 pci_read_config_byte(pdev, 0x5A, &ata66); 151 /* Restore state */ 152 pci_write_config_byte(pdev, 0x5B, scr2); 153 154 if (ata66 & (2 >> ap->port_no)) 155 return ATA_CBL_PATA40; 156 else 157 return ATA_CBL_PATA80; 158 } 159 160 /** 161 * hpt3x2n_pre_reset - reset the hpt3x2n bus 162 * @link: ATA link to reset 163 * @deadline: deadline jiffies for the operation 164 * 165 * Perform the initial reset handling for the 3x2n series controllers. 166 * Reset the hardware and state machine, 167 */ 168 169 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) 170 { 171 struct ata_port *ap = link->ap; 172 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 173 174 /* Reset the state machine */ 175 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 176 udelay(100); 177 178 return ata_sff_prereset(link, deadline); 179 } 180 181 static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, 182 u8 mode) 183 { 184 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 185 u32 addr1, addr2; 186 u32 reg, timing, mask; 187 u8 fast; 188 189 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 190 addr2 = 0x51 + 4 * ap->port_no; 191 192 /* Fast interrupt prediction disable, hold off interrupt disable */ 193 pci_read_config_byte(pdev, addr2, &fast); 194 fast &= ~0x07; 195 pci_write_config_byte(pdev, addr2, fast); 196 197 /* Determine timing mask and find matching mode entry */ 198 if (mode < XFER_MW_DMA_0) 199 mask = 0xcfc3ffff; 200 else if (mode < XFER_UDMA_0) 201 mask = 0x31c001ff; 202 else 203 mask = 0x303c0000; 204 205 timing = hpt3x2n_find_mode(ap, mode); 206 207 pci_read_config_dword(pdev, addr1, ®); 208 reg = (reg & ~mask) | (timing & mask); 209 pci_write_config_dword(pdev, addr1, reg); 210 } 211 212 /** 213 * hpt3x2n_set_piomode - PIO setup 214 * @ap: ATA interface 215 * @adev: device on the interface 216 * 217 * Perform PIO mode setup. 218 */ 219 220 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) 221 { 222 hpt3x2n_set_mode(ap, adev, adev->pio_mode); 223 } 224 225 /** 226 * hpt3x2n_set_dmamode - DMA timing setup 227 * @ap: ATA interface 228 * @adev: Device being configured 229 * 230 * Set up the channel for MWDMA or UDMA modes. 231 */ 232 233 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) 234 { 235 hpt3x2n_set_mode(ap, adev, adev->dma_mode); 236 } 237 238 /** 239 * hpt3x2n_bmdma_end - DMA engine stop 240 * @qc: ATA command 241 * 242 * Clean up after the HPT3x2n and later DMA engine 243 */ 244 245 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) 246 { 247 struct ata_port *ap = qc->ap; 248 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 249 int mscreg = 0x50 + 2 * ap->port_no; 250 u8 bwsr_stat, msc_stat; 251 252 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 253 pci_read_config_byte(pdev, mscreg, &msc_stat); 254 if (bwsr_stat & (1 << ap->port_no)) 255 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 256 ata_bmdma_stop(qc); 257 } 258 259 /** 260 * hpt3x2n_set_clock - clock control 261 * @ap: ATA port 262 * @source: 0x21 or 0x23 for PLL or PCI sourced clock 263 * 264 * Switch the ATA bus clock between the PLL and PCI clock sources 265 * while correctly isolating the bus and resetting internal logic 266 * 267 * We must use the DPLL for 268 * - writing 269 * - second channel UDMA7 (SATA ports) or higher 270 * - 66MHz PCI 271 * 272 * or we will underclock the device and get reduced performance. 273 */ 274 275 static void hpt3x2n_set_clock(struct ata_port *ap, int source) 276 { 277 void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; 278 279 /* Tristate the bus */ 280 iowrite8(0x80, bmdma+0x73); 281 iowrite8(0x80, bmdma+0x77); 282 283 /* Switch clock and reset channels */ 284 iowrite8(source, bmdma+0x7B); 285 iowrite8(0xC0, bmdma+0x79); 286 287 /* Reset state machines, avoid enabling the disabled channels */ 288 iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); 289 iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); 290 291 /* Complete reset */ 292 iowrite8(0x00, bmdma+0x79); 293 294 /* Reconnect channels to bus */ 295 iowrite8(0x00, bmdma+0x73); 296 iowrite8(0x00, bmdma+0x77); 297 } 298 299 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) 300 { 301 long flags = (long)ap->host->private_data; 302 303 /* See if we should use the DPLL */ 304 if (writing) 305 return USE_DPLL; /* Needed for write */ 306 if (flags & PCI66) 307 return USE_DPLL; /* Needed at 66Mhz */ 308 return 0; 309 } 310 311 static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) 312 { 313 struct ata_port *ap = qc->ap; 314 struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; 315 int rc, flags = (long)ap->host->private_data; 316 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); 317 318 /* First apply the usual rules */ 319 rc = ata_std_qc_defer(qc); 320 if (rc != 0) 321 return rc; 322 323 if ((flags & USE_DPLL) != dpll && alt->qc_active) 324 return ATA_DEFER_PORT; 325 return 0; 326 } 327 328 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) 329 { 330 struct ata_port *ap = qc->ap; 331 int flags = (long)ap->host->private_data; 332 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); 333 334 if ((flags & USE_DPLL) != dpll) { 335 flags &= ~USE_DPLL; 336 flags |= dpll; 337 ap->host->private_data = (void *)(long)flags; 338 339 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); 340 } 341 return ata_bmdma_qc_issue(qc); 342 } 343 344 static struct scsi_host_template hpt3x2n_sht = { 345 ATA_BMDMA_SHT(DRV_NAME), 346 }; 347 348 /* 349 * Configuration for HPT302N/371N. 350 */ 351 352 static struct ata_port_operations hpt3xxn_port_ops = { 353 .inherits = &ata_bmdma_port_ops, 354 355 .bmdma_stop = hpt3x2n_bmdma_stop, 356 357 .qc_defer = hpt3x2n_qc_defer, 358 .qc_issue = hpt3x2n_qc_issue, 359 360 .cable_detect = hpt3x2n_cable_detect, 361 .set_piomode = hpt3x2n_set_piomode, 362 .set_dmamode = hpt3x2n_set_dmamode, 363 .prereset = hpt3x2n_pre_reset, 364 }; 365 366 /* 367 * Configuration for HPT372N. Same as 302N/371N but we have a mode filter. 368 */ 369 370 static struct ata_port_operations hpt372n_port_ops = { 371 .inherits = &hpt3xxn_port_ops, 372 .mode_filter = &hpt372n_filter, 373 }; 374 375 /** 376 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop 377 * @dev: PCI device 378 * 379 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this 380 * succeeds 381 */ 382 383 static int hpt3xn_calibrate_dpll(struct pci_dev *dev) 384 { 385 u8 reg5b; 386 u32 reg5c; 387 int tries; 388 389 for (tries = 0; tries < 0x5000; tries++) { 390 udelay(50); 391 pci_read_config_byte(dev, 0x5b, ®5b); 392 if (reg5b & 0x80) { 393 /* See if it stays set */ 394 for (tries = 0; tries < 0x1000; tries++) { 395 pci_read_config_byte(dev, 0x5b, ®5b); 396 /* Failed ? */ 397 if ((reg5b & 0x80) == 0) 398 return 0; 399 } 400 /* Turn off tuning, we have the DPLL set */ 401 pci_read_config_dword(dev, 0x5c, ®5c); 402 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); 403 return 1; 404 } 405 } 406 /* Never went stable */ 407 return 0; 408 } 409 410 static int hpt3x2n_pci_clock(struct pci_dev *pdev) 411 { 412 unsigned long freq; 413 u32 fcnt; 414 unsigned long iobase = pci_resource_start(pdev, 4); 415 416 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ 417 if ((fcnt >> 12) != 0xABCDE) { 418 int i; 419 u16 sr; 420 u32 total = 0; 421 422 pr_warn("BIOS clock data not set\n"); 423 424 /* This is the process the HPT371 BIOS is reported to use */ 425 for (i = 0; i < 128; i++) { 426 pci_read_config_word(pdev, 0x78, &sr); 427 total += sr & 0x1FF; 428 udelay(15); 429 } 430 fcnt = total / 128; 431 } 432 fcnt &= 0x1FF; 433 434 freq = (fcnt * 77) / 192; 435 436 /* Clamp to bands */ 437 if (freq < 40) 438 return 33; 439 if (freq < 45) 440 return 40; 441 if (freq < 55) 442 return 50; 443 return 66; 444 } 445 446 /** 447 * hpt3x2n_init_one - Initialise an HPT37X/302 448 * @dev: PCI device 449 * @id: Entry in match table 450 * 451 * Initialise an HPT3x2n device. There are some interesting complications 452 * here. Firstly the chip may report 366 and be one of several variants. 453 * Secondly all the timings depend on the clock for the chip which we must 454 * detect and look up 455 * 456 * This is the known chip mappings. It may be missing a couple of later 457 * releases. 458 * 459 * Chip version PCI Rev Notes 460 * HPT372 4 (HPT366) 5 Other driver 461 * HPT372N 4 (HPT366) 6 UDMA133 462 * HPT372 5 (HPT372) 1 Other driver 463 * HPT372N 5 (HPT372) 2 UDMA133 464 * HPT302 6 (HPT302) * Other driver 465 * HPT302N 6 (HPT302) > 1 UDMA133 466 * HPT371 7 (HPT371) * Other driver 467 * HPT371N 7 (HPT371) > 1 UDMA133 468 * HPT374 8 (HPT374) * Other driver 469 * HPT372N 9 (HPT372N) * UDMA133 470 * 471 * (1) UDMA133 support depends on the bus clock 472 */ 473 474 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) 475 { 476 /* HPT372N - UDMA133 */ 477 static const struct ata_port_info info_hpt372n = { 478 .flags = ATA_FLAG_SLAVE_POSS, 479 .pio_mask = ATA_PIO4, 480 .mwdma_mask = ATA_MWDMA2, 481 .udma_mask = ATA_UDMA6, 482 .port_ops = &hpt372n_port_ops 483 }; 484 /* HPT302N and HPT371N - UDMA133 */ 485 static const struct ata_port_info info_hpt3xxn = { 486 .flags = ATA_FLAG_SLAVE_POSS, 487 .pio_mask = ATA_PIO4, 488 .mwdma_mask = ATA_MWDMA2, 489 .udma_mask = ATA_UDMA6, 490 .port_ops = &hpt3xxn_port_ops 491 }; 492 const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL }; 493 u8 rev = dev->revision; 494 u8 irqmask; 495 unsigned int pci_mhz; 496 unsigned int f_low, f_high; 497 int adjust; 498 unsigned long iobase = pci_resource_start(dev, 4); 499 void *hpriv = (void *)USE_DPLL; 500 int rc; 501 502 rc = pcim_enable_device(dev); 503 if (rc) 504 return rc; 505 506 switch (dev->device) { 507 case PCI_DEVICE_ID_TTI_HPT366: 508 /* 372N if rev >= 6 */ 509 if (rev < 6) 510 return -ENODEV; 511 goto hpt372n; 512 case PCI_DEVICE_ID_TTI_HPT371: 513 /* 371N if rev >= 2 */ 514 if (rev < 2) 515 return -ENODEV; 516 break; 517 case PCI_DEVICE_ID_TTI_HPT372: 518 /* 372N if rev >= 2 */ 519 if (rev < 2) 520 return -ENODEV; 521 goto hpt372n; 522 case PCI_DEVICE_ID_TTI_HPT302: 523 /* 302N if rev >= 2 */ 524 if (rev < 2) 525 return -ENODEV; 526 break; 527 case PCI_DEVICE_ID_TTI_HPT372N: 528 hpt372n: 529 ppi[0] = &info_hpt372n; 530 break; 531 default: 532 pr_err("PCI table is bogus, please report (%d)\n", dev->device); 533 return -ENODEV; 534 } 535 536 /* Ok so this is a chip we support */ 537 538 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 539 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 540 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 541 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 542 543 pci_read_config_byte(dev, 0x5A, &irqmask); 544 irqmask &= ~0x10; 545 pci_write_config_byte(dev, 0x5a, irqmask); 546 547 /* 548 * HPT371 chips physically have only one channel, the secondary one, 549 * but the primary channel registers do exist! Go figure... 550 * So, we manually disable the non-existing channel here 551 * (if the BIOS hasn't done this already). 552 */ 553 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { 554 u8 mcr1; 555 pci_read_config_byte(dev, 0x50, &mcr1); 556 mcr1 &= ~0x04; 557 pci_write_config_byte(dev, 0x50, mcr1); 558 } 559 560 /* 561 * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or 562 * 50 for UDMA100. Right now we always use 66 563 */ 564 565 pci_mhz = hpt3x2n_pci_clock(dev); 566 567 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ 568 f_high = f_low + 2; /* Tolerance */ 569 570 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); 571 /* PLL clock */ 572 pci_write_config_byte(dev, 0x5B, 0x21); 573 574 /* Unlike the 37x we don't try jiggling the frequency */ 575 for (adjust = 0; adjust < 8; adjust++) { 576 if (hpt3xn_calibrate_dpll(dev)) 577 break; 578 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); 579 } 580 if (adjust == 8) { 581 pr_err("DPLL did not stabilize!\n"); 582 return -ENODEV; 583 } 584 585 pr_info("bus clock %dMHz, using 66MHz DPLL\n", pci_mhz); 586 587 /* 588 * Set our private data up. We only need a few flags 589 * so we use it directly. 590 */ 591 if (pci_mhz > 60) 592 hpriv = (void *)(PCI66 | USE_DPLL); 593 594 /* 595 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 596 * the MISC. register to stretch the UltraDMA Tss timing. 597 * NOTE: This register is only writeable via I/O space. 598 */ 599 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) 600 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); 601 602 /* Now kick off ATA set up */ 603 return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0); 604 } 605 606 static const struct pci_device_id hpt3x2n[] = { 607 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 608 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 610 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 611 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, 612 613 { }, 614 }; 615 616 static struct pci_driver hpt3x2n_pci_driver = { 617 .name = DRV_NAME, 618 .id_table = hpt3x2n, 619 .probe = hpt3x2n_init_one, 620 .remove = ata_pci_remove_one 621 }; 622 623 module_pci_driver(hpt3x2n_pci_driver); 624 625 MODULE_AUTHOR("Alan Cox"); 626 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN"); 627 MODULE_LICENSE("GPL"); 628 MODULE_DEVICE_TABLE(pci, hpt3x2n); 629 MODULE_VERSION(DRV_VERSION); 630