1 /* 2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers. 3 * 4 * This driver is heavily based upon: 5 * 6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 7 * 8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 10 * Portions Copyright (C) 2003 Red Hat Inc 11 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc. 12 * 13 * 14 * TODO 15 * Work out best PLL policy 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <scsi/scsi_host.h> 25 #include <linux/libata.h> 26 27 #define DRV_NAME "pata_hpt3x2n" 28 #define DRV_VERSION "0.3.3" 29 30 enum { 31 HPT_PCI_FAST = (1 << 31), 32 PCI66 = (1 << 1), 33 USE_DPLL = (1 << 0) 34 }; 35 36 struct hpt_clock { 37 u8 xfer_speed; 38 u32 timing; 39 }; 40 41 struct hpt_chip { 42 const char *name; 43 struct hpt_clock *clocks[3]; 44 }; 45 46 /* key for bus clock timings 47 * bit 48 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW 49 * DMA. cycles = value + 1 50 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW 51 * DMA. cycles = value + 1 52 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file 53 * register access. 54 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file 55 * register access. 56 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. 57 * during task file register access. 58 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA 59 * xfer. 60 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task 61 * register access. 62 * 28 UDMA enable 63 * 29 DMA enable 64 * 30 PIO_MST enable. if set, the chip is in bus master mode during 65 * PIO. 66 * 31 FIFO enable. 67 */ 68 69 /* 66MHz DPLL clocks */ 70 71 static struct hpt_clock hpt3x2n_clocks[] = { 72 { XFER_UDMA_7, 0x1c869c62 }, 73 { XFER_UDMA_6, 0x1c869c62 }, 74 { XFER_UDMA_5, 0x1c8a9c62 }, 75 { XFER_UDMA_4, 0x1c8a9c62 }, 76 { XFER_UDMA_3, 0x1c8e9c62 }, 77 { XFER_UDMA_2, 0x1c929c62 }, 78 { XFER_UDMA_1, 0x1c9a9c62 }, 79 { XFER_UDMA_0, 0x1c829c62 }, 80 81 { XFER_MW_DMA_2, 0x2c829c62 }, 82 { XFER_MW_DMA_1, 0x2c829c66 }, 83 { XFER_MW_DMA_0, 0x2c829d2c }, 84 85 { XFER_PIO_4, 0x0c829c62 }, 86 { XFER_PIO_3, 0x0c829c84 }, 87 { XFER_PIO_2, 0x0c829ca6 }, 88 { XFER_PIO_1, 0x0d029d26 }, 89 { XFER_PIO_0, 0x0d029d5e }, 90 { 0, 0x0d029d5e } 91 }; 92 93 /** 94 * hpt3x2n_find_mode - reset the hpt3x2n bus 95 * @ap: ATA port 96 * @speed: transfer mode 97 * 98 * Return the 32bit register programming information for this channel 99 * that matches the speed provided. For the moment the clocks table 100 * is hard coded but easy to change. This will be needed if we use 101 * different DPLLs 102 */ 103 104 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) 105 { 106 struct hpt_clock *clocks = hpt3x2n_clocks; 107 108 while(clocks->xfer_speed) { 109 if (clocks->xfer_speed == speed) 110 return clocks->timing; 111 clocks++; 112 } 113 BUG(); 114 return 0xffffffffU; /* silence compiler warning */ 115 } 116 117 /** 118 * hpt3x2n_cable_detect - Detect the cable type 119 * @ap: ATA port to detect on 120 * 121 * Return the cable type attached to this port 122 */ 123 124 static int hpt3x2n_cable_detect(struct ata_port *ap) 125 { 126 u8 scr2, ata66; 127 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 128 129 pci_read_config_byte(pdev, 0x5B, &scr2); 130 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 131 /* Cable register now active */ 132 pci_read_config_byte(pdev, 0x5A, &ata66); 133 /* Restore state */ 134 pci_write_config_byte(pdev, 0x5B, scr2); 135 136 if (ata66 & (1 << ap->port_no)) 137 return ATA_CBL_PATA40; 138 else 139 return ATA_CBL_PATA80; 140 } 141 142 /** 143 * hpt3x2n_pre_reset - reset the hpt3x2n bus 144 * @ap: ATA port to reset 145 * @deadline: deadline jiffies for the operation 146 * 147 * Perform the initial reset handling for the 3x2n series controllers. 148 * Reset the hardware and state machine, 149 */ 150 151 static int hpt3xn_pre_reset(struct ata_port *ap, unsigned long deadline) 152 { 153 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 154 /* Reset the state machine */ 155 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 156 udelay(100); 157 158 return ata_std_prereset(ap, deadline); 159 } 160 161 /** 162 * hpt3x2n_error_handler - probe the hpt3x2n bus 163 * @ap: ATA port to reset 164 * 165 * Perform the probe reset handling for the 3x2N 166 */ 167 168 static void hpt3x2n_error_handler(struct ata_port *ap) 169 { 170 ata_bmdma_drive_eh(ap, hpt3xn_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 171 } 172 173 /** 174 * hpt3x2n_set_piomode - PIO setup 175 * @ap: ATA interface 176 * @adev: device on the interface 177 * 178 * Perform PIO mode setup. 179 */ 180 181 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) 182 { 183 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 184 u32 addr1, addr2; 185 u32 reg; 186 u32 mode; 187 u8 fast; 188 189 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 190 addr2 = 0x51 + 4 * ap->port_no; 191 192 /* Fast interrupt prediction disable, hold off interrupt disable */ 193 pci_read_config_byte(pdev, addr2, &fast); 194 fast &= ~0x07; 195 pci_write_config_byte(pdev, addr2, fast); 196 197 pci_read_config_dword(pdev, addr1, ®); 198 mode = hpt3x2n_find_mode(ap, adev->pio_mode); 199 mode &= ~0x8000000; /* No FIFO in PIO */ 200 mode &= ~0x30070000; /* Leave config bits alone */ 201 reg &= 0x30070000; /* Strip timing bits */ 202 pci_write_config_dword(pdev, addr1, reg | mode); 203 } 204 205 /** 206 * hpt3x2n_set_dmamode - DMA timing setup 207 * @ap: ATA interface 208 * @adev: Device being configured 209 * 210 * Set up the channel for MWDMA or UDMA modes. Much the same as with 211 * PIO, load the mode number and then set MWDMA or UDMA flag. 212 */ 213 214 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) 215 { 216 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 217 u32 addr1, addr2; 218 u32 reg; 219 u32 mode; 220 u8 fast; 221 222 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 223 addr2 = 0x51 + 4 * ap->port_no; 224 225 /* Fast interrupt prediction disable, hold off interrupt disable */ 226 pci_read_config_byte(pdev, addr2, &fast); 227 fast &= ~0x07; 228 pci_write_config_byte(pdev, addr2, fast); 229 230 pci_read_config_dword(pdev, addr1, ®); 231 mode = hpt3x2n_find_mode(ap, adev->dma_mode); 232 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */ 233 mode &= ~0xC0000000; /* Leave config bits alone */ 234 reg &= 0xC0000000; /* Strip timing bits */ 235 pci_write_config_dword(pdev, addr1, reg | mode); 236 } 237 238 /** 239 * hpt3x2n_bmdma_end - DMA engine stop 240 * @qc: ATA command 241 * 242 * Clean up after the HPT3x2n and later DMA engine 243 */ 244 245 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) 246 { 247 struct ata_port *ap = qc->ap; 248 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 249 int mscreg = 0x50 + 2 * ap->port_no; 250 u8 bwsr_stat, msc_stat; 251 252 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 253 pci_read_config_byte(pdev, mscreg, &msc_stat); 254 if (bwsr_stat & (1 << ap->port_no)) 255 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 256 ata_bmdma_stop(qc); 257 } 258 259 /** 260 * hpt3x2n_set_clock - clock control 261 * @ap: ATA port 262 * @source: 0x21 or 0x23 for PLL or PCI sourced clock 263 * 264 * Switch the ATA bus clock between the PLL and PCI clock sources 265 * while correctly isolating the bus and resetting internal logic 266 * 267 * We must use the DPLL for 268 * - writing 269 * - second channel UDMA7 (SATA ports) or higher 270 * - 66MHz PCI 271 * 272 * or we will underclock the device and get reduced performance. 273 */ 274 275 static void hpt3x2n_set_clock(struct ata_port *ap, int source) 276 { 277 void __iomem *bmdma = ap->ioaddr.bmdma_addr; 278 279 /* Tristate the bus */ 280 iowrite8(0x80, bmdma+0x73); 281 iowrite8(0x80, bmdma+0x77); 282 283 /* Switch clock and reset channels */ 284 iowrite8(source, bmdma+0x7B); 285 iowrite8(0xC0, bmdma+0x79); 286 287 /* Reset state machines */ 288 iowrite8(0x37, bmdma+0x70); 289 iowrite8(0x37, bmdma+0x74); 290 291 /* Complete reset */ 292 iowrite8(0x00, bmdma+0x79); 293 294 /* Reconnect channels to bus */ 295 iowrite8(0x00, bmdma+0x73); 296 iowrite8(0x00, bmdma+0x77); 297 } 298 299 /* Check if our partner interface is busy */ 300 301 static int hpt3x2n_pair_idle(struct ata_port *ap) 302 { 303 struct ata_host *host = ap->host; 304 struct ata_port *pair = host->ports[ap->port_no ^ 1]; 305 306 if (pair->hsm_task_state == HSM_ST_IDLE) 307 return 1; 308 return 0; 309 } 310 311 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) 312 { 313 long flags = (long)ap->host->private_data; 314 /* See if we should use the DPLL */ 315 if (writing) 316 return USE_DPLL; /* Needed for write */ 317 if (flags & PCI66) 318 return USE_DPLL; /* Needed at 66Mhz */ 319 return 0; 320 } 321 322 static unsigned int hpt3x2n_qc_issue_prot(struct ata_queued_cmd *qc) 323 { 324 struct ata_taskfile *tf = &qc->tf; 325 struct ata_port *ap = qc->ap; 326 int flags = (long)ap->host->private_data; 327 328 if (hpt3x2n_pair_idle(ap)) { 329 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE)); 330 if ((flags & USE_DPLL) != dpll) { 331 if (dpll == 1) 332 hpt3x2n_set_clock(ap, 0x21); 333 else 334 hpt3x2n_set_clock(ap, 0x23); 335 } 336 } 337 return ata_qc_issue_prot(qc); 338 } 339 340 static struct scsi_host_template hpt3x2n_sht = { 341 .module = THIS_MODULE, 342 .name = DRV_NAME, 343 .ioctl = ata_scsi_ioctl, 344 .queuecommand = ata_scsi_queuecmd, 345 .can_queue = ATA_DEF_QUEUE, 346 .this_id = ATA_SHT_THIS_ID, 347 .sg_tablesize = LIBATA_MAX_PRD, 348 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 349 .emulated = ATA_SHT_EMULATED, 350 .use_clustering = ATA_SHT_USE_CLUSTERING, 351 .proc_name = DRV_NAME, 352 .dma_boundary = ATA_DMA_BOUNDARY, 353 .slave_configure = ata_scsi_slave_config, 354 .slave_destroy = ata_scsi_slave_destroy, 355 .bios_param = ata_std_bios_param, 356 }; 357 358 /* 359 * Configuration for HPT3x2n. 360 */ 361 362 static struct ata_port_operations hpt3x2n_port_ops = { 363 .port_disable = ata_port_disable, 364 .set_piomode = hpt3x2n_set_piomode, 365 .set_dmamode = hpt3x2n_set_dmamode, 366 .mode_filter = ata_pci_default_filter, 367 368 .tf_load = ata_tf_load, 369 .tf_read = ata_tf_read, 370 .check_status = ata_check_status, 371 .exec_command = ata_exec_command, 372 .dev_select = ata_std_dev_select, 373 374 .freeze = ata_bmdma_freeze, 375 .thaw = ata_bmdma_thaw, 376 .error_handler = hpt3x2n_error_handler, 377 .post_internal_cmd = ata_bmdma_post_internal_cmd, 378 .cable_detect = hpt3x2n_cable_detect, 379 380 .bmdma_setup = ata_bmdma_setup, 381 .bmdma_start = ata_bmdma_start, 382 .bmdma_stop = hpt3x2n_bmdma_stop, 383 .bmdma_status = ata_bmdma_status, 384 385 .qc_prep = ata_qc_prep, 386 .qc_issue = hpt3x2n_qc_issue_prot, 387 388 .data_xfer = ata_data_xfer, 389 390 .irq_handler = ata_interrupt, 391 .irq_clear = ata_bmdma_irq_clear, 392 .irq_on = ata_irq_on, 393 .irq_ack = ata_irq_ack, 394 395 .port_start = ata_port_start, 396 }; 397 398 /** 399 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop 400 * @dev: PCI device 401 * 402 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this 403 * succeeds 404 */ 405 406 static int hpt3xn_calibrate_dpll(struct pci_dev *dev) 407 { 408 u8 reg5b; 409 u32 reg5c; 410 int tries; 411 412 for(tries = 0; tries < 0x5000; tries++) { 413 udelay(50); 414 pci_read_config_byte(dev, 0x5b, ®5b); 415 if (reg5b & 0x80) { 416 /* See if it stays set */ 417 for(tries = 0; tries < 0x1000; tries ++) { 418 pci_read_config_byte(dev, 0x5b, ®5b); 419 /* Failed ? */ 420 if ((reg5b & 0x80) == 0) 421 return 0; 422 } 423 /* Turn off tuning, we have the DPLL set */ 424 pci_read_config_dword(dev, 0x5c, ®5c); 425 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); 426 return 1; 427 } 428 } 429 /* Never went stable */ 430 return 0; 431 } 432 433 static int hpt3x2n_pci_clock(struct pci_dev *pdev) 434 { 435 unsigned long freq; 436 u32 fcnt; 437 unsigned long iobase = pci_resource_start(pdev, 4); 438 439 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ 440 if ((fcnt >> 12) != 0xABCDE) { 441 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n"); 442 return 33; /* Not BIOS set */ 443 } 444 fcnt &= 0x1FF; 445 446 freq = (fcnt * 77) / 192; 447 448 /* Clamp to bands */ 449 if (freq < 40) 450 return 33; 451 if (freq < 45) 452 return 40; 453 if (freq < 55) 454 return 50; 455 return 66; 456 } 457 458 /** 459 * hpt3x2n_init_one - Initialise an HPT37X/302 460 * @dev: PCI device 461 * @id: Entry in match table 462 * 463 * Initialise an HPT3x2n device. There are some interesting complications 464 * here. Firstly the chip may report 366 and be one of several variants. 465 * Secondly all the timings depend on the clock for the chip which we must 466 * detect and look up 467 * 468 * This is the known chip mappings. It may be missing a couple of later 469 * releases. 470 * 471 * Chip version PCI Rev Notes 472 * HPT372 4 (HPT366) 5 Other driver 473 * HPT372N 4 (HPT366) 6 UDMA133 474 * HPT372 5 (HPT372) 1 Other driver 475 * HPT372N 5 (HPT372) 2 UDMA133 476 * HPT302 6 (HPT302) * Other driver 477 * HPT302N 6 (HPT302) > 1 UDMA133 478 * HPT371 7 (HPT371) * Other driver 479 * HPT371N 7 (HPT371) > 1 UDMA133 480 * HPT374 8 (HPT374) * Other driver 481 * HPT372N 9 (HPT372N) * UDMA133 482 * 483 * (1) UDMA133 support depends on the bus clock 484 * 485 * To pin down HPT371N 486 */ 487 488 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) 489 { 490 /* HPT372N and friends - UDMA133 */ 491 static const struct ata_port_info info = { 492 .sht = &hpt3x2n_sht, 493 .flags = ATA_FLAG_SLAVE_POSS, 494 .pio_mask = 0x1f, 495 .mwdma_mask = 0x07, 496 .udma_mask = ATA_UDMA6, 497 .port_ops = &hpt3x2n_port_ops 498 }; 499 struct ata_port_info port = info; 500 const struct ata_port_info *ppi[] = { &port, NULL }; 501 502 u8 irqmask; 503 u32 class_rev; 504 505 unsigned int pci_mhz; 506 unsigned int f_low, f_high; 507 int adjust; 508 unsigned long iobase = pci_resource_start(dev, 4); 509 510 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 511 class_rev &= 0xFF; 512 513 switch(dev->device) { 514 case PCI_DEVICE_ID_TTI_HPT366: 515 if (class_rev < 6) 516 return -ENODEV; 517 break; 518 case PCI_DEVICE_ID_TTI_HPT371: 519 if (class_rev < 2) 520 return -ENODEV; 521 /* 371N if rev > 1 */ 522 break; 523 case PCI_DEVICE_ID_TTI_HPT372: 524 /* 372N if rev >= 2*/ 525 if (class_rev < 2) 526 return -ENODEV; 527 break; 528 case PCI_DEVICE_ID_TTI_HPT302: 529 if (class_rev < 2) 530 return -ENODEV; 531 break; 532 case PCI_DEVICE_ID_TTI_HPT372N: 533 break; 534 default: 535 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device); 536 return -ENODEV; 537 } 538 539 /* Ok so this is a chip we support */ 540 541 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 542 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 543 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 544 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 545 546 pci_read_config_byte(dev, 0x5A, &irqmask); 547 irqmask &= ~0x10; 548 pci_write_config_byte(dev, 0x5a, irqmask); 549 550 /* 551 * HPT371 chips physically have only one channel, the secondary one, 552 * but the primary channel registers do exist! Go figure... 553 * So, we manually disable the non-existing channel here 554 * (if the BIOS hasn't done this already). 555 */ 556 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { 557 u8 mcr1; 558 pci_read_config_byte(dev, 0x50, &mcr1); 559 mcr1 &= ~0x04; 560 pci_write_config_byte(dev, 0x50, mcr1); 561 } 562 563 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or 564 50 for UDMA100. Right now we always use 66 */ 565 566 pci_mhz = hpt3x2n_pci_clock(dev); 567 568 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ 569 f_high = f_low + 2; /* Tolerance */ 570 571 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); 572 /* PLL clock */ 573 pci_write_config_byte(dev, 0x5B, 0x21); 574 575 /* Unlike the 37x we don't try jiggling the frequency */ 576 for(adjust = 0; adjust < 8; adjust++) { 577 if (hpt3xn_calibrate_dpll(dev)) 578 break; 579 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); 580 } 581 if (adjust == 8) { 582 printk(KERN_WARNING "hpt3x2n: DPLL did not stabilize.\n"); 583 return -ENODEV; 584 } 585 586 /* Set our private data up. We only need a few flags so we use 587 it directly */ 588 port.private_data = NULL; 589 if (pci_mhz > 60) { 590 port.private_data = (void *)PCI66; 591 /* 592 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 593 * the MISC. register to stretch the UltraDMA Tss timing. 594 * NOTE: This register is only writeable via I/O space. 595 */ 596 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) 597 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); 598 } 599 600 /* Now kick off ATA set up */ 601 return ata_pci_init_one(dev, ppi); 602 } 603 604 static const struct pci_device_id hpt3x2n[] = { 605 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 606 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 607 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 608 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, 610 611 { }, 612 }; 613 614 static struct pci_driver hpt3x2n_pci_driver = { 615 .name = DRV_NAME, 616 .id_table = hpt3x2n, 617 .probe = hpt3x2n_init_one, 618 .remove = ata_pci_remove_one 619 }; 620 621 static int __init hpt3x2n_init(void) 622 { 623 return pci_register_driver(&hpt3x2n_pci_driver); 624 } 625 626 static void __exit hpt3x2n_exit(void) 627 { 628 pci_unregister_driver(&hpt3x2n_pci_driver); 629 } 630 631 MODULE_AUTHOR("Alan Cox"); 632 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x"); 633 MODULE_LICENSE("GPL"); 634 MODULE_DEVICE_TABLE(pci, hpt3x2n); 635 MODULE_VERSION(DRV_VERSION); 636 637 module_init(hpt3x2n_init); 638 module_exit(hpt3x2n_exit); 639