1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers. 4 * 5 * This driver is heavily based upon: 6 * 7 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 8 * 9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 10 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 11 * Portions Copyright (C) 2003 Red Hat Inc 12 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. 13 * 14 * 15 * TODO 16 * Work out best PLL policy 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/blkdev.h> 22 #include <linux/delay.h> 23 #include <scsi/scsi_host.h> 24 #include <linux/libata.h> 25 26 #define DRV_NAME "pata_hpt3x2n" 27 #define DRV_VERSION "0.3.15" 28 29 enum { 30 HPT_PCI_FAST = (1 << 31), 31 PCI66 = (1 << 1), 32 USE_DPLL = (1 << 0) 33 }; 34 35 struct hpt_clock { 36 u8 xfer_speed; 37 u32 timing; 38 }; 39 40 struct hpt_chip { 41 const char *name; 42 struct hpt_clock *clocks[3]; 43 }; 44 45 /* key for bus clock timings 46 * bit 47 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 48 * cycles = value + 1 49 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 50 * cycles = value + 1 51 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 52 * register access. 53 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 54 * register access. 55 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 56 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. 57 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. 58 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file 59 * register access. 60 * 28 UDMA enable. 61 * 29 DMA enable. 62 * 30 PIO_MST enable. If set, the chip is in bus master mode during 63 * PIO xfer. 64 * 31 FIFO enable. Only for PIO. 65 */ 66 67 /* 66MHz DPLL clocks */ 68 69 static struct hpt_clock hpt3x2n_clocks[] = { 70 { XFER_UDMA_7, 0x1c869c62 }, 71 { XFER_UDMA_6, 0x1c869c62 }, 72 { XFER_UDMA_5, 0x1c8a9c62 }, 73 { XFER_UDMA_4, 0x1c8a9c62 }, 74 { XFER_UDMA_3, 0x1c8e9c62 }, 75 { XFER_UDMA_2, 0x1c929c62 }, 76 { XFER_UDMA_1, 0x1c9a9c62 }, 77 { XFER_UDMA_0, 0x1c829c62 }, 78 79 { XFER_MW_DMA_2, 0x2c829c62 }, 80 { XFER_MW_DMA_1, 0x2c829c66 }, 81 { XFER_MW_DMA_0, 0x2c829d2e }, 82 83 { XFER_PIO_4, 0x0c829c62 }, 84 { XFER_PIO_3, 0x0c829c84 }, 85 { XFER_PIO_2, 0x0c829ca6 }, 86 { XFER_PIO_1, 0x0d029d26 }, 87 { XFER_PIO_0, 0x0d029d5e }, 88 }; 89 90 /** 91 * hpt3x2n_find_mode - reset the hpt3x2n bus 92 * @ap: ATA port 93 * @speed: transfer mode 94 * 95 * Return the 32bit register programming information for this channel 96 * that matches the speed provided. For the moment the clocks table 97 * is hard coded but easy to change. This will be needed if we use 98 * different DPLLs 99 */ 100 101 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) 102 { 103 struct hpt_clock *clocks = hpt3x2n_clocks; 104 105 while (clocks->xfer_speed) { 106 if (clocks->xfer_speed == speed) 107 return clocks->timing; 108 clocks++; 109 } 110 BUG(); 111 return 0xffffffffU; /* silence compiler warning */ 112 } 113 114 /** 115 * hpt372n_filter - mode selection filter 116 * @adev: ATA device 117 * @mask: mode mask 118 * 119 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 120 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 121 */ 122 static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask) 123 { 124 if (ata_id_is_sata(adev->id)) 125 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); 126 127 return mask; 128 } 129 130 /** 131 * hpt3x2n_cable_detect - Detect the cable type 132 * @ap: ATA port to detect on 133 * 134 * Return the cable type attached to this port 135 */ 136 137 static int hpt3x2n_cable_detect(struct ata_port *ap) 138 { 139 u8 scr2, ata66; 140 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 141 142 pci_read_config_byte(pdev, 0x5B, &scr2); 143 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 144 145 udelay(10); /* debounce */ 146 147 /* Cable register now active */ 148 pci_read_config_byte(pdev, 0x5A, &ata66); 149 /* Restore state */ 150 pci_write_config_byte(pdev, 0x5B, scr2); 151 152 if (ata66 & (2 >> ap->port_no)) 153 return ATA_CBL_PATA40; 154 else 155 return ATA_CBL_PATA80; 156 } 157 158 /** 159 * hpt3x2n_pre_reset - reset the hpt3x2n bus 160 * @link: ATA link to reset 161 * @deadline: deadline jiffies for the operation 162 * 163 * Perform the initial reset handling for the 3x2n series controllers. 164 * Reset the hardware and state machine, 165 */ 166 167 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) 168 { 169 struct ata_port *ap = link->ap; 170 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 171 172 /* Reset the state machine */ 173 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 174 udelay(100); 175 176 return ata_sff_prereset(link, deadline); 177 } 178 179 static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, 180 u8 mode) 181 { 182 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 183 u32 addr1, addr2; 184 u32 reg, timing, mask; 185 u8 fast; 186 187 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 188 addr2 = 0x51 + 4 * ap->port_no; 189 190 /* Fast interrupt prediction disable, hold off interrupt disable */ 191 pci_read_config_byte(pdev, addr2, &fast); 192 fast &= ~0x07; 193 pci_write_config_byte(pdev, addr2, fast); 194 195 /* Determine timing mask and find matching mode entry */ 196 if (mode < XFER_MW_DMA_0) 197 mask = 0xcfc3ffff; 198 else if (mode < XFER_UDMA_0) 199 mask = 0x31c001ff; 200 else 201 mask = 0x303c0000; 202 203 timing = hpt3x2n_find_mode(ap, mode); 204 205 pci_read_config_dword(pdev, addr1, ®); 206 reg = (reg & ~mask) | (timing & mask); 207 pci_write_config_dword(pdev, addr1, reg); 208 } 209 210 /** 211 * hpt3x2n_set_piomode - PIO setup 212 * @ap: ATA interface 213 * @adev: device on the interface 214 * 215 * Perform PIO mode setup. 216 */ 217 218 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) 219 { 220 hpt3x2n_set_mode(ap, adev, adev->pio_mode); 221 } 222 223 /** 224 * hpt3x2n_set_dmamode - DMA timing setup 225 * @ap: ATA interface 226 * @adev: Device being configured 227 * 228 * Set up the channel for MWDMA or UDMA modes. 229 */ 230 231 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) 232 { 233 hpt3x2n_set_mode(ap, adev, adev->dma_mode); 234 } 235 236 /** 237 * hpt3x2n_bmdma_stop - DMA engine stop 238 * @qc: ATA command 239 * 240 * Clean up after the HPT3x2n and later DMA engine 241 */ 242 243 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) 244 { 245 struct ata_port *ap = qc->ap; 246 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 247 int mscreg = 0x50 + 2 * ap->port_no; 248 u8 bwsr_stat, msc_stat; 249 250 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 251 pci_read_config_byte(pdev, mscreg, &msc_stat); 252 if (bwsr_stat & (1 << ap->port_no)) 253 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 254 ata_bmdma_stop(qc); 255 } 256 257 /** 258 * hpt3x2n_set_clock - clock control 259 * @ap: ATA port 260 * @source: 0x21 or 0x23 for PLL or PCI sourced clock 261 * 262 * Switch the ATA bus clock between the PLL and PCI clock sources 263 * while correctly isolating the bus and resetting internal logic 264 * 265 * We must use the DPLL for 266 * - writing 267 * - second channel UDMA7 (SATA ports) or higher 268 * - 66MHz PCI 269 * 270 * or we will underclock the device and get reduced performance. 271 */ 272 273 static void hpt3x2n_set_clock(struct ata_port *ap, int source) 274 { 275 void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; 276 277 /* Tristate the bus */ 278 iowrite8(0x80, bmdma+0x73); 279 iowrite8(0x80, bmdma+0x77); 280 281 /* Switch clock and reset channels */ 282 iowrite8(source, bmdma+0x7B); 283 iowrite8(0xC0, bmdma+0x79); 284 285 /* Reset state machines, avoid enabling the disabled channels */ 286 iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); 287 iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); 288 289 /* Complete reset */ 290 iowrite8(0x00, bmdma+0x79); 291 292 /* Reconnect channels to bus */ 293 iowrite8(0x00, bmdma+0x73); 294 iowrite8(0x00, bmdma+0x77); 295 } 296 297 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) 298 { 299 long flags = (long)ap->host->private_data; 300 301 /* See if we should use the DPLL */ 302 if (writing) 303 return USE_DPLL; /* Needed for write */ 304 if (flags & PCI66) 305 return USE_DPLL; /* Needed at 66Mhz */ 306 return 0; 307 } 308 309 static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) 310 { 311 struct ata_port *ap = qc->ap; 312 struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; 313 int rc, flags = (long)ap->host->private_data; 314 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); 315 316 /* First apply the usual rules */ 317 rc = ata_std_qc_defer(qc); 318 if (rc != 0) 319 return rc; 320 321 if ((flags & USE_DPLL) != dpll && alt->qc_active) 322 return ATA_DEFER_PORT; 323 return 0; 324 } 325 326 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) 327 { 328 struct ata_port *ap = qc->ap; 329 int flags = (long)ap->host->private_data; 330 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); 331 332 if ((flags & USE_DPLL) != dpll) { 333 flags &= ~USE_DPLL; 334 flags |= dpll; 335 ap->host->private_data = (void *)(long)flags; 336 337 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); 338 } 339 return ata_bmdma_qc_issue(qc); 340 } 341 342 static struct scsi_host_template hpt3x2n_sht = { 343 ATA_BMDMA_SHT(DRV_NAME), 344 }; 345 346 /* 347 * Configuration for HPT302N/371N. 348 */ 349 350 static struct ata_port_operations hpt3xxn_port_ops = { 351 .inherits = &ata_bmdma_port_ops, 352 353 .bmdma_stop = hpt3x2n_bmdma_stop, 354 355 .qc_defer = hpt3x2n_qc_defer, 356 .qc_issue = hpt3x2n_qc_issue, 357 358 .cable_detect = hpt3x2n_cable_detect, 359 .set_piomode = hpt3x2n_set_piomode, 360 .set_dmamode = hpt3x2n_set_dmamode, 361 .prereset = hpt3x2n_pre_reset, 362 }; 363 364 /* 365 * Configuration for HPT372N. Same as 302N/371N but we have a mode filter. 366 */ 367 368 static struct ata_port_operations hpt372n_port_ops = { 369 .inherits = &hpt3xxn_port_ops, 370 .mode_filter = &hpt372n_filter, 371 }; 372 373 /** 374 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop 375 * @dev: PCI device 376 * 377 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this 378 * succeeds 379 */ 380 381 static int hpt3xn_calibrate_dpll(struct pci_dev *dev) 382 { 383 u8 reg5b; 384 u32 reg5c; 385 int tries; 386 387 for (tries = 0; tries < 0x5000; tries++) { 388 udelay(50); 389 pci_read_config_byte(dev, 0x5b, ®5b); 390 if (reg5b & 0x80) { 391 /* See if it stays set */ 392 for (tries = 0; tries < 0x1000; tries++) { 393 pci_read_config_byte(dev, 0x5b, ®5b); 394 /* Failed ? */ 395 if ((reg5b & 0x80) == 0) 396 return 0; 397 } 398 /* Turn off tuning, we have the DPLL set */ 399 pci_read_config_dword(dev, 0x5c, ®5c); 400 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); 401 return 1; 402 } 403 } 404 /* Never went stable */ 405 return 0; 406 } 407 408 static int hpt3x2n_pci_clock(struct pci_dev *pdev) 409 { 410 unsigned long freq; 411 u32 fcnt; 412 unsigned long iobase = pci_resource_start(pdev, 4); 413 414 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ 415 if ((fcnt >> 12) != 0xABCDE) { 416 int i; 417 u16 sr; 418 u32 total = 0; 419 420 dev_warn(&pdev->dev, "BIOS clock data not set\n"); 421 422 /* This is the process the HPT371 BIOS is reported to use */ 423 for (i = 0; i < 128; i++) { 424 pci_read_config_word(pdev, 0x78, &sr); 425 total += sr & 0x1FF; 426 udelay(15); 427 } 428 fcnt = total / 128; 429 } 430 fcnt &= 0x1FF; 431 432 freq = (fcnt * 77) / 192; 433 434 /* Clamp to bands */ 435 if (freq < 40) 436 return 33; 437 if (freq < 45) 438 return 40; 439 if (freq < 55) 440 return 50; 441 return 66; 442 } 443 444 /** 445 * hpt3x2n_init_one - Initialise an HPT37X/302 446 * @dev: PCI device 447 * @id: Entry in match table 448 * 449 * Initialise an HPT3x2n device. There are some interesting complications 450 * here. Firstly the chip may report 366 and be one of several variants. 451 * Secondly all the timings depend on the clock for the chip which we must 452 * detect and look up 453 * 454 * This is the known chip mappings. It may be missing a couple of later 455 * releases. 456 * 457 * Chip version PCI Rev Notes 458 * HPT372 4 (HPT366) 5 Other driver 459 * HPT372N 4 (HPT366) 6 UDMA133 460 * HPT372 5 (HPT372) 1 Other driver 461 * HPT372N 5 (HPT372) 2 UDMA133 462 * HPT302 6 (HPT302) * Other driver 463 * HPT302N 6 (HPT302) > 1 UDMA133 464 * HPT371 7 (HPT371) * Other driver 465 * HPT371N 7 (HPT371) > 1 UDMA133 466 * HPT374 8 (HPT374) * Other driver 467 * HPT372N 9 (HPT372N) * UDMA133 468 * 469 * (1) UDMA133 support depends on the bus clock 470 */ 471 472 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) 473 { 474 /* HPT372N - UDMA133 */ 475 static const struct ata_port_info info_hpt372n = { 476 .flags = ATA_FLAG_SLAVE_POSS, 477 .pio_mask = ATA_PIO4, 478 .mwdma_mask = ATA_MWDMA2, 479 .udma_mask = ATA_UDMA6, 480 .port_ops = &hpt372n_port_ops 481 }; 482 /* HPT302N and HPT371N - UDMA133 */ 483 static const struct ata_port_info info_hpt3xxn = { 484 .flags = ATA_FLAG_SLAVE_POSS, 485 .pio_mask = ATA_PIO4, 486 .mwdma_mask = ATA_MWDMA2, 487 .udma_mask = ATA_UDMA6, 488 .port_ops = &hpt3xxn_port_ops 489 }; 490 const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL }; 491 u8 rev = dev->revision; 492 u8 irqmask; 493 unsigned int pci_mhz; 494 unsigned int f_low, f_high; 495 int adjust; 496 unsigned long iobase = pci_resource_start(dev, 4); 497 void *hpriv = (void *)USE_DPLL; 498 int rc; 499 500 rc = pcim_enable_device(dev); 501 if (rc) 502 return rc; 503 504 switch (dev->device) { 505 case PCI_DEVICE_ID_TTI_HPT366: 506 /* 372N if rev >= 6 */ 507 if (rev < 6) 508 return -ENODEV; 509 goto hpt372n; 510 case PCI_DEVICE_ID_TTI_HPT371: 511 /* 371N if rev >= 2 */ 512 if (rev < 2) 513 return -ENODEV; 514 break; 515 case PCI_DEVICE_ID_TTI_HPT372: 516 /* 372N if rev >= 2 */ 517 if (rev < 2) 518 return -ENODEV; 519 goto hpt372n; 520 case PCI_DEVICE_ID_TTI_HPT302: 521 /* 302N if rev >= 2 */ 522 if (rev < 2) 523 return -ENODEV; 524 break; 525 case PCI_DEVICE_ID_TTI_HPT372N: 526 hpt372n: 527 ppi[0] = &info_hpt372n; 528 break; 529 default: 530 dev_err(&dev->dev,"PCI table is bogus, please report (%d)\n", 531 dev->device); 532 return -ENODEV; 533 } 534 535 /* Ok so this is a chip we support */ 536 537 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 538 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 539 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 540 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 541 542 pci_read_config_byte(dev, 0x5A, &irqmask); 543 irqmask &= ~0x10; 544 pci_write_config_byte(dev, 0x5a, irqmask); 545 546 /* 547 * HPT371 chips physically have only one channel, the secondary one, 548 * but the primary channel registers do exist! Go figure... 549 * So, we manually disable the non-existing channel here 550 * (if the BIOS hasn't done this already). 551 */ 552 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { 553 u8 mcr1; 554 pci_read_config_byte(dev, 0x50, &mcr1); 555 mcr1 &= ~0x04; 556 pci_write_config_byte(dev, 0x50, mcr1); 557 } 558 559 /* 560 * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or 561 * 50 for UDMA100. Right now we always use 66 562 */ 563 564 pci_mhz = hpt3x2n_pci_clock(dev); 565 566 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ 567 f_high = f_low + 2; /* Tolerance */ 568 569 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); 570 /* PLL clock */ 571 pci_write_config_byte(dev, 0x5B, 0x21); 572 573 /* Unlike the 37x we don't try jiggling the frequency */ 574 for (adjust = 0; adjust < 8; adjust++) { 575 if (hpt3xn_calibrate_dpll(dev)) 576 break; 577 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); 578 } 579 if (adjust == 8) { 580 dev_err(&dev->dev, "DPLL did not stabilize!\n"); 581 return -ENODEV; 582 } 583 584 dev_info(&dev->dev, "bus clock %dMHz, using 66MHz DPLL\n", pci_mhz); 585 586 /* 587 * Set our private data up. We only need a few flags 588 * so we use it directly. 589 */ 590 if (pci_mhz > 60) 591 hpriv = (void *)(PCI66 | USE_DPLL); 592 593 /* 594 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 595 * the MISC. register to stretch the UltraDMA Tss timing. 596 * NOTE: This register is only writeable via I/O space. 597 */ 598 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) 599 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); 600 601 /* Now kick off ATA set up */ 602 return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0); 603 } 604 605 static const struct pci_device_id hpt3x2n[] = { 606 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 607 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 608 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 610 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, 611 612 { }, 613 }; 614 615 static struct pci_driver hpt3x2n_pci_driver = { 616 .name = DRV_NAME, 617 .id_table = hpt3x2n, 618 .probe = hpt3x2n_init_one, 619 .remove = ata_pci_remove_one 620 }; 621 622 module_pci_driver(hpt3x2n_pci_driver); 623 624 MODULE_AUTHOR("Alan Cox"); 625 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN"); 626 MODULE_LICENSE("GPL"); 627 MODULE_DEVICE_TABLE(pci, hpt3x2n); 628 MODULE_VERSION(DRV_VERSION); 629