1 /* 2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. 3 * 4 * This driver is heavily based upon: 5 * 6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 7 * 8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 10 * Portions Copyright (C) 2003 Red Hat Inc 11 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc. 12 * 13 * TODO 14 * PLL mode 15 * Look into engine reset on timeout errors. Should not be 16 * required. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/init.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <scsi/scsi_host.h> 26 #include <linux/libata.h> 27 28 #define DRV_NAME "pata_hpt37x" 29 #define DRV_VERSION "0.6.6" 30 31 struct hpt_clock { 32 u8 xfer_speed; 33 u32 timing; 34 }; 35 36 struct hpt_chip { 37 const char *name; 38 unsigned int base; 39 struct hpt_clock const *clocks[4]; 40 }; 41 42 /* key for bus clock timings 43 * bit 44 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW 45 * DMA. cycles = value + 1 46 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW 47 * DMA. cycles = value + 1 48 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file 49 * register access. 50 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file 51 * register access. 52 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. 53 * during task file register access. 54 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA 55 * xfer. 56 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task 57 * register access. 58 * 28 UDMA enable 59 * 29 DMA enable 60 * 30 PIO_MST enable. if set, the chip is in bus master mode during 61 * PIO. 62 * 31 FIFO enable. 63 */ 64 65 static struct hpt_clock hpt37x_timings_33[] = { 66 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ 67 { XFER_UDMA_5, 0x12446231 }, 68 { XFER_UDMA_4, 0x12446231 }, 69 { XFER_UDMA_3, 0x126c6231 }, 70 { XFER_UDMA_2, 0x12486231 }, 71 { XFER_UDMA_1, 0x124c6233 }, 72 { XFER_UDMA_0, 0x12506297 }, 73 74 { XFER_MW_DMA_2, 0x22406c31 }, 75 { XFER_MW_DMA_1, 0x22406c33 }, 76 { XFER_MW_DMA_0, 0x22406c97 }, 77 78 { XFER_PIO_4, 0x06414e31 }, 79 { XFER_PIO_3, 0x06414e42 }, 80 { XFER_PIO_2, 0x06414e53 }, 81 { XFER_PIO_1, 0x06814e93 }, 82 { XFER_PIO_0, 0x06814ea7 } 83 }; 84 85 static struct hpt_clock hpt37x_timings_50[] = { 86 { XFER_UDMA_6, 0x12848242 }, 87 { XFER_UDMA_5, 0x12848242 }, 88 { XFER_UDMA_4, 0x12ac8242 }, 89 { XFER_UDMA_3, 0x128c8242 }, 90 { XFER_UDMA_2, 0x120c8242 }, 91 { XFER_UDMA_1, 0x12148254 }, 92 { XFER_UDMA_0, 0x121882ea }, 93 94 { XFER_MW_DMA_2, 0x22808242 }, 95 { XFER_MW_DMA_1, 0x22808254 }, 96 { XFER_MW_DMA_0, 0x228082ea }, 97 98 { XFER_PIO_4, 0x0a81f442 }, 99 { XFER_PIO_3, 0x0a81f443 }, 100 { XFER_PIO_2, 0x0a81f454 }, 101 { XFER_PIO_1, 0x0ac1f465 }, 102 { XFER_PIO_0, 0x0ac1f48a } 103 }; 104 105 static struct hpt_clock hpt37x_timings_66[] = { 106 { XFER_UDMA_6, 0x1c869c62 }, 107 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ 108 { XFER_UDMA_4, 0x1c8a9c62 }, 109 { XFER_UDMA_3, 0x1c8e9c62 }, 110 { XFER_UDMA_2, 0x1c929c62 }, 111 { XFER_UDMA_1, 0x1c9a9c62 }, 112 { XFER_UDMA_0, 0x1c829c62 }, 113 114 { XFER_MW_DMA_2, 0x2c829c62 }, 115 { XFER_MW_DMA_1, 0x2c829c66 }, 116 { XFER_MW_DMA_0, 0x2c829d2e }, 117 118 { XFER_PIO_4, 0x0c829c62 }, 119 { XFER_PIO_3, 0x0c829c84 }, 120 { XFER_PIO_2, 0x0c829ca6 }, 121 { XFER_PIO_1, 0x0d029d26 }, 122 { XFER_PIO_0, 0x0d029d5e } 123 }; 124 125 126 static const struct hpt_chip hpt370 = { 127 "HPT370", 128 48, 129 { 130 hpt37x_timings_33, 131 NULL, 132 NULL, 133 NULL 134 } 135 }; 136 137 static const struct hpt_chip hpt370a = { 138 "HPT370A", 139 48, 140 { 141 hpt37x_timings_33, 142 NULL, 143 hpt37x_timings_50, 144 NULL 145 } 146 }; 147 148 static const struct hpt_chip hpt372 = { 149 "HPT372", 150 55, 151 { 152 hpt37x_timings_33, 153 NULL, 154 hpt37x_timings_50, 155 hpt37x_timings_66 156 } 157 }; 158 159 static const struct hpt_chip hpt302 = { 160 "HPT302", 161 66, 162 { 163 hpt37x_timings_33, 164 NULL, 165 hpt37x_timings_50, 166 hpt37x_timings_66 167 } 168 }; 169 170 static const struct hpt_chip hpt371 = { 171 "HPT371", 172 66, 173 { 174 hpt37x_timings_33, 175 NULL, 176 hpt37x_timings_50, 177 hpt37x_timings_66 178 } 179 }; 180 181 static const struct hpt_chip hpt372a = { 182 "HPT372A", 183 66, 184 { 185 hpt37x_timings_33, 186 NULL, 187 hpt37x_timings_50, 188 hpt37x_timings_66 189 } 190 }; 191 192 static const struct hpt_chip hpt374 = { 193 "HPT374", 194 48, 195 { 196 hpt37x_timings_33, 197 NULL, 198 NULL, 199 NULL 200 } 201 }; 202 203 /** 204 * hpt37x_find_mode - reset the hpt37x bus 205 * @ap: ATA port 206 * @speed: transfer mode 207 * 208 * Return the 32bit register programming information for this channel 209 * that matches the speed provided. 210 */ 211 212 static u32 hpt37x_find_mode(struct ata_port *ap, int speed) 213 { 214 struct hpt_clock *clocks = ap->host->private_data; 215 216 while(clocks->xfer_speed) { 217 if (clocks->xfer_speed == speed) 218 return clocks->timing; 219 clocks++; 220 } 221 BUG(); 222 return 0xffffffffU; /* silence compiler warning */ 223 } 224 225 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[]) 226 { 227 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 228 int i = 0; 229 230 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 231 232 while (list[i] != NULL) { 233 if (!strcmp(list[i], model_num)) { 234 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n", 235 modestr, list[i]); 236 return 1; 237 } 238 i++; 239 } 240 return 0; 241 } 242 243 static const char *bad_ata33[] = { 244 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 245 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 246 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 247 "Maxtor 90510D4", 248 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 249 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 250 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 251 NULL 252 }; 253 254 static const char *bad_ata100_5[] = { 255 "IBM-DTLA-307075", 256 "IBM-DTLA-307060", 257 "IBM-DTLA-307045", 258 "IBM-DTLA-307030", 259 "IBM-DTLA-307020", 260 "IBM-DTLA-307015", 261 "IBM-DTLA-305040", 262 "IBM-DTLA-305030", 263 "IBM-DTLA-305020", 264 "IC35L010AVER07-0", 265 "IC35L020AVER07-0", 266 "IC35L030AVER07-0", 267 "IC35L040AVER07-0", 268 "IC35L060AVER07-0", 269 "WDC AC310200R", 270 NULL 271 }; 272 273 /** 274 * hpt370_filter - mode selection filter 275 * @adev: ATA device 276 * 277 * Block UDMA on devices that cause trouble with this controller. 278 */ 279 280 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) 281 { 282 if (adev->class == ATA_DEV_ATA) { 283 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) 284 mask &= ~ATA_MASK_UDMA; 285 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) 286 mask &= ~(0x1F << ATA_SHIFT_UDMA); 287 } 288 return ata_pci_default_filter(adev, mask); 289 } 290 291 /** 292 * hpt370a_filter - mode selection filter 293 * @adev: ATA device 294 * 295 * Block UDMA on devices that cause trouble with this controller. 296 */ 297 298 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) 299 { 300 if (adev->class != ATA_DEV_ATA) { 301 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) 302 mask &= ~ (0x1F << ATA_SHIFT_UDMA); 303 } 304 return ata_pci_default_filter(adev, mask); 305 } 306 307 /** 308 * hpt37x_pre_reset - reset the hpt37x bus 309 * @ap: ATA port to reset 310 * @deadline: deadline jiffies for the operation 311 * 312 * Perform the initial reset handling for the 370/372 and 374 func 0 313 */ 314 315 static int hpt37x_pre_reset(struct ata_port *ap, unsigned long deadline) 316 { 317 u8 scr2, ata66; 318 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 319 static const struct pci_bits hpt37x_enable_bits[] = { 320 { 0x50, 1, 0x04, 0x04 }, 321 { 0x54, 1, 0x04, 0x04 } 322 }; 323 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) 324 return -ENOENT; 325 326 pci_read_config_byte(pdev, 0x5B, &scr2); 327 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 328 /* Cable register now active */ 329 pci_read_config_byte(pdev, 0x5A, &ata66); 330 /* Restore state */ 331 pci_write_config_byte(pdev, 0x5B, scr2); 332 333 if (ata66 & (1 << ap->port_no)) 334 ap->cbl = ATA_CBL_PATA40; 335 else 336 ap->cbl = ATA_CBL_PATA80; 337 338 /* Reset the state machine */ 339 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 340 udelay(100); 341 342 return ata_std_prereset(ap, deadline); 343 } 344 345 /** 346 * hpt37x_error_handler - reset the hpt374 347 * @ap: ATA port to reset 348 * 349 * Perform probe for HPT37x, except for HPT374 channel 2 350 */ 351 352 static void hpt37x_error_handler(struct ata_port *ap) 353 { 354 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 355 } 356 357 static int hpt374_pre_reset(struct ata_port *ap, unsigned long deadline) 358 { 359 static const struct pci_bits hpt37x_enable_bits[] = { 360 { 0x50, 1, 0x04, 0x04 }, 361 { 0x54, 1, 0x04, 0x04 } 362 }; 363 u16 mcr3, mcr6; 364 u8 ata66; 365 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 366 367 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) 368 return -ENOENT; 369 370 /* Do the extra channel work */ 371 pci_read_config_word(pdev, 0x52, &mcr3); 372 pci_read_config_word(pdev, 0x56, &mcr6); 373 /* Set bit 15 of 0x52 to enable TCBLID as input 374 Set bit 15 of 0x56 to enable FCBLID as input 375 */ 376 pci_write_config_word(pdev, 0x52, mcr3 | 0x8000); 377 pci_write_config_word(pdev, 0x56, mcr6 | 0x8000); 378 pci_read_config_byte(pdev, 0x5A, &ata66); 379 /* Reset TCBLID/FCBLID to output */ 380 pci_write_config_word(pdev, 0x52, mcr3); 381 pci_write_config_word(pdev, 0x56, mcr6); 382 383 if (ata66 & (1 << ap->port_no)) 384 ap->cbl = ATA_CBL_PATA40; 385 else 386 ap->cbl = ATA_CBL_PATA80; 387 388 /* Reset the state machine */ 389 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 390 udelay(100); 391 392 return ata_std_prereset(ap, deadline); 393 } 394 395 /** 396 * hpt374_error_handler - reset the hpt374 397 * @classes: 398 * 399 * The 374 cable detect is a little different due to the extra 400 * channels. The function 0 channels work like usual but function 1 401 * is special 402 */ 403 404 static void hpt374_error_handler(struct ata_port *ap) 405 { 406 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 407 408 if (!(PCI_FUNC(pdev->devfn) & 1)) 409 hpt37x_error_handler(ap); 410 else 411 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 412 } 413 414 /** 415 * hpt370_set_piomode - PIO setup 416 * @ap: ATA interface 417 * @adev: device on the interface 418 * 419 * Perform PIO mode setup. 420 */ 421 422 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) 423 { 424 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 425 u32 addr1, addr2; 426 u32 reg; 427 u32 mode; 428 u8 fast; 429 430 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 431 addr2 = 0x51 + 4 * ap->port_no; 432 433 /* Fast interrupt prediction disable, hold off interrupt disable */ 434 pci_read_config_byte(pdev, addr2, &fast); 435 fast &= ~0x02; 436 fast |= 0x01; 437 pci_write_config_byte(pdev, addr2, fast); 438 439 pci_read_config_dword(pdev, addr1, ®); 440 mode = hpt37x_find_mode(ap, adev->pio_mode); 441 mode &= ~0x8000000; /* No FIFO in PIO */ 442 mode &= ~0x30070000; /* Leave config bits alone */ 443 reg &= 0x30070000; /* Strip timing bits */ 444 pci_write_config_dword(pdev, addr1, reg | mode); 445 } 446 447 /** 448 * hpt370_set_dmamode - DMA timing setup 449 * @ap: ATA interface 450 * @adev: Device being configured 451 * 452 * Set up the channel for MWDMA or UDMA modes. Much the same as with 453 * PIO, load the mode number and then set MWDMA or UDMA flag. 454 */ 455 456 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) 457 { 458 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 459 u32 addr1, addr2; 460 u32 reg; 461 u32 mode; 462 u8 fast; 463 464 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 465 addr2 = 0x51 + 4 * ap->port_no; 466 467 /* Fast interrupt prediction disable, hold off interrupt disable */ 468 pci_read_config_byte(pdev, addr2, &fast); 469 fast &= ~0x02; 470 fast |= 0x01; 471 pci_write_config_byte(pdev, addr2, fast); 472 473 pci_read_config_dword(pdev, addr1, ®); 474 mode = hpt37x_find_mode(ap, adev->dma_mode); 475 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */ 476 mode &= ~0xC0000000; /* Leave config bits alone */ 477 reg &= 0xC0000000; /* Strip timing bits */ 478 pci_write_config_dword(pdev, addr1, reg | mode); 479 } 480 481 /** 482 * hpt370_bmdma_start - DMA engine begin 483 * @qc: ATA command 484 * 485 * The 370 and 370A want us to reset the DMA engine each time we 486 * use it. The 372 and later are fine. 487 */ 488 489 static void hpt370_bmdma_start(struct ata_queued_cmd *qc) 490 { 491 struct ata_port *ap = qc->ap; 492 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 493 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 494 udelay(10); 495 ata_bmdma_start(qc); 496 } 497 498 /** 499 * hpt370_bmdma_end - DMA engine stop 500 * @qc: ATA command 501 * 502 * Work around the HPT370 DMA engine. 503 */ 504 505 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) 506 { 507 struct ata_port *ap = qc->ap; 508 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 509 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2); 510 u8 dma_cmd; 511 void __iomem *bmdma = ap->ioaddr.bmdma_addr; 512 513 if (dma_stat & 0x01) { 514 udelay(20); 515 dma_stat = ioread8(bmdma + 2); 516 } 517 if (dma_stat & 0x01) { 518 /* Clear the engine */ 519 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 520 udelay(10); 521 /* Stop DMA */ 522 dma_cmd = ioread8(bmdma ); 523 iowrite8(dma_cmd & 0xFE, bmdma); 524 /* Clear Error */ 525 dma_stat = ioread8(bmdma + 2); 526 iowrite8(dma_stat | 0x06 , bmdma + 2); 527 /* Clear the engine */ 528 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 529 udelay(10); 530 } 531 ata_bmdma_stop(qc); 532 } 533 534 /** 535 * hpt372_set_piomode - PIO setup 536 * @ap: ATA interface 537 * @adev: device on the interface 538 * 539 * Perform PIO mode setup. 540 */ 541 542 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) 543 { 544 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 545 u32 addr1, addr2; 546 u32 reg; 547 u32 mode; 548 u8 fast; 549 550 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 551 addr2 = 0x51 + 4 * ap->port_no; 552 553 /* Fast interrupt prediction disable, hold off interrupt disable */ 554 pci_read_config_byte(pdev, addr2, &fast); 555 fast &= ~0x07; 556 pci_write_config_byte(pdev, addr2, fast); 557 558 pci_read_config_dword(pdev, addr1, ®); 559 mode = hpt37x_find_mode(ap, adev->pio_mode); 560 561 printk("Find mode for %d reports %X\n", adev->pio_mode, mode); 562 mode &= ~0x80000000; /* No FIFO in PIO */ 563 mode &= ~0x30070000; /* Leave config bits alone */ 564 reg &= 0x30070000; /* Strip timing bits */ 565 pci_write_config_dword(pdev, addr1, reg | mode); 566 } 567 568 /** 569 * hpt372_set_dmamode - DMA timing setup 570 * @ap: ATA interface 571 * @adev: Device being configured 572 * 573 * Set up the channel for MWDMA or UDMA modes. Much the same as with 574 * PIO, load the mode number and then set MWDMA or UDMA flag. 575 */ 576 577 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) 578 { 579 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 580 u32 addr1, addr2; 581 u32 reg; 582 u32 mode; 583 u8 fast; 584 585 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 586 addr2 = 0x51 + 4 * ap->port_no; 587 588 /* Fast interrupt prediction disable, hold off interrupt disable */ 589 pci_read_config_byte(pdev, addr2, &fast); 590 fast &= ~0x07; 591 pci_write_config_byte(pdev, addr2, fast); 592 593 pci_read_config_dword(pdev, addr1, ®); 594 mode = hpt37x_find_mode(ap, adev->dma_mode); 595 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode); 596 mode &= ~0xC0000000; /* Leave config bits alone */ 597 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */ 598 reg &= 0xC0000000; /* Strip timing bits */ 599 pci_write_config_dword(pdev, addr1, reg | mode); 600 } 601 602 /** 603 * hpt37x_bmdma_end - DMA engine stop 604 * @qc: ATA command 605 * 606 * Clean up after the HPT372 and later DMA engine 607 */ 608 609 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) 610 { 611 struct ata_port *ap = qc->ap; 612 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 613 int mscreg = 0x50 + 4 * ap->port_no; 614 u8 bwsr_stat, msc_stat; 615 616 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 617 pci_read_config_byte(pdev, mscreg, &msc_stat); 618 if (bwsr_stat & (1 << ap->port_no)) 619 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 620 ata_bmdma_stop(qc); 621 } 622 623 624 static struct scsi_host_template hpt37x_sht = { 625 .module = THIS_MODULE, 626 .name = DRV_NAME, 627 .ioctl = ata_scsi_ioctl, 628 .queuecommand = ata_scsi_queuecmd, 629 .can_queue = ATA_DEF_QUEUE, 630 .this_id = ATA_SHT_THIS_ID, 631 .sg_tablesize = LIBATA_MAX_PRD, 632 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 633 .emulated = ATA_SHT_EMULATED, 634 .use_clustering = ATA_SHT_USE_CLUSTERING, 635 .proc_name = DRV_NAME, 636 .dma_boundary = ATA_DMA_BOUNDARY, 637 .slave_configure = ata_scsi_slave_config, 638 .slave_destroy = ata_scsi_slave_destroy, 639 .bios_param = ata_std_bios_param, 640 }; 641 642 /* 643 * Configuration for HPT370 644 */ 645 646 static struct ata_port_operations hpt370_port_ops = { 647 .port_disable = ata_port_disable, 648 .set_piomode = hpt370_set_piomode, 649 .set_dmamode = hpt370_set_dmamode, 650 .mode_filter = hpt370_filter, 651 652 .tf_load = ata_tf_load, 653 .tf_read = ata_tf_read, 654 .check_status = ata_check_status, 655 .exec_command = ata_exec_command, 656 .dev_select = ata_std_dev_select, 657 658 .freeze = ata_bmdma_freeze, 659 .thaw = ata_bmdma_thaw, 660 .error_handler = hpt37x_error_handler, 661 .post_internal_cmd = ata_bmdma_post_internal_cmd, 662 663 .bmdma_setup = ata_bmdma_setup, 664 .bmdma_start = hpt370_bmdma_start, 665 .bmdma_stop = hpt370_bmdma_stop, 666 .bmdma_status = ata_bmdma_status, 667 668 .qc_prep = ata_qc_prep, 669 .qc_issue = ata_qc_issue_prot, 670 671 .data_xfer = ata_data_xfer, 672 673 .irq_handler = ata_interrupt, 674 .irq_clear = ata_bmdma_irq_clear, 675 .irq_on = ata_irq_on, 676 .irq_ack = ata_irq_ack, 677 678 .port_start = ata_port_start, 679 }; 680 681 /* 682 * Configuration for HPT370A. Close to 370 but less filters 683 */ 684 685 static struct ata_port_operations hpt370a_port_ops = { 686 .port_disable = ata_port_disable, 687 .set_piomode = hpt370_set_piomode, 688 .set_dmamode = hpt370_set_dmamode, 689 .mode_filter = hpt370a_filter, 690 691 .tf_load = ata_tf_load, 692 .tf_read = ata_tf_read, 693 .check_status = ata_check_status, 694 .exec_command = ata_exec_command, 695 .dev_select = ata_std_dev_select, 696 697 .freeze = ata_bmdma_freeze, 698 .thaw = ata_bmdma_thaw, 699 .error_handler = hpt37x_error_handler, 700 .post_internal_cmd = ata_bmdma_post_internal_cmd, 701 702 .bmdma_setup = ata_bmdma_setup, 703 .bmdma_start = hpt370_bmdma_start, 704 .bmdma_stop = hpt370_bmdma_stop, 705 .bmdma_status = ata_bmdma_status, 706 707 .qc_prep = ata_qc_prep, 708 .qc_issue = ata_qc_issue_prot, 709 710 .data_xfer = ata_data_xfer, 711 712 .irq_handler = ata_interrupt, 713 .irq_clear = ata_bmdma_irq_clear, 714 .irq_on = ata_irq_on, 715 .irq_ack = ata_irq_ack, 716 717 .port_start = ata_port_start, 718 }; 719 720 /* 721 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO 722 * and DMA mode setting functionality. 723 */ 724 725 static struct ata_port_operations hpt372_port_ops = { 726 .port_disable = ata_port_disable, 727 .set_piomode = hpt372_set_piomode, 728 .set_dmamode = hpt372_set_dmamode, 729 .mode_filter = ata_pci_default_filter, 730 731 .tf_load = ata_tf_load, 732 .tf_read = ata_tf_read, 733 .check_status = ata_check_status, 734 .exec_command = ata_exec_command, 735 .dev_select = ata_std_dev_select, 736 737 .freeze = ata_bmdma_freeze, 738 .thaw = ata_bmdma_thaw, 739 .error_handler = hpt37x_error_handler, 740 .post_internal_cmd = ata_bmdma_post_internal_cmd, 741 742 .bmdma_setup = ata_bmdma_setup, 743 .bmdma_start = ata_bmdma_start, 744 .bmdma_stop = hpt37x_bmdma_stop, 745 .bmdma_status = ata_bmdma_status, 746 747 .qc_prep = ata_qc_prep, 748 .qc_issue = ata_qc_issue_prot, 749 750 .data_xfer = ata_data_xfer, 751 752 .irq_handler = ata_interrupt, 753 .irq_clear = ata_bmdma_irq_clear, 754 .irq_on = ata_irq_on, 755 .irq_ack = ata_irq_ack, 756 757 .port_start = ata_port_start, 758 }; 759 760 /* 761 * Configuration for HPT374. Mode setting works like 372 and friends 762 * but we have a different cable detection procedure. 763 */ 764 765 static struct ata_port_operations hpt374_port_ops = { 766 .port_disable = ata_port_disable, 767 .set_piomode = hpt372_set_piomode, 768 .set_dmamode = hpt372_set_dmamode, 769 .mode_filter = ata_pci_default_filter, 770 771 .tf_load = ata_tf_load, 772 .tf_read = ata_tf_read, 773 .check_status = ata_check_status, 774 .exec_command = ata_exec_command, 775 .dev_select = ata_std_dev_select, 776 777 .freeze = ata_bmdma_freeze, 778 .thaw = ata_bmdma_thaw, 779 .error_handler = hpt374_error_handler, 780 .post_internal_cmd = ata_bmdma_post_internal_cmd, 781 782 .bmdma_setup = ata_bmdma_setup, 783 .bmdma_start = ata_bmdma_start, 784 .bmdma_stop = hpt37x_bmdma_stop, 785 .bmdma_status = ata_bmdma_status, 786 787 .qc_prep = ata_qc_prep, 788 .qc_issue = ata_qc_issue_prot, 789 790 .data_xfer = ata_data_xfer, 791 792 .irq_handler = ata_interrupt, 793 .irq_clear = ata_bmdma_irq_clear, 794 .irq_on = ata_irq_on, 795 .irq_ack = ata_irq_ack, 796 797 .port_start = ata_port_start, 798 }; 799 800 /** 801 * htp37x_clock_slot - Turn timing to PC clock entry 802 * @freq: Reported frequency timing 803 * @base: Base timing 804 * 805 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 806 * and 3 for 66Mhz) 807 */ 808 809 static int hpt37x_clock_slot(unsigned int freq, unsigned int base) 810 { 811 unsigned int f = (base * freq) / 192; /* Mhz */ 812 if (f < 40) 813 return 0; /* 33Mhz slot */ 814 if (f < 45) 815 return 1; /* 40Mhz slot */ 816 if (f < 55) 817 return 2; /* 50Mhz slot */ 818 return 3; /* 60Mhz slot */ 819 } 820 821 /** 822 * hpt37x_calibrate_dpll - Calibrate the DPLL loop 823 * @dev: PCI device 824 * 825 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this 826 * succeeds 827 */ 828 829 static int hpt37x_calibrate_dpll(struct pci_dev *dev) 830 { 831 u8 reg5b; 832 u32 reg5c; 833 int tries; 834 835 for(tries = 0; tries < 0x5000; tries++) { 836 udelay(50); 837 pci_read_config_byte(dev, 0x5b, ®5b); 838 if (reg5b & 0x80) { 839 /* See if it stays set */ 840 for(tries = 0; tries < 0x1000; tries ++) { 841 pci_read_config_byte(dev, 0x5b, ®5b); 842 /* Failed ? */ 843 if ((reg5b & 0x80) == 0) 844 return 0; 845 } 846 /* Turn off tuning, we have the DPLL set */ 847 pci_read_config_dword(dev, 0x5c, ®5c); 848 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); 849 return 1; 850 } 851 } 852 /* Never went stable */ 853 return 0; 854 } 855 /** 856 * hpt37x_init_one - Initialise an HPT37X/302 857 * @dev: PCI device 858 * @id: Entry in match table 859 * 860 * Initialise an HPT37x device. There are some interesting complications 861 * here. Firstly the chip may report 366 and be one of several variants. 862 * Secondly all the timings depend on the clock for the chip which we must 863 * detect and look up 864 * 865 * This is the known chip mappings. It may be missing a couple of later 866 * releases. 867 * 868 * Chip version PCI Rev Notes 869 * HPT366 4 (HPT366) 0 Other driver 870 * HPT366 4 (HPT366) 1 Other driver 871 * HPT368 4 (HPT366) 2 Other driver 872 * HPT370 4 (HPT366) 3 UDMA100 873 * HPT370A 4 (HPT366) 4 UDMA100 874 * HPT372 4 (HPT366) 5 UDMA133 (1) 875 * HPT372N 4 (HPT366) 6 Other driver 876 * HPT372A 5 (HPT372) 1 UDMA133 (1) 877 * HPT372N 5 (HPT372) 2 Other driver 878 * HPT302 6 (HPT302) 1 UDMA133 879 * HPT302N 6 (HPT302) 2 Other driver 880 * HPT371 7 (HPT371) * UDMA133 881 * HPT374 8 (HPT374) * UDMA133 4 channel 882 * HPT372N 9 (HPT372N) * Other driver 883 * 884 * (1) UDMA133 support depends on the bus clock 885 */ 886 887 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 888 { 889 /* HPT370 - UDMA100 */ 890 static const struct ata_port_info info_hpt370 = { 891 .sht = &hpt37x_sht, 892 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, 893 .pio_mask = 0x1f, 894 .mwdma_mask = 0x07, 895 .udma_mask = 0x3f, 896 .port_ops = &hpt370_port_ops 897 }; 898 /* HPT370A - UDMA100 */ 899 static const struct ata_port_info info_hpt370a = { 900 .sht = &hpt37x_sht, 901 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, 902 .pio_mask = 0x1f, 903 .mwdma_mask = 0x07, 904 .udma_mask = 0x3f, 905 .port_ops = &hpt370a_port_ops 906 }; 907 /* HPT370 - UDMA100 */ 908 static const struct ata_port_info info_hpt370_33 = { 909 .sht = &hpt37x_sht, 910 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, 911 .pio_mask = 0x1f, 912 .mwdma_mask = 0x07, 913 .udma_mask = 0x0f, 914 .port_ops = &hpt370_port_ops 915 }; 916 /* HPT370A - UDMA100 */ 917 static const struct ata_port_info info_hpt370a_33 = { 918 .sht = &hpt37x_sht, 919 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, 920 .pio_mask = 0x1f, 921 .mwdma_mask = 0x07, 922 .udma_mask = 0x0f, 923 .port_ops = &hpt370a_port_ops 924 }; 925 /* HPT371, 372 and friends - UDMA133 */ 926 static const struct ata_port_info info_hpt372 = { 927 .sht = &hpt37x_sht, 928 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, 929 .pio_mask = 0x1f, 930 .mwdma_mask = 0x07, 931 .udma_mask = 0x7f, 932 .port_ops = &hpt372_port_ops 933 }; 934 /* HPT374 - UDMA100 */ 935 static const struct ata_port_info info_hpt374 = { 936 .sht = &hpt37x_sht, 937 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, 938 .pio_mask = 0x1f, 939 .mwdma_mask = 0x07, 940 .udma_mask = 0x3f, 941 .port_ops = &hpt374_port_ops 942 }; 943 944 static const int MHz[4] = { 33, 40, 50, 66 }; 945 const struct ata_port_info *port; 946 void *private_data = NULL; 947 struct ata_port_info port_info; 948 const struct ata_port_info *ppi[] = { &port_info, NULL }; 949 950 u8 irqmask; 951 u32 class_rev; 952 u8 mcr1; 953 u32 freq; 954 int prefer_dpll = 1; 955 956 unsigned long iobase = pci_resource_start(dev, 4); 957 958 const struct hpt_chip *chip_table; 959 int clock_slot; 960 961 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 962 class_rev &= 0xFF; 963 964 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) { 965 /* May be a later chip in disguise. Check */ 966 /* Older chips are in the HPT366 driver. Ignore them */ 967 if (class_rev < 3) 968 return -ENODEV; 969 /* N series chips have their own driver. Ignore */ 970 if (class_rev == 6) 971 return -ENODEV; 972 973 switch(class_rev) { 974 case 3: 975 port = &info_hpt370; 976 chip_table = &hpt370; 977 prefer_dpll = 0; 978 break; 979 case 4: 980 port = &info_hpt370a; 981 chip_table = &hpt370a; 982 prefer_dpll = 0; 983 break; 984 case 5: 985 port = &info_hpt372; 986 chip_table = &hpt372; 987 break; 988 default: 989 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev); 990 return -ENODEV; 991 } 992 } else { 993 switch(dev->device) { 994 case PCI_DEVICE_ID_TTI_HPT372: 995 /* 372N if rev >= 2*/ 996 if (class_rev >= 2) 997 return -ENODEV; 998 port = &info_hpt372; 999 chip_table = &hpt372a; 1000 break; 1001 case PCI_DEVICE_ID_TTI_HPT302: 1002 /* 302N if rev > 1 */ 1003 if (class_rev > 1) 1004 return -ENODEV; 1005 port = &info_hpt372; 1006 /* Check this */ 1007 chip_table = &hpt302; 1008 break; 1009 case PCI_DEVICE_ID_TTI_HPT371: 1010 if (class_rev > 1) 1011 return -ENODEV; 1012 port = &info_hpt372; 1013 chip_table = &hpt371; 1014 /* Single channel device, master is not present 1015 but the BIOS (or us for non x86) must mark it 1016 absent */ 1017 pci_read_config_byte(dev, 0x50, &mcr1); 1018 mcr1 &= ~0x04; 1019 pci_write_config_byte(dev, 0x50, mcr1); 1020 break; 1021 case PCI_DEVICE_ID_TTI_HPT374: 1022 chip_table = &hpt374; 1023 port = &info_hpt374; 1024 break; 1025 default: 1026 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device); 1027 return -ENODEV; 1028 } 1029 } 1030 /* Ok so this is a chip we support */ 1031 1032 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 1033 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 1034 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 1035 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 1036 1037 pci_read_config_byte(dev, 0x5A, &irqmask); 1038 irqmask &= ~0x10; 1039 pci_write_config_byte(dev, 0x5a, irqmask); 1040 1041 /* 1042 * default to pci clock. make sure MA15/16 are set to output 1043 * to prevent drives having problems with 40-pin cables. Needed 1044 * for some drives such as IBM-DTLA which will not enter ready 1045 * state on reset when PDIAG is a input. 1046 */ 1047 1048 pci_write_config_byte(dev, 0x5b, 0x23); 1049 1050 /* 1051 * HighPoint does this for HPT372A. 1052 * NOTE: This register is only writeable via I/O space. 1053 */ 1054 if (chip_table == &hpt372a) 1055 outb(0x0e, iobase + 0x9c); 1056 1057 /* Some devices do not let this value be accessed via PCI space 1058 according to the old driver */ 1059 1060 freq = inl(iobase + 0x90); 1061 if ((freq >> 12) != 0xABCDE) { 1062 int i; 1063 u8 sr; 1064 u32 total = 0; 1065 1066 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n"); 1067 1068 /* This is the process the HPT371 BIOS is reported to use */ 1069 for(i = 0; i < 128; i++) { 1070 pci_read_config_byte(dev, 0x78, &sr); 1071 total += sr & 0x1FF; 1072 udelay(15); 1073 } 1074 freq = total / 128; 1075 } 1076 freq &= 0x1FF; 1077 1078 /* 1079 * Turn the frequency check into a band and then find a timing 1080 * table to match it. 1081 */ 1082 1083 clock_slot = hpt37x_clock_slot(freq, chip_table->base); 1084 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { 1085 /* 1086 * We need to try PLL mode instead 1087 * 1088 * For non UDMA133 capable devices we should 1089 * use a 50MHz DPLL by choice 1090 */ 1091 unsigned int f_low, f_high; 1092 int dpll, adjust; 1093 1094 /* Compute DPLL */ 1095 dpll = 2; 1096 if (port->udma_mask & 0xE0) 1097 dpll = 3; 1098 1099 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; 1100 f_high = f_low + 2; 1101 if (clock_slot > 1) 1102 f_high += 2; 1103 1104 /* Select the DPLL clock. */ 1105 pci_write_config_byte(dev, 0x5b, 0x21); 1106 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); 1107 1108 for(adjust = 0; adjust < 8; adjust++) { 1109 if (hpt37x_calibrate_dpll(dev)) 1110 break; 1111 /* See if it'll settle at a fractionally different clock */ 1112 if ((adjust & 3) == 3) { 1113 f_low --; 1114 f_high ++; 1115 } 1116 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); 1117 } 1118 if (adjust == 8) { 1119 printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n"); 1120 return -ENODEV; 1121 } 1122 if (dpll == 3) 1123 private_data = (void *)hpt37x_timings_66; 1124 else 1125 private_data = (void *)hpt37x_timings_50; 1126 1127 printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[dpll]); 1128 } else { 1129 private_data = (void *)chip_table->clocks[clock_slot]; 1130 /* 1131 * Perform a final fixup. Note that we will have used the 1132 * DPLL on the HPT372 which means we don't have to worry 1133 * about lack of UDMA133 support on lower clocks 1134 */ 1135 1136 if (clock_slot < 2 && port == &info_hpt370) 1137 port = &info_hpt370_33; 1138 if (clock_slot < 2 && port == &info_hpt370a) 1139 port = &info_hpt370a_33; 1140 printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]); 1141 } 1142 1143 /* Now kick off ATA set up */ 1144 port_info = *port; 1145 port_info.private_data = private_data; 1146 1147 return ata_pci_init_one(dev, ppi); 1148 } 1149 1150 static const struct pci_device_id hpt37x[] = { 1151 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 1152 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 1153 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 1154 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, 1155 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 1156 1157 { }, 1158 }; 1159 1160 static struct pci_driver hpt37x_pci_driver = { 1161 .name = DRV_NAME, 1162 .id_table = hpt37x, 1163 .probe = hpt37x_init_one, 1164 .remove = ata_pci_remove_one 1165 }; 1166 1167 static int __init hpt37x_init(void) 1168 { 1169 return pci_register_driver(&hpt37x_pci_driver); 1170 } 1171 1172 static void __exit hpt37x_exit(void) 1173 { 1174 pci_unregister_driver(&hpt37x_pci_driver); 1175 } 1176 1177 MODULE_AUTHOR("Alan Cox"); 1178 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); 1179 MODULE_LICENSE("GPL"); 1180 MODULE_DEVICE_TABLE(pci, hpt37x); 1181 MODULE_VERSION(DRV_VERSION); 1182 1183 module_init(hpt37x_init); 1184 module_exit(hpt37x_exit); 1185