1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. 4 * 5 * This driver is heavily based upon: 6 * 7 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 8 * 9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 10 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 11 * Portions Copyright (C) 2003 Red Hat Inc 12 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. 13 * 14 * TODO 15 * Look into engine reset on timeout errors. Should not be required. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/blkdev.h> 21 #include <linux/delay.h> 22 #include <scsi/scsi_host.h> 23 #include <linux/libata.h> 24 25 #define DRV_NAME "pata_hpt37x" 26 #define DRV_VERSION "0.6.25" 27 28 struct hpt_clock { 29 u8 xfer_speed; 30 u32 timing; 31 }; 32 33 struct hpt_chip { 34 const char *name; 35 unsigned int base; 36 struct hpt_clock const *clocks[4]; 37 }; 38 39 /* key for bus clock timings 40 * bit 41 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 42 * cycles = value + 1 43 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 44 * cycles = value + 1 45 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 46 * register access. 47 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 48 * register access. 49 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 50 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. 51 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. 52 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file 53 * register access. 54 * 28 UDMA enable. 55 * 29 DMA enable. 56 * 30 PIO_MST enable. If set, the chip is in bus master mode during 57 * PIO xfer. 58 * 31 FIFO enable. Only for PIO. 59 */ 60 61 static struct hpt_clock hpt37x_timings_33[] = { 62 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ 63 { XFER_UDMA_5, 0x12446231 }, 64 { XFER_UDMA_4, 0x12446231 }, 65 { XFER_UDMA_3, 0x126c6231 }, 66 { XFER_UDMA_2, 0x12486231 }, 67 { XFER_UDMA_1, 0x124c6233 }, 68 { XFER_UDMA_0, 0x12506297 }, 69 70 { XFER_MW_DMA_2, 0x22406c31 }, 71 { XFER_MW_DMA_1, 0x22406c33 }, 72 { XFER_MW_DMA_0, 0x22406c97 }, 73 74 { XFER_PIO_4, 0x06414e31 }, 75 { XFER_PIO_3, 0x06414e42 }, 76 { XFER_PIO_2, 0x06414e53 }, 77 { XFER_PIO_1, 0x06814e93 }, 78 { XFER_PIO_0, 0x06814ea7 } 79 }; 80 81 static struct hpt_clock hpt37x_timings_50[] = { 82 { XFER_UDMA_6, 0x12848242 }, 83 { XFER_UDMA_5, 0x12848242 }, 84 { XFER_UDMA_4, 0x12ac8242 }, 85 { XFER_UDMA_3, 0x128c8242 }, 86 { XFER_UDMA_2, 0x120c8242 }, 87 { XFER_UDMA_1, 0x12148254 }, 88 { XFER_UDMA_0, 0x121882ea }, 89 90 { XFER_MW_DMA_2, 0x22808242 }, 91 { XFER_MW_DMA_1, 0x22808254 }, 92 { XFER_MW_DMA_0, 0x228082ea }, 93 94 { XFER_PIO_4, 0x0a81f442 }, 95 { XFER_PIO_3, 0x0a81f443 }, 96 { XFER_PIO_2, 0x0a81f454 }, 97 { XFER_PIO_1, 0x0ac1f465 }, 98 { XFER_PIO_0, 0x0ac1f48a } 99 }; 100 101 static struct hpt_clock hpt37x_timings_66[] = { 102 { XFER_UDMA_6, 0x1c869c62 }, 103 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ 104 { XFER_UDMA_4, 0x1c8a9c62 }, 105 { XFER_UDMA_3, 0x1c8e9c62 }, 106 { XFER_UDMA_2, 0x1c929c62 }, 107 { XFER_UDMA_1, 0x1c9a9c62 }, 108 { XFER_UDMA_0, 0x1c829c62 }, 109 110 { XFER_MW_DMA_2, 0x2c829c62 }, 111 { XFER_MW_DMA_1, 0x2c829c66 }, 112 { XFER_MW_DMA_0, 0x2c829d2e }, 113 114 { XFER_PIO_4, 0x0c829c62 }, 115 { XFER_PIO_3, 0x0c829c84 }, 116 { XFER_PIO_2, 0x0c829ca6 }, 117 { XFER_PIO_1, 0x0d029d26 }, 118 { XFER_PIO_0, 0x0d029d5e } 119 }; 120 121 122 static const struct hpt_chip hpt370 = { 123 "HPT370", 124 48, 125 { 126 hpt37x_timings_33, 127 NULL, 128 NULL, 129 NULL 130 } 131 }; 132 133 static const struct hpt_chip hpt370a = { 134 "HPT370A", 135 48, 136 { 137 hpt37x_timings_33, 138 NULL, 139 hpt37x_timings_50, 140 NULL 141 } 142 }; 143 144 static const struct hpt_chip hpt372 = { 145 "HPT372", 146 55, 147 { 148 hpt37x_timings_33, 149 NULL, 150 hpt37x_timings_50, 151 hpt37x_timings_66 152 } 153 }; 154 155 static const struct hpt_chip hpt302 = { 156 "HPT302", 157 66, 158 { 159 hpt37x_timings_33, 160 NULL, 161 hpt37x_timings_50, 162 hpt37x_timings_66 163 } 164 }; 165 166 static const struct hpt_chip hpt371 = { 167 "HPT371", 168 66, 169 { 170 hpt37x_timings_33, 171 NULL, 172 hpt37x_timings_50, 173 hpt37x_timings_66 174 } 175 }; 176 177 static const struct hpt_chip hpt372a = { 178 "HPT372A", 179 66, 180 { 181 hpt37x_timings_33, 182 NULL, 183 hpt37x_timings_50, 184 hpt37x_timings_66 185 } 186 }; 187 188 static const struct hpt_chip hpt374 = { 189 "HPT374", 190 48, 191 { 192 hpt37x_timings_33, 193 NULL, 194 NULL, 195 NULL 196 } 197 }; 198 199 /** 200 * hpt37x_find_mode - reset the hpt37x bus 201 * @ap: ATA port 202 * @speed: transfer mode 203 * 204 * Return the 32bit register programming information for this channel 205 * that matches the speed provided. 206 */ 207 208 static u32 hpt37x_find_mode(struct ata_port *ap, int speed) 209 { 210 struct hpt_clock *clocks = ap->host->private_data; 211 212 while (clocks->xfer_speed) { 213 if (clocks->xfer_speed == speed) 214 return clocks->timing; 215 clocks++; 216 } 217 BUG(); 218 return 0xffffffffU; /* silence compiler warning */ 219 } 220 221 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, 222 const char * const list[]) 223 { 224 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 225 int i; 226 227 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 228 229 i = match_string(list, -1, model_num); 230 if (i >= 0) { 231 ata_dev_warn(dev, "%s is not supported for %s\n", 232 modestr, list[i]); 233 return 1; 234 } 235 return 0; 236 } 237 238 static const char * const bad_ata33[] = { 239 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", 240 "Maxtor 90845U3", "Maxtor 90650U2", 241 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", 242 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 243 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", 244 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 245 "Maxtor 90510D4", 246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", 248 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 249 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", 250 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 251 NULL 252 }; 253 254 static const char * const bad_ata100_5[] = { 255 "IBM-DTLA-307075", 256 "IBM-DTLA-307060", 257 "IBM-DTLA-307045", 258 "IBM-DTLA-307030", 259 "IBM-DTLA-307020", 260 "IBM-DTLA-307015", 261 "IBM-DTLA-305040", 262 "IBM-DTLA-305030", 263 "IBM-DTLA-305020", 264 "IC35L010AVER07-0", 265 "IC35L020AVER07-0", 266 "IC35L030AVER07-0", 267 "IC35L040AVER07-0", 268 "IC35L060AVER07-0", 269 "WDC AC310200R", 270 NULL 271 }; 272 273 /** 274 * hpt370_filter - mode selection filter 275 * @adev: ATA device 276 * @mask: mode mask 277 * 278 * Block UDMA on devices that cause trouble with this controller. 279 */ 280 281 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) 282 { 283 if (adev->class == ATA_DEV_ATA) { 284 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) 285 mask &= ~ATA_MASK_UDMA; 286 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) 287 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 288 } 289 return mask; 290 } 291 292 /** 293 * hpt370a_filter - mode selection filter 294 * @adev: ATA device 295 * @mask: mode mask 296 * 297 * Block UDMA on devices that cause trouble with this controller. 298 */ 299 300 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) 301 { 302 if (adev->class == ATA_DEV_ATA) { 303 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) 304 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 305 } 306 return mask; 307 } 308 309 /** 310 * hpt372_filter - mode selection filter 311 * @adev: ATA device 312 * @mask: mode mask 313 * 314 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 315 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 316 */ 317 static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask) 318 { 319 if (ata_id_is_sata(adev->id)) 320 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); 321 322 return mask; 323 } 324 325 /** 326 * hpt37x_cable_detect - Detect the cable type 327 * @ap: ATA port to detect on 328 * 329 * Return the cable type attached to this port 330 */ 331 332 static int hpt37x_cable_detect(struct ata_port *ap) 333 { 334 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 335 u8 scr2, ata66; 336 337 pci_read_config_byte(pdev, 0x5B, &scr2); 338 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 339 340 udelay(10); /* debounce */ 341 342 /* Cable register now active */ 343 pci_read_config_byte(pdev, 0x5A, &ata66); 344 /* Restore state */ 345 pci_write_config_byte(pdev, 0x5B, scr2); 346 347 if (ata66 & (2 >> ap->port_no)) 348 return ATA_CBL_PATA40; 349 else 350 return ATA_CBL_PATA80; 351 } 352 353 /** 354 * hpt374_fn1_cable_detect - Detect the cable type 355 * @ap: ATA port to detect on 356 * 357 * Return the cable type attached to this port 358 */ 359 360 static int hpt374_fn1_cable_detect(struct ata_port *ap) 361 { 362 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 363 unsigned int mcrbase = 0x50 + 4 * ap->port_no; 364 u16 mcr3; 365 u8 ata66; 366 367 /* Do the extra channel work */ 368 pci_read_config_word(pdev, mcrbase + 2, &mcr3); 369 /* Set bit 15 of 0x52 to enable TCBLID as input */ 370 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); 371 pci_read_config_byte(pdev, 0x5A, &ata66); 372 /* Reset TCBLID/FCBLID to output */ 373 pci_write_config_word(pdev, mcrbase + 2, mcr3); 374 375 if (ata66 & (2 >> ap->port_no)) 376 return ATA_CBL_PATA40; 377 else 378 return ATA_CBL_PATA80; 379 } 380 381 /** 382 * hpt37x_pre_reset - reset the hpt37x bus 383 * @link: ATA link to reset 384 * @deadline: deadline jiffies for the operation 385 * 386 * Perform the initial reset handling for the HPT37x. 387 */ 388 389 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) 390 { 391 struct ata_port *ap = link->ap; 392 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 393 static const struct pci_bits hpt37x_enable_bits[] = { 394 { 0x50, 1, 0x04, 0x04 }, 395 { 0x54, 1, 0x04, 0x04 } 396 }; 397 u8 mcr2; 398 399 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) 400 return -ENOENT; 401 402 /* Reset the state machine */ 403 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 404 udelay(100); 405 406 /* 407 * Disable the "fast interrupt" prediction. Don't hold off 408 * on interrupts. (== 0x01 despite what the docs say) 409 */ 410 pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2); 411 /* Is it HPT370/A? */ 412 if (pdev->device == PCI_DEVICE_ID_TTI_HPT366 && pdev->revision < 5) { 413 mcr2 &= ~0x02; 414 mcr2 |= 0x01; 415 } else { 416 mcr2 &= ~0x07; 417 } 418 pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2); 419 420 return ata_sff_prereset(link, deadline); 421 } 422 423 static void hpt37x_set_mode(struct ata_port *ap, struct ata_device *adev, 424 u8 mode) 425 { 426 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 427 int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 428 u32 reg, timing, mask; 429 430 /* Determine timing mask and find matching mode entry */ 431 if (mode < XFER_MW_DMA_0) 432 mask = 0xcfc3ffff; 433 else if (mode < XFER_UDMA_0) 434 mask = 0x31c001ff; 435 else 436 mask = 0x303c0000; 437 438 timing = hpt37x_find_mode(ap, mode); 439 440 pci_read_config_dword(pdev, addr, ®); 441 reg = (reg & ~mask) | (timing & mask); 442 pci_write_config_dword(pdev, addr, reg); 443 } 444 /** 445 * hpt37x_set_piomode - PIO setup 446 * @ap: ATA interface 447 * @adev: device on the interface 448 * 449 * Perform PIO mode setup. 450 */ 451 452 static void hpt37x_set_piomode(struct ata_port *ap, struct ata_device *adev) 453 { 454 hpt37x_set_mode(ap, adev, adev->pio_mode); 455 } 456 457 /** 458 * hpt37x_set_dmamode - DMA timing setup 459 * @ap: ATA interface 460 * @adev: Device being configured 461 * 462 * Set up the channel for MWDMA or UDMA modes. 463 */ 464 465 static void hpt37x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 466 { 467 hpt37x_set_mode(ap, adev, adev->dma_mode); 468 } 469 470 /** 471 * hpt370_bmdma_stop - DMA engine stop 472 * @qc: ATA command 473 * 474 * Work around the HPT370 DMA engine. 475 */ 476 477 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) 478 { 479 struct ata_port *ap = qc->ap; 480 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 481 void __iomem *bmdma = ap->ioaddr.bmdma_addr; 482 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 483 u8 dma_cmd; 484 485 if (dma_stat & ATA_DMA_ACTIVE) { 486 udelay(20); 487 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 488 } 489 if (dma_stat & ATA_DMA_ACTIVE) { 490 /* Clear the engine */ 491 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 492 udelay(10); 493 /* Stop DMA */ 494 dma_cmd = ioread8(bmdma + ATA_DMA_CMD); 495 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); 496 /* Clear Error */ 497 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 498 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, 499 bmdma + ATA_DMA_STATUS); 500 /* Clear the engine */ 501 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 502 udelay(10); 503 } 504 ata_bmdma_stop(qc); 505 } 506 507 /** 508 * hpt37x_bmdma_stop - DMA engine stop 509 * @qc: ATA command 510 * 511 * Clean up after the HPT372 and later DMA engine 512 */ 513 514 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) 515 { 516 struct ata_port *ap = qc->ap; 517 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 518 int mscreg = 0x50 + 4 * ap->port_no; 519 u8 bwsr_stat, msc_stat; 520 521 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 522 pci_read_config_byte(pdev, mscreg, &msc_stat); 523 if (bwsr_stat & (1 << ap->port_no)) 524 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 525 ata_bmdma_stop(qc); 526 } 527 528 529 static struct scsi_host_template hpt37x_sht = { 530 ATA_BMDMA_SHT(DRV_NAME), 531 }; 532 533 /* 534 * Configuration for HPT370 535 */ 536 537 static struct ata_port_operations hpt370_port_ops = { 538 .inherits = &ata_bmdma_port_ops, 539 540 .bmdma_stop = hpt370_bmdma_stop, 541 542 .mode_filter = hpt370_filter, 543 .cable_detect = hpt37x_cable_detect, 544 .set_piomode = hpt37x_set_piomode, 545 .set_dmamode = hpt37x_set_dmamode, 546 .prereset = hpt37x_pre_reset, 547 }; 548 549 /* 550 * Configuration for HPT370A. Close to 370 but less filters 551 */ 552 553 static struct ata_port_operations hpt370a_port_ops = { 554 .inherits = &hpt370_port_ops, 555 .mode_filter = hpt370a_filter, 556 }; 557 558 /* 559 * Configuration for HPT371 and HPT302. 560 */ 561 562 static struct ata_port_operations hpt302_port_ops = { 563 .inherits = &ata_bmdma_port_ops, 564 565 .bmdma_stop = hpt37x_bmdma_stop, 566 567 .cable_detect = hpt37x_cable_detect, 568 .set_piomode = hpt37x_set_piomode, 569 .set_dmamode = hpt37x_set_dmamode, 570 .prereset = hpt37x_pre_reset, 571 }; 572 573 /* 574 * Configuration for HPT372. Mode setting works like 371 and 302 575 * but we have a mode filter. 576 */ 577 578 static struct ata_port_operations hpt372_port_ops = { 579 .inherits = &hpt302_port_ops, 580 .mode_filter = hpt372_filter, 581 }; 582 583 /* 584 * Configuration for HPT374. Mode setting and filtering works like 372 585 * but we have a different cable detection procedure for function 1. 586 */ 587 588 static struct ata_port_operations hpt374_fn1_port_ops = { 589 .inherits = &hpt372_port_ops, 590 .cable_detect = hpt374_fn1_cable_detect, 591 }; 592 593 /** 594 * hpt37x_clock_slot - Turn timing to PC clock entry 595 * @freq: Reported frequency timing 596 * @base: Base timing 597 * 598 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 599 * and 3 for 66Mhz) 600 */ 601 602 static int hpt37x_clock_slot(unsigned int freq, unsigned int base) 603 { 604 unsigned int f = (base * freq) / 192; /* Mhz */ 605 if (f < 40) 606 return 0; /* 33Mhz slot */ 607 if (f < 45) 608 return 1; /* 40Mhz slot */ 609 if (f < 55) 610 return 2; /* 50Mhz slot */ 611 return 3; /* 60Mhz slot */ 612 } 613 614 /** 615 * hpt37x_calibrate_dpll - Calibrate the DPLL loop 616 * @dev: PCI device 617 * 618 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this 619 * succeeds 620 */ 621 622 static int hpt37x_calibrate_dpll(struct pci_dev *dev) 623 { 624 u8 reg5b; 625 u32 reg5c; 626 int tries; 627 628 for (tries = 0; tries < 0x5000; tries++) { 629 udelay(50); 630 pci_read_config_byte(dev, 0x5b, ®5b); 631 if (reg5b & 0x80) { 632 /* See if it stays set */ 633 for (tries = 0; tries < 0x1000; tries++) { 634 pci_read_config_byte(dev, 0x5b, ®5b); 635 /* Failed ? */ 636 if ((reg5b & 0x80) == 0) 637 return 0; 638 } 639 /* Turn off tuning, we have the DPLL set */ 640 pci_read_config_dword(dev, 0x5c, ®5c); 641 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); 642 return 1; 643 } 644 } 645 /* Never went stable */ 646 return 0; 647 } 648 649 static u32 hpt374_read_freq(struct pci_dev *pdev) 650 { 651 u32 freq; 652 unsigned long io_base = pci_resource_start(pdev, 4); 653 654 if (PCI_FUNC(pdev->devfn) & 1) { 655 struct pci_dev *pdev_0; 656 657 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); 658 /* Someone hot plugged the controller on us ? */ 659 if (pdev_0 == NULL) 660 return 0; 661 io_base = pci_resource_start(pdev_0, 4); 662 freq = inl(io_base + 0x90); 663 pci_dev_put(pdev_0); 664 } else 665 freq = inl(io_base + 0x90); 666 return freq; 667 } 668 669 /** 670 * hpt37x_init_one - Initialise an HPT37X/302 671 * @dev: PCI device 672 * @id: Entry in match table 673 * 674 * Initialise an HPT37x device. There are some interesting complications 675 * here. Firstly the chip may report 366 and be one of several variants. 676 * Secondly all the timings depend on the clock for the chip which we must 677 * detect and look up 678 * 679 * This is the known chip mappings. It may be missing a couple of later 680 * releases. 681 * 682 * Chip version PCI Rev Notes 683 * HPT366 4 (HPT366) 0 Other driver 684 * HPT366 4 (HPT366) 1 Other driver 685 * HPT368 4 (HPT366) 2 Other driver 686 * HPT370 4 (HPT366) 3 UDMA100 687 * HPT370A 4 (HPT366) 4 UDMA100 688 * HPT372 4 (HPT366) 5 UDMA133 (1) 689 * HPT372N 4 (HPT366) 6 Other driver 690 * HPT372A 5 (HPT372) 1 UDMA133 (1) 691 * HPT372N 5 (HPT372) 2 Other driver 692 * HPT302 6 (HPT302) 1 UDMA133 693 * HPT302N 6 (HPT302) 2 Other driver 694 * HPT371 7 (HPT371) * UDMA133 695 * HPT374 8 (HPT374) * UDMA133 4 channel 696 * HPT372N 9 (HPT372N) * Other driver 697 * 698 * (1) UDMA133 support depends on the bus clock 699 */ 700 701 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 702 { 703 /* HPT370 - UDMA100 */ 704 static const struct ata_port_info info_hpt370 = { 705 .flags = ATA_FLAG_SLAVE_POSS, 706 .pio_mask = ATA_PIO4, 707 .mwdma_mask = ATA_MWDMA2, 708 .udma_mask = ATA_UDMA5, 709 .port_ops = &hpt370_port_ops 710 }; 711 /* HPT370A - UDMA100 */ 712 static const struct ata_port_info info_hpt370a = { 713 .flags = ATA_FLAG_SLAVE_POSS, 714 .pio_mask = ATA_PIO4, 715 .mwdma_mask = ATA_MWDMA2, 716 .udma_mask = ATA_UDMA5, 717 .port_ops = &hpt370a_port_ops 718 }; 719 /* HPT370 - UDMA66 */ 720 static const struct ata_port_info info_hpt370_33 = { 721 .flags = ATA_FLAG_SLAVE_POSS, 722 .pio_mask = ATA_PIO4, 723 .mwdma_mask = ATA_MWDMA2, 724 .udma_mask = ATA_UDMA4, 725 .port_ops = &hpt370_port_ops 726 }; 727 /* HPT370A - UDMA66 */ 728 static const struct ata_port_info info_hpt370a_33 = { 729 .flags = ATA_FLAG_SLAVE_POSS, 730 .pio_mask = ATA_PIO4, 731 .mwdma_mask = ATA_MWDMA2, 732 .udma_mask = ATA_UDMA4, 733 .port_ops = &hpt370a_port_ops 734 }; 735 /* HPT372 - UDMA133 */ 736 static const struct ata_port_info info_hpt372 = { 737 .flags = ATA_FLAG_SLAVE_POSS, 738 .pio_mask = ATA_PIO4, 739 .mwdma_mask = ATA_MWDMA2, 740 .udma_mask = ATA_UDMA6, 741 .port_ops = &hpt372_port_ops 742 }; 743 /* HPT371, 302 - UDMA133 */ 744 static const struct ata_port_info info_hpt302 = { 745 .flags = ATA_FLAG_SLAVE_POSS, 746 .pio_mask = ATA_PIO4, 747 .mwdma_mask = ATA_MWDMA2, 748 .udma_mask = ATA_UDMA6, 749 .port_ops = &hpt302_port_ops 750 }; 751 /* HPT374 - UDMA100, function 1 uses different cable_detect method */ 752 static const struct ata_port_info info_hpt374_fn0 = { 753 .flags = ATA_FLAG_SLAVE_POSS, 754 .pio_mask = ATA_PIO4, 755 .mwdma_mask = ATA_MWDMA2, 756 .udma_mask = ATA_UDMA5, 757 .port_ops = &hpt372_port_ops 758 }; 759 static const struct ata_port_info info_hpt374_fn1 = { 760 .flags = ATA_FLAG_SLAVE_POSS, 761 .pio_mask = ATA_PIO4, 762 .mwdma_mask = ATA_MWDMA2, 763 .udma_mask = ATA_UDMA5, 764 .port_ops = &hpt374_fn1_port_ops 765 }; 766 767 static const int MHz[4] = { 33, 40, 50, 66 }; 768 void *private_data = NULL; 769 const struct ata_port_info *ppi[] = { NULL, NULL }; 770 u8 rev = dev->revision; 771 u8 irqmask; 772 u8 mcr1; 773 u32 freq; 774 int prefer_dpll = 1; 775 776 unsigned long iobase = pci_resource_start(dev, 4); 777 778 const struct hpt_chip *chip_table; 779 int clock_slot; 780 int rc; 781 782 rc = pcim_enable_device(dev); 783 if (rc) 784 return rc; 785 786 switch (dev->device) { 787 case PCI_DEVICE_ID_TTI_HPT366: 788 /* May be a later chip in disguise. Check */ 789 /* Older chips are in the HPT366 driver. Ignore them */ 790 if (rev < 3) 791 return -ENODEV; 792 /* N series chips have their own driver. Ignore */ 793 if (rev == 6) 794 return -ENODEV; 795 796 switch (rev) { 797 case 3: 798 ppi[0] = &info_hpt370; 799 chip_table = &hpt370; 800 prefer_dpll = 0; 801 break; 802 case 4: 803 ppi[0] = &info_hpt370a; 804 chip_table = &hpt370a; 805 prefer_dpll = 0; 806 break; 807 case 5: 808 ppi[0] = &info_hpt372; 809 chip_table = &hpt372; 810 break; 811 default: 812 dev_err(&dev->dev, 813 "Unknown HPT366 subtype, please report (%d)\n", 814 rev); 815 return -ENODEV; 816 } 817 break; 818 case PCI_DEVICE_ID_TTI_HPT372: 819 /* 372N if rev >= 2 */ 820 if (rev >= 2) 821 return -ENODEV; 822 ppi[0] = &info_hpt372; 823 chip_table = &hpt372a; 824 break; 825 case PCI_DEVICE_ID_TTI_HPT302: 826 /* 302N if rev > 1 */ 827 if (rev > 1) 828 return -ENODEV; 829 ppi[0] = &info_hpt302; 830 /* Check this */ 831 chip_table = &hpt302; 832 break; 833 case PCI_DEVICE_ID_TTI_HPT371: 834 if (rev > 1) 835 return -ENODEV; 836 ppi[0] = &info_hpt302; 837 chip_table = &hpt371; 838 /* 839 * Single channel device, master is not present but the BIOS 840 * (or us for non x86) must mark it absent 841 */ 842 pci_read_config_byte(dev, 0x50, &mcr1); 843 mcr1 &= ~0x04; 844 pci_write_config_byte(dev, 0x50, mcr1); 845 break; 846 case PCI_DEVICE_ID_TTI_HPT374: 847 chip_table = &hpt374; 848 if (!(PCI_FUNC(dev->devfn) & 1)) 849 *ppi = &info_hpt374_fn0; 850 else 851 *ppi = &info_hpt374_fn1; 852 break; 853 default: 854 dev_err(&dev->dev, "PCI table is bogus, please report (%d)\n", 855 dev->device); 856 return -ENODEV; 857 } 858 /* Ok so this is a chip we support */ 859 860 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 861 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 862 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 863 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 864 865 pci_read_config_byte(dev, 0x5A, &irqmask); 866 irqmask &= ~0x10; 867 pci_write_config_byte(dev, 0x5a, irqmask); 868 869 /* 870 * HPT371 chips physically have only one channel, the secondary one, 871 * but the primary channel registers do exist! Go figure... 872 * So, we manually disable the non-existing channel here 873 * (if the BIOS hasn't done this already). 874 */ 875 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { 876 u8 mcr1; 877 878 pci_read_config_byte(dev, 0x50, &mcr1); 879 mcr1 &= ~0x04; 880 pci_write_config_byte(dev, 0x50, mcr1); 881 } 882 883 /* 884 * default to pci clock. make sure MA15/16 are set to output 885 * to prevent drives having problems with 40-pin cables. Needed 886 * for some drives such as IBM-DTLA which will not enter ready 887 * state on reset when PDIAG is a input. 888 */ 889 890 pci_write_config_byte(dev, 0x5b, 0x23); 891 892 /* 893 * HighPoint does this for HPT372A. 894 * NOTE: This register is only writeable via I/O space. 895 */ 896 if (chip_table == &hpt372a) 897 outb(0x0e, iobase + 0x9c); 898 899 /* 900 * Some devices do not let this value be accessed via PCI space 901 * according to the old driver. In addition we must use the value 902 * from FN 0 on the HPT374. 903 */ 904 905 if (chip_table == &hpt374) { 906 freq = hpt374_read_freq(dev); 907 if (freq == 0) 908 return -ENODEV; 909 } else 910 freq = inl(iobase + 0x90); 911 912 if ((freq >> 12) != 0xABCDE) { 913 int i; 914 u16 sr; 915 u32 total = 0; 916 917 dev_warn(&dev->dev, "BIOS has not set timing clocks\n"); 918 919 /* This is the process the HPT371 BIOS is reported to use */ 920 for (i = 0; i < 128; i++) { 921 pci_read_config_word(dev, 0x78, &sr); 922 total += sr & 0x1FF; 923 udelay(15); 924 } 925 freq = total / 128; 926 } 927 freq &= 0x1FF; 928 929 /* 930 * Turn the frequency check into a band and then find a timing 931 * table to match it. 932 */ 933 934 clock_slot = hpt37x_clock_slot(freq, chip_table->base); 935 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { 936 /* 937 * We need to try PLL mode instead 938 * 939 * For non UDMA133 capable devices we should 940 * use a 50MHz DPLL by choice 941 */ 942 unsigned int f_low, f_high; 943 int dpll, adjust; 944 945 /* Compute DPLL */ 946 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; 947 948 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; 949 f_high = f_low + 2; 950 if (clock_slot > 1) 951 f_high += 2; 952 953 /* Select the DPLL clock. */ 954 pci_write_config_byte(dev, 0x5b, 0x21); 955 pci_write_config_dword(dev, 0x5C, 956 (f_high << 16) | f_low | 0x100); 957 958 for (adjust = 0; adjust < 8; adjust++) { 959 if (hpt37x_calibrate_dpll(dev)) 960 break; 961 /* 962 * See if it'll settle at a fractionally 963 * different clock 964 */ 965 if (adjust & 1) 966 f_low -= adjust >> 1; 967 else 968 f_high += adjust >> 1; 969 pci_write_config_dword(dev, 0x5C, 970 (f_high << 16) | f_low | 0x100); 971 } 972 if (adjust == 8) { 973 dev_err(&dev->dev, "DPLL did not stabilize!\n"); 974 return -ENODEV; 975 } 976 if (dpll == 3) 977 private_data = (void *)hpt37x_timings_66; 978 else 979 private_data = (void *)hpt37x_timings_50; 980 981 dev_info(&dev->dev, "bus clock %dMHz, using %dMHz DPLL\n", 982 MHz[clock_slot], MHz[dpll]); 983 } else { 984 private_data = (void *)chip_table->clocks[clock_slot]; 985 /* 986 * Perform a final fixup. Note that we will have used the 987 * DPLL on the HPT372 which means we don't have to worry 988 * about lack of UDMA133 support on lower clocks 989 */ 990 991 if (clock_slot < 2 && ppi[0] == &info_hpt370) 992 ppi[0] = &info_hpt370_33; 993 if (clock_slot < 2 && ppi[0] == &info_hpt370a) 994 ppi[0] = &info_hpt370a_33; 995 996 dev_info(&dev->dev, "%s using %dMHz bus clock\n", 997 chip_table->name, MHz[clock_slot]); 998 } 999 1000 /* Now kick off ATA set up */ 1001 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); 1002 } 1003 1004 static const struct pci_device_id hpt37x[] = { 1005 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 1006 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 1007 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 1008 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, 1009 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 1010 1011 { }, 1012 }; 1013 1014 static struct pci_driver hpt37x_pci_driver = { 1015 .name = DRV_NAME, 1016 .id_table = hpt37x, 1017 .probe = hpt37x_init_one, 1018 .remove = ata_pci_remove_one 1019 }; 1020 1021 module_pci_driver(hpt37x_pci_driver); 1022 1023 MODULE_AUTHOR("Alan Cox"); 1024 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); 1025 MODULE_LICENSE("GPL"); 1026 MODULE_DEVICE_TABLE(pci, hpt37x); 1027 MODULE_VERSION(DRV_VERSION); 1028