1 /* 2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers. 3 * 4 * This driver is heavily based upon: 5 * 6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 7 * 8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 10 * Portions Copyright (C) 2003 Red Hat Inc 11 * 12 * 13 * TODO 14 * Look into engine reset on timeout errors. Should not be required. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <scsi/scsi_host.h> 25 #include <linux/libata.h> 26 27 #define DRV_NAME "pata_hpt366" 28 #define DRV_VERSION "0.6.11" 29 30 struct hpt_clock { 31 u8 xfer_mode; 32 u32 timing; 33 }; 34 35 /* key for bus clock timings 36 * bit 37 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 38 * cycles = value + 1 39 * 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 40 * cycles = value + 1 41 * 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 42 * register access. 43 * 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file 44 * register access. 45 * 16:18 udma_cycle_time. Clock cycles for UDMA xfer? 46 * 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. 47 * 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file 48 * register access. 49 * 28 UDMA enable. 50 * 29 DMA enable. 51 * 30 PIO_MST enable. If set, the chip is in bus master mode during 52 * PIO xfer. 53 * 31 FIFO enable. 54 */ 55 56 static const struct hpt_clock hpt366_40[] = { 57 { XFER_UDMA_4, 0x900fd943 }, 58 { XFER_UDMA_3, 0x900ad943 }, 59 { XFER_UDMA_2, 0x900bd943 }, 60 { XFER_UDMA_1, 0x9008d943 }, 61 { XFER_UDMA_0, 0x9008d943 }, 62 63 { XFER_MW_DMA_2, 0xa008d943 }, 64 { XFER_MW_DMA_1, 0xa010d955 }, 65 { XFER_MW_DMA_0, 0xa010d9fc }, 66 67 { XFER_PIO_4, 0xc008d963 }, 68 { XFER_PIO_3, 0xc010d974 }, 69 { XFER_PIO_2, 0xc010d997 }, 70 { XFER_PIO_1, 0xc010d9c7 }, 71 { XFER_PIO_0, 0xc018d9d9 }, 72 { 0, 0x0120d9d9 } 73 }; 74 75 static const struct hpt_clock hpt366_33[] = { 76 { XFER_UDMA_4, 0x90c9a731 }, 77 { XFER_UDMA_3, 0x90cfa731 }, 78 { XFER_UDMA_2, 0x90caa731 }, 79 { XFER_UDMA_1, 0x90cba731 }, 80 { XFER_UDMA_0, 0x90c8a731 }, 81 82 { XFER_MW_DMA_2, 0xa0c8a731 }, 83 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */ 84 { XFER_MW_DMA_0, 0xa0c8a797 }, 85 86 { XFER_PIO_4, 0xc0c8a731 }, 87 { XFER_PIO_3, 0xc0c8a742 }, 88 { XFER_PIO_2, 0xc0d0a753 }, 89 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */ 90 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */ 91 { 0, 0x0120a7a7 } 92 }; 93 94 static const struct hpt_clock hpt366_25[] = { 95 { XFER_UDMA_4, 0x90c98521 }, 96 { XFER_UDMA_3, 0x90cf8521 }, 97 { XFER_UDMA_2, 0x90cf8521 }, 98 { XFER_UDMA_1, 0x90cb8521 }, 99 { XFER_UDMA_0, 0x90cb8521 }, 100 101 { XFER_MW_DMA_2, 0xa0ca8521 }, 102 { XFER_MW_DMA_1, 0xa0ca8532 }, 103 { XFER_MW_DMA_0, 0xa0ca8575 }, 104 105 { XFER_PIO_4, 0xc0ca8521 }, 106 { XFER_PIO_3, 0xc0ca8532 }, 107 { XFER_PIO_2, 0xc0ca8542 }, 108 { XFER_PIO_1, 0xc0d08572 }, 109 { XFER_PIO_0, 0xc0d08585 }, 110 { 0, 0x01208585 } 111 }; 112 113 /** 114 * hpt36x_find_mode - find the hpt36x timing 115 * @ap: ATA port 116 * @speed: transfer mode 117 * 118 * Return the 32bit register programming information for this channel 119 * that matches the speed provided. 120 */ 121 122 static u32 hpt36x_find_mode(struct ata_port *ap, int speed) 123 { 124 struct hpt_clock *clocks = ap->host->private_data; 125 126 while (clocks->xfer_mode) { 127 if (clocks->xfer_mode == speed) 128 return clocks->timing; 129 clocks++; 130 } 131 BUG(); 132 return 0xffffffffU; /* silence compiler warning */ 133 } 134 135 static const char * const bad_ata33[] = { 136 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", 137 "Maxtor 90845U3", "Maxtor 90650U2", 138 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", 139 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 140 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", 141 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 142 "Maxtor 90510D4", 143 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 144 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", 145 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 146 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", 147 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 148 NULL 149 }; 150 151 static const char * const bad_ata66_4[] = { 152 "IBM-DTLA-307075", 153 "IBM-DTLA-307060", 154 "IBM-DTLA-307045", 155 "IBM-DTLA-307030", 156 "IBM-DTLA-307020", 157 "IBM-DTLA-307015", 158 "IBM-DTLA-305040", 159 "IBM-DTLA-305030", 160 "IBM-DTLA-305020", 161 "IC35L010AVER07-0", 162 "IC35L020AVER07-0", 163 "IC35L030AVER07-0", 164 "IC35L040AVER07-0", 165 "IC35L060AVER07-0", 166 "WDC AC310200R", 167 NULL 168 }; 169 170 static const char * const bad_ata66_3[] = { 171 "WDC AC310200R", 172 NULL 173 }; 174 175 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, 176 const char * const list[]) 177 { 178 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 179 int i; 180 181 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 182 183 i = match_string(list, -1, model_num); 184 if (i >= 0) { 185 pr_warn("%s is not supported for %s\n", modestr, list[i]); 186 return 1; 187 } 188 return 0; 189 } 190 191 /** 192 * hpt366_filter - mode selection filter 193 * @adev: ATA device 194 * 195 * Block UDMA on devices that cause trouble with this controller. 196 */ 197 198 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask) 199 { 200 if (adev->class == ATA_DEV_ATA) { 201 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) 202 mask &= ~ATA_MASK_UDMA; 203 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3)) 204 mask &= ~(0xF8 << ATA_SHIFT_UDMA); 205 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4)) 206 mask &= ~(0xF0 << ATA_SHIFT_UDMA); 207 } else if (adev->class == ATA_DEV_ATAPI) 208 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); 209 210 return mask; 211 } 212 213 static int hpt36x_cable_detect(struct ata_port *ap) 214 { 215 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 216 u8 ata66; 217 218 /* 219 * Each channel of pata_hpt366 occupies separate PCI function 220 * as the primary channel and bit1 indicates the cable type. 221 */ 222 pci_read_config_byte(pdev, 0x5A, &ata66); 223 if (ata66 & 2) 224 return ATA_CBL_PATA40; 225 return ATA_CBL_PATA80; 226 } 227 228 static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev, 229 u8 mode) 230 { 231 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 232 u32 addr = 0x40 + 4 * adev->devno; 233 u32 mask, reg, t; 234 235 /* determine timing mask and find matching clock entry */ 236 if (mode < XFER_MW_DMA_0) 237 mask = 0xc1f8ffff; 238 else if (mode < XFER_UDMA_0) 239 mask = 0x303800ff; 240 else 241 mask = 0x30070000; 242 243 t = hpt36x_find_mode(ap, mode); 244 245 /* 246 * Combine new mode bits with old config bits and disable 247 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid 248 * problems handling I/O errors later. 249 */ 250 pci_read_config_dword(pdev, addr, ®); 251 reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000; 252 pci_write_config_dword(pdev, addr, reg); 253 } 254 255 /** 256 * hpt366_set_piomode - PIO setup 257 * @ap: ATA interface 258 * @adev: device on the interface 259 * 260 * Perform PIO mode setup. 261 */ 262 263 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev) 264 { 265 hpt366_set_mode(ap, adev, adev->pio_mode); 266 } 267 268 /** 269 * hpt366_set_dmamode - DMA timing setup 270 * @ap: ATA interface 271 * @adev: Device being configured 272 * 273 * Set up the channel for MWDMA or UDMA modes. Much the same as with 274 * PIO, load the mode number and then set MWDMA or UDMA flag. 275 */ 276 277 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev) 278 { 279 hpt366_set_mode(ap, adev, adev->dma_mode); 280 } 281 282 static struct scsi_host_template hpt36x_sht = { 283 ATA_BMDMA_SHT(DRV_NAME), 284 }; 285 286 /* 287 * Configuration for HPT366/68 288 */ 289 290 static struct ata_port_operations hpt366_port_ops = { 291 .inherits = &ata_bmdma_port_ops, 292 .cable_detect = hpt36x_cable_detect, 293 .mode_filter = hpt366_filter, 294 .set_piomode = hpt366_set_piomode, 295 .set_dmamode = hpt366_set_dmamode, 296 }; 297 298 /** 299 * hpt36x_init_chipset - common chip setup 300 * @dev: PCI device 301 * 302 * Perform the chip setup work that must be done at both init and 303 * resume time 304 */ 305 306 static void hpt36x_init_chipset(struct pci_dev *dev) 307 { 308 u8 drive_fast; 309 310 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 311 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 312 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 313 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 314 315 pci_read_config_byte(dev, 0x51, &drive_fast); 316 if (drive_fast & 0x80) 317 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80); 318 } 319 320 /** 321 * hpt36x_init_one - Initialise an HPT366/368 322 * @dev: PCI device 323 * @id: Entry in match table 324 * 325 * Initialise an HPT36x device. There are some interesting complications 326 * here. Firstly the chip may report 366 and be one of several variants. 327 * Secondly all the timings depend on the clock for the chip which we must 328 * detect and look up 329 * 330 * This is the known chip mappings. It may be missing a couple of later 331 * releases. 332 * 333 * Chip version PCI Rev Notes 334 * HPT366 4 (HPT366) 0 UDMA66 335 * HPT366 4 (HPT366) 1 UDMA66 336 * HPT368 4 (HPT366) 2 UDMA66 337 * HPT37x/30x 4 (HPT366) 3+ Other driver 338 * 339 */ 340 341 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 342 { 343 static const struct ata_port_info info_hpt366 = { 344 .flags = ATA_FLAG_SLAVE_POSS, 345 .pio_mask = ATA_PIO4, 346 .mwdma_mask = ATA_MWDMA2, 347 .udma_mask = ATA_UDMA4, 348 .port_ops = &hpt366_port_ops 349 }; 350 const struct ata_port_info *ppi[] = { &info_hpt366, NULL }; 351 352 const void *hpriv = NULL; 353 u32 reg1; 354 int rc; 355 356 rc = pcim_enable_device(dev); 357 if (rc) 358 return rc; 359 360 /* May be a later chip in disguise. Check */ 361 /* Newer chips are not in the HPT36x driver. Ignore them */ 362 if (dev->revision > 2) 363 return -ENODEV; 364 365 hpt36x_init_chipset(dev); 366 367 pci_read_config_dword(dev, 0x40, ®1); 368 369 /* PCI clocking determines the ATA timing values to use */ 370 /* info_hpt366 is safe against re-entry so we can scribble on it */ 371 switch ((reg1 & 0xf00) >> 8) { 372 case 9: 373 hpriv = &hpt366_40; 374 break; 375 case 5: 376 hpriv = &hpt366_25; 377 break; 378 default: 379 hpriv = &hpt366_33; 380 break; 381 } 382 /* Now kick off ATA set up */ 383 return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0); 384 } 385 386 #ifdef CONFIG_PM_SLEEP 387 static int hpt36x_reinit_one(struct pci_dev *dev) 388 { 389 struct ata_host *host = pci_get_drvdata(dev); 390 int rc; 391 392 rc = ata_pci_device_do_resume(dev); 393 if (rc) 394 return rc; 395 hpt36x_init_chipset(dev); 396 ata_host_resume(host); 397 return 0; 398 } 399 #endif 400 401 static const struct pci_device_id hpt36x[] = { 402 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 403 { }, 404 }; 405 406 static struct pci_driver hpt36x_pci_driver = { 407 .name = DRV_NAME, 408 .id_table = hpt36x, 409 .probe = hpt36x_init_one, 410 .remove = ata_pci_remove_one, 411 #ifdef CONFIG_PM_SLEEP 412 .suspend = ata_pci_device_suspend, 413 .resume = hpt36x_reinit_one, 414 #endif 415 }; 416 417 module_pci_driver(hpt36x_pci_driver); 418 419 MODULE_AUTHOR("Alan Cox"); 420 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368"); 421 MODULE_LICENSE("GPL"); 422 MODULE_DEVICE_TABLE(pci, hpt36x); 423 MODULE_VERSION(DRV_VERSION); 424