1 /* 2 * pata_cs5536.c - CS5536 PATA for new ATA layer 3 * (C) 2007 Martin K. Petersen <mkp@mkp.net> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 * Documentation: 19 * Available from AMD web site. 20 * 21 * The IDE timing registers for the CS5536 live in the Geode Machine 22 * Specific Register file and not PCI config space. Most BIOSes 23 * virtualize the PCI registers so the chip looks like a standard IDE 24 * controller. Unfortunately not all implementations get this right. 25 * In particular some have problems with unaligned accesses to the 26 * virtualized PCI registers. This driver always does full dword 27 * writes to work around the issue. Also, in case of a bad BIOS this 28 * driver can be loaded with the "msr=1" parameter which forces using 29 * the Machine Specific Registers to configure the device. 30 */ 31 32 #include <linux/kernel.h> 33 #include <linux/module.h> 34 #include <linux/pci.h> 35 #include <linux/init.h> 36 #include <linux/blkdev.h> 37 #include <linux/delay.h> 38 #include <linux/libata.h> 39 #include <scsi/scsi_host.h> 40 #include <asm/msr.h> 41 42 #define DRV_NAME "pata_cs5536" 43 #define DRV_VERSION "0.0.7" 44 45 enum { 46 CFG = 0, 47 DTC = 1, 48 CAST = 2, 49 ETC = 3, 50 51 MSR_IDE_BASE = 0x51300000, 52 MSR_IDE_CFG = (MSR_IDE_BASE + 0x10), 53 MSR_IDE_DTC = (MSR_IDE_BASE + 0x12), 54 MSR_IDE_CAST = (MSR_IDE_BASE + 0x13), 55 MSR_IDE_ETC = (MSR_IDE_BASE + 0x14), 56 57 PCI_IDE_CFG = 0x40, 58 PCI_IDE_DTC = 0x48, 59 PCI_IDE_CAST = 0x4c, 60 PCI_IDE_ETC = 0x50, 61 62 IDE_CFG_CHANEN = 0x2, 63 IDE_CFG_CABLE = 0x10000, 64 65 IDE_D0_SHIFT = 24, 66 IDE_D1_SHIFT = 16, 67 IDE_DRV_MASK = 0xff, 68 69 IDE_CAST_D0_SHIFT = 6, 70 IDE_CAST_D1_SHIFT = 4, 71 IDE_CAST_DRV_MASK = 0x3, 72 IDE_CAST_CMD_MASK = 0xff, 73 IDE_CAST_CMD_SHIFT = 24, 74 75 IDE_ETC_NODMA = 0x03, 76 }; 77 78 static int use_msr; 79 80 static const u32 msr_reg[4] = { 81 MSR_IDE_CFG, MSR_IDE_DTC, MSR_IDE_CAST, MSR_IDE_ETC, 82 }; 83 84 static const u8 pci_reg[4] = { 85 PCI_IDE_CFG, PCI_IDE_DTC, PCI_IDE_CAST, PCI_IDE_ETC, 86 }; 87 88 static inline int cs5536_read(struct pci_dev *pdev, int reg, u32 *val) 89 { 90 if (unlikely(use_msr)) { 91 u32 dummy; 92 93 rdmsr(msr_reg[reg], *val, dummy); 94 return 0; 95 } 96 97 return pci_read_config_dword(pdev, pci_reg[reg], val); 98 } 99 100 static inline int cs5536_write(struct pci_dev *pdev, int reg, int val) 101 { 102 if (unlikely(use_msr)) { 103 wrmsr(msr_reg[reg], val, 0); 104 return 0; 105 } 106 107 return pci_write_config_dword(pdev, pci_reg[reg], val); 108 } 109 110 /** 111 * cs5536_cable_detect - detect cable type 112 * @ap: Port to detect on 113 * 114 * Perform cable detection for ATA66 capable cable. Return a libata 115 * cable type. 116 */ 117 118 static int cs5536_cable_detect(struct ata_port *ap) 119 { 120 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 121 u32 cfg; 122 123 cs5536_read(pdev, CFG, &cfg); 124 125 if (cfg & (IDE_CFG_CABLE << ap->port_no)) 126 return ATA_CBL_PATA80; 127 else 128 return ATA_CBL_PATA40; 129 } 130 131 /** 132 * cs5536_set_piomode - PIO setup 133 * @ap: ATA interface 134 * @adev: device on the interface 135 */ 136 137 static void cs5536_set_piomode(struct ata_port *ap, struct ata_device *adev) 138 { 139 static const u8 drv_timings[5] = { 140 0x98, 0x55, 0x32, 0x21, 0x20, 141 }; 142 143 static const u8 addr_timings[5] = { 144 0x2, 0x1, 0x0, 0x0, 0x0, 145 }; 146 147 static const u8 cmd_timings[5] = { 148 0x99, 0x92, 0x90, 0x22, 0x20, 149 }; 150 151 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 152 struct ata_device *pair = ata_dev_pair(adev); 153 int mode = adev->pio_mode - XFER_PIO_0; 154 int cmdmode = mode; 155 int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT; 156 int cshift = adev->devno ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT; 157 u32 dtc, cast, etc; 158 159 if (pair) 160 cmdmode = min(mode, pair->pio_mode - XFER_PIO_0); 161 162 cs5536_read(pdev, DTC, &dtc); 163 cs5536_read(pdev, CAST, &cast); 164 cs5536_read(pdev, ETC, &etc); 165 166 dtc &= ~(IDE_DRV_MASK << dshift); 167 dtc |= drv_timings[mode] << dshift; 168 169 cast &= ~(IDE_CAST_DRV_MASK << cshift); 170 cast |= addr_timings[mode] << cshift; 171 172 cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT); 173 cast |= cmd_timings[cmdmode] << IDE_CAST_CMD_SHIFT; 174 175 etc &= ~(IDE_DRV_MASK << dshift); 176 etc |= IDE_ETC_NODMA << dshift; 177 178 cs5536_write(pdev, DTC, dtc); 179 cs5536_write(pdev, CAST, cast); 180 cs5536_write(pdev, ETC, etc); 181 } 182 183 /** 184 * cs5536_set_dmamode - DMA timing setup 185 * @ap: ATA interface 186 * @adev: Device being configured 187 * 188 */ 189 190 static void cs5536_set_dmamode(struct ata_port *ap, struct ata_device *adev) 191 { 192 static const u8 udma_timings[6] = { 193 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 194 }; 195 196 static const u8 mwdma_timings[3] = { 197 0x67, 0x21, 0x20, 198 }; 199 200 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 201 u32 dtc, etc; 202 int mode = adev->dma_mode; 203 int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT; 204 205 if (mode >= XFER_UDMA_0) { 206 cs5536_read(pdev, ETC, &etc); 207 208 etc &= ~(IDE_DRV_MASK << dshift); 209 etc |= udma_timings[mode - XFER_UDMA_0] << dshift; 210 211 cs5536_write(pdev, ETC, etc); 212 } else { /* MWDMA */ 213 cs5536_read(pdev, DTC, &dtc); 214 215 dtc &= ~(IDE_DRV_MASK << dshift); 216 dtc |= mwdma_timings[mode - XFER_MW_DMA_0] << dshift; 217 218 cs5536_write(pdev, DTC, dtc); 219 } 220 } 221 222 static struct scsi_host_template cs5536_sht = { 223 ATA_BMDMA_SHT(DRV_NAME), 224 }; 225 226 static struct ata_port_operations cs5536_port_ops = { 227 .inherits = &ata_bmdma32_port_ops, 228 .cable_detect = cs5536_cable_detect, 229 .set_piomode = cs5536_set_piomode, 230 .set_dmamode = cs5536_set_dmamode, 231 }; 232 233 /** 234 * cs5536_init_one 235 * @dev: PCI device 236 * @id: Entry in match table 237 * 238 */ 239 240 static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id) 241 { 242 static const struct ata_port_info info = { 243 .flags = ATA_FLAG_SLAVE_POSS, 244 .pio_mask = ATA_PIO4, 245 .mwdma_mask = ATA_MWDMA2, 246 .udma_mask = ATA_UDMA5, 247 .port_ops = &cs5536_port_ops, 248 }; 249 250 const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info }; 251 u32 cfg; 252 253 if (use_msr) 254 printk(KERN_ERR DRV_NAME ": Using MSR regs instead of PCI\n"); 255 256 cs5536_read(dev, CFG, &cfg); 257 258 if ((cfg & IDE_CFG_CHANEN) == 0) { 259 printk(KERN_ERR DRV_NAME ": disabled by BIOS\n"); 260 return -ENODEV; 261 } 262 263 return ata_pci_sff_init_one(dev, ppi, &cs5536_sht, NULL); 264 } 265 266 static const struct pci_device_id cs5536[] = { 267 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), }, 268 { }, 269 }; 270 271 static struct pci_driver cs5536_pci_driver = { 272 .name = DRV_NAME, 273 .id_table = cs5536, 274 .probe = cs5536_init_one, 275 .remove = ata_pci_remove_one, 276 #ifdef CONFIG_PM 277 .suspend = ata_pci_device_suspend, 278 .resume = ata_pci_device_resume, 279 #endif 280 }; 281 282 static int __init cs5536_init(void) 283 { 284 return pci_register_driver(&cs5536_pci_driver); 285 } 286 287 static void __exit cs5536_exit(void) 288 { 289 pci_unregister_driver(&cs5536_pci_driver); 290 } 291 292 MODULE_AUTHOR("Martin K. Petersen"); 293 MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller"); 294 MODULE_LICENSE("GPL"); 295 MODULE_DEVICE_TABLE(pci, cs5536); 296 MODULE_VERSION(DRV_VERSION); 297 module_param_named(msr, use_msr, int, 0644); 298 MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)"); 299 300 module_init(cs5536_init); 301 module_exit(cs5536_exit); 302