1 /* 2 * pata-cs5530.c - CS5530 PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * based upon cs5530.c by Mark Lord. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 * Loosely based on the piix & svwks drivers. 22 * 23 * Documentation: 24 * Available from AMD web site. 25 */ 26 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/blkdev.h> 32 #include <linux/delay.h> 33 #include <scsi/scsi_host.h> 34 #include <linux/libata.h> 35 #include <linux/dmi.h> 36 37 #define DRV_NAME "pata_cs5530" 38 #define DRV_VERSION "0.7.4" 39 40 static void __iomem *cs5530_port_base(struct ata_port *ap) 41 { 42 unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr; 43 44 return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no); 45 } 46 47 /** 48 * cs5530_set_piomode - PIO setup 49 * @ap: ATA interface 50 * @adev: device on the interface 51 * 52 * Set our PIO requirements. This is fairly simple on the CS5530 53 * chips. 54 */ 55 56 static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev) 57 { 58 static const unsigned int cs5530_pio_timings[2][5] = { 59 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, 60 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010} 61 }; 62 void __iomem *base = cs5530_port_base(ap); 63 u32 tuning; 64 int format; 65 66 /* Find out which table to use */ 67 tuning = ioread32(base + 0x04); 68 format = (tuning & 0x80000000UL) ? 1 : 0; 69 70 /* Now load the right timing register */ 71 if (adev->devno) 72 base += 0x08; 73 74 iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); 75 } 76 77 /** 78 * cs5530_set_dmamode - DMA timing setup 79 * @ap: ATA interface 80 * @adev: Device being configured 81 * 82 * We cannot mix MWDMA and UDMA without reloading timings each switch 83 * master to slave. We track the last DMA setup in order to minimise 84 * reloads. 85 */ 86 87 static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev) 88 { 89 void __iomem *base = cs5530_port_base(ap); 90 u32 tuning, timing = 0; 91 u8 reg; 92 93 /* Find out which table to use */ 94 tuning = ioread32(base + 0x04); 95 96 switch(adev->dma_mode) { 97 case XFER_UDMA_0: 98 timing = 0x00921250;break; 99 case XFER_UDMA_1: 100 timing = 0x00911140;break; 101 case XFER_UDMA_2: 102 timing = 0x00911030;break; 103 case XFER_MW_DMA_0: 104 timing = 0x00077771;break; 105 case XFER_MW_DMA_1: 106 timing = 0x00012121;break; 107 case XFER_MW_DMA_2: 108 timing = 0x00002020;break; 109 default: 110 BUG(); 111 } 112 /* Merge in the PIO format bit */ 113 timing |= (tuning & 0x80000000UL); 114 if (adev->devno == 0) /* Master */ 115 iowrite32(timing, base + 0x04); 116 else { 117 if (timing & 0x00100000) 118 tuning |= 0x00100000; /* UDMA for both */ 119 else 120 tuning &= ~0x00100000; /* MWDMA for both */ 121 iowrite32(tuning, base + 0x04); 122 iowrite32(timing, base + 0x0C); 123 } 124 125 /* Set the DMA capable bit in the BMDMA area */ 126 reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 127 reg |= (1 << (5 + adev->devno)); 128 iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 129 130 /* Remember the last DMA setup we did */ 131 132 ap->private_data = adev; 133 } 134 135 /** 136 * cs5530_qc_issue_prot - command issue 137 * @qc: command pending 138 * 139 * Called when the libata layer is about to issue a command. We wrap 140 * this interface so that we can load the correct ATA timings if 141 * necessary. Specifically we have a problem that there is only 142 * one MWDMA/UDMA bit. 143 */ 144 145 static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc) 146 { 147 struct ata_port *ap = qc->ap; 148 struct ata_device *adev = qc->dev; 149 struct ata_device *prev = ap->private_data; 150 151 /* See if the DMA settings could be wrong */ 152 if (adev->dma_mode != 0 && adev != prev && prev != NULL) { 153 /* Maybe, but do the channels match MWDMA/UDMA ? */ 154 if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) || 155 (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0)) 156 /* Switch the mode bits */ 157 cs5530_set_dmamode(ap, adev); 158 } 159 160 return ata_qc_issue_prot(qc); 161 } 162 163 static struct scsi_host_template cs5530_sht = { 164 .module = THIS_MODULE, 165 .name = DRV_NAME, 166 .ioctl = ata_scsi_ioctl, 167 .queuecommand = ata_scsi_queuecmd, 168 .can_queue = ATA_DEF_QUEUE, 169 .this_id = ATA_SHT_THIS_ID, 170 .sg_tablesize = LIBATA_DUMB_MAX_PRD, 171 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 172 .emulated = ATA_SHT_EMULATED, 173 .use_clustering = ATA_SHT_USE_CLUSTERING, 174 .proc_name = DRV_NAME, 175 .dma_boundary = ATA_DMA_BOUNDARY, 176 .slave_configure = ata_scsi_slave_config, 177 .slave_destroy = ata_scsi_slave_destroy, 178 .bios_param = ata_std_bios_param, 179 }; 180 181 static struct ata_port_operations cs5530_port_ops = { 182 .set_piomode = cs5530_set_piomode, 183 .set_dmamode = cs5530_set_dmamode, 184 .mode_filter = ata_pci_default_filter, 185 186 .tf_load = ata_tf_load, 187 .tf_read = ata_tf_read, 188 .check_status = ata_check_status, 189 .exec_command = ata_exec_command, 190 .dev_select = ata_std_dev_select, 191 192 .bmdma_setup = ata_bmdma_setup, 193 .bmdma_start = ata_bmdma_start, 194 .bmdma_stop = ata_bmdma_stop, 195 .bmdma_status = ata_bmdma_status, 196 197 .freeze = ata_bmdma_freeze, 198 .thaw = ata_bmdma_thaw, 199 .error_handler = ata_bmdma_error_handler, 200 .post_internal_cmd = ata_bmdma_post_internal_cmd, 201 .cable_detect = ata_cable_40wire, 202 203 .qc_prep = ata_dumb_qc_prep, 204 .qc_issue = cs5530_qc_issue_prot, 205 206 .data_xfer = ata_data_xfer, 207 208 .irq_handler = ata_interrupt, 209 .irq_clear = ata_bmdma_irq_clear, 210 .irq_on = ata_irq_on, 211 212 .port_start = ata_sff_port_start, 213 }; 214 215 static const struct dmi_system_id palmax_dmi_table[] = { 216 { 217 .ident = "Palmax PD1100", 218 .matches = { 219 DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"), 220 DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"), 221 }, 222 }, 223 { } 224 }; 225 226 static int cs5530_is_palmax(void) 227 { 228 if (dmi_check_system(palmax_dmi_table)) { 229 printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n"); 230 return 1; 231 } 232 return 0; 233 } 234 235 236 /** 237 * cs5530_init_chip - Chipset init 238 * 239 * Perform the chip initialisation work that is shared between both 240 * setup and resume paths 241 */ 242 243 static int cs5530_init_chip(void) 244 { 245 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL; 246 247 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) { 248 switch (dev->device) { 249 case PCI_DEVICE_ID_CYRIX_PCI_MASTER: 250 master_0 = pci_dev_get(dev); 251 break; 252 case PCI_DEVICE_ID_CYRIX_5530_LEGACY: 253 cs5530_0 = pci_dev_get(dev); 254 break; 255 } 256 } 257 if (!master_0) { 258 printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n"); 259 goto fail_put; 260 } 261 if (!cs5530_0) { 262 printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n"); 263 goto fail_put; 264 } 265 266 pci_set_master(cs5530_0); 267 pci_try_set_mwi(cs5530_0); 268 269 /* 270 * Set PCI CacheLineSize to 16-bytes: 271 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530 272 * 273 * Note: This value is constant because the 5530 is only a Geode companion 274 */ 275 276 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04); 277 278 /* 279 * Disable trapping of UDMA register accesses (Win98 hack): 280 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530 281 */ 282 283 pci_write_config_word(cs5530_0, 0xd0, 0x5006); 284 285 /* 286 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus: 287 * The other settings are what is necessary to get the register 288 * into a sane state for IDE DMA operation. 289 */ 290 291 pci_write_config_byte(master_0, 0x40, 0x1e); 292 293 /* 294 * Set max PCI burst size (16-bytes seems to work best): 295 * 16bytes: set bit-1 at 0x41 (reg value of 0x16) 296 * all others: clear bit-1 at 0x41, and do: 297 * 128bytes: OR 0x00 at 0x41 298 * 256bytes: OR 0x04 at 0x41 299 * 512bytes: OR 0x08 at 0x41 300 * 1024bytes: OR 0x0c at 0x41 301 */ 302 303 pci_write_config_byte(master_0, 0x41, 0x14); 304 305 /* 306 * These settings are necessary to get the chip 307 * into a sane state for IDE DMA operation. 308 */ 309 310 pci_write_config_byte(master_0, 0x42, 0x00); 311 pci_write_config_byte(master_0, 0x43, 0xc1); 312 313 pci_dev_put(master_0); 314 pci_dev_put(cs5530_0); 315 return 0; 316 fail_put: 317 if (master_0) 318 pci_dev_put(master_0); 319 if (cs5530_0) 320 pci_dev_put(cs5530_0); 321 return -ENODEV; 322 } 323 324 /** 325 * cs5530_init_one - Initialise a CS5530 326 * @dev: PCI device 327 * @id: Entry in match table 328 * 329 * Install a driver for the newly found CS5530 companion chip. Most of 330 * this is just housekeeping. We have to set the chip up correctly and 331 * turn off various bits of emulation magic. 332 */ 333 334 static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 335 { 336 static const struct ata_port_info info = { 337 .sht = &cs5530_sht, 338 .flags = ATA_FLAG_SLAVE_POSS, 339 .pio_mask = 0x1f, 340 .mwdma_mask = 0x07, 341 .udma_mask = 0x07, 342 .port_ops = &cs5530_port_ops 343 }; 344 /* The docking connector doesn't do UDMA, and it seems not MWDMA */ 345 static const struct ata_port_info info_palmax_secondary = { 346 .sht = &cs5530_sht, 347 .flags = ATA_FLAG_SLAVE_POSS, 348 .pio_mask = 0x1f, 349 .port_ops = &cs5530_port_ops 350 }; 351 const struct ata_port_info *ppi[] = { &info, NULL }; 352 353 /* Chip initialisation */ 354 if (cs5530_init_chip()) 355 return -ENODEV; 356 357 if (cs5530_is_palmax()) 358 ppi[1] = &info_palmax_secondary; 359 360 /* Now kick off ATA set up */ 361 return ata_pci_init_one(pdev, ppi); 362 } 363 364 #ifdef CONFIG_PM 365 static int cs5530_reinit_one(struct pci_dev *pdev) 366 { 367 /* If we fail on resume we are doomed */ 368 if (cs5530_init_chip()) 369 BUG(); 370 return ata_pci_device_resume(pdev); 371 } 372 #endif /* CONFIG_PM */ 373 374 static const struct pci_device_id cs5530[] = { 375 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), }, 376 377 { }, 378 }; 379 380 static struct pci_driver cs5530_pci_driver = { 381 .name = DRV_NAME, 382 .id_table = cs5530, 383 .probe = cs5530_init_one, 384 .remove = ata_pci_remove_one, 385 #ifdef CONFIG_PM 386 .suspend = ata_pci_device_suspend, 387 .resume = cs5530_reinit_one, 388 #endif 389 }; 390 391 static int __init cs5530_init(void) 392 { 393 return pci_register_driver(&cs5530_pci_driver); 394 } 395 396 static void __exit cs5530_exit(void) 397 { 398 pci_unregister_driver(&cs5530_pci_driver); 399 } 400 401 MODULE_AUTHOR("Alan Cox"); 402 MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530"); 403 MODULE_LICENSE("GPL"); 404 MODULE_DEVICE_TABLE(pci, cs5530); 405 MODULE_VERSION(DRV_VERSION); 406 407 module_init(cs5530_init); 408 module_exit(cs5530_exit); 409