1 /* 2 * IDE tuning and bus mastering support for the CS5510/CS5520 3 * chipsets 4 * 5 * The CS5510/CS5520 are slightly unusual devices. Unlike the 6 * typical IDE controllers they do bus mastering with the drive in 7 * PIO mode and smarter silicon. 8 * 9 * The practical upshot of this is that we must always tune the 10 * drive for the right PIO mode. We must also ignore all the blacklists 11 * and the drive bus mastering DMA information. Also to confuse matters 12 * further we can do DMA on PIO only drives. 13 * 14 * DMA on the 5510 also requires we disable_hlt() during DMA on early 15 * revisions. 16 * 17 * *** This driver is strictly experimental *** 18 * 19 * (c) Copyright Red Hat Inc 2002 20 * 21 * This program is free software; you can redistribute it and/or modify it 22 * under the terms of the GNU General Public License as published by the 23 * Free Software Foundation; either version 2, or (at your option) any 24 * later version. 25 * 26 * This program is distributed in the hope that it will be useful, but 27 * WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 29 * General Public License for more details. 30 * 31 * Documentation: 32 * Not publically available. 33 */ 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/init.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <scsi/scsi_host.h> 41 #include <linux/libata.h> 42 43 #define DRV_NAME "pata_cs5520" 44 #define DRV_VERSION "0.6.6" 45 46 struct pio_clocks 47 { 48 int address; 49 int assert; 50 int recovery; 51 }; 52 53 static const struct pio_clocks cs5520_pio_clocks[]={ 54 {3, 6, 11}, 55 {2, 5, 6}, 56 {1, 4, 3}, 57 {1, 3, 2}, 58 {1, 2, 1} 59 }; 60 61 /** 62 * cs5520_set_timings - program PIO timings 63 * @ap: ATA port 64 * @adev: ATA device 65 * 66 * Program the PIO mode timings for the controller according to the pio 67 * clocking table. 68 */ 69 70 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) 71 { 72 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 73 int slave = adev->devno; 74 75 pio -= XFER_PIO_0; 76 77 /* Channel command timing */ 78 pci_write_config_byte(pdev, 0x62 + ap->port_no, 79 (cs5520_pio_clocks[pio].recovery << 4) | 80 (cs5520_pio_clocks[pio].assert)); 81 /* FIXME: should these use address ? */ 82 /* Read command timing */ 83 pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave, 84 (cs5520_pio_clocks[pio].recovery << 4) | 85 (cs5520_pio_clocks[pio].assert)); 86 /* Write command timing */ 87 pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave, 88 (cs5520_pio_clocks[pio].recovery << 4) | 89 (cs5520_pio_clocks[pio].assert)); 90 } 91 92 /** 93 * cs5520_enable_dma - turn on DMA bits 94 * 95 * Turn on the DMA bits for this disk. Needed because the BIOS probably 96 * has not done the work for us. Belongs in the core SATA code. 97 */ 98 99 static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev) 100 { 101 /* Set the DMA enable/disable flag */ 102 u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02); 103 reg |= 1<<(adev->devno + 5); 104 iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02); 105 } 106 107 /** 108 * cs5520_set_dmamode - program DMA timings 109 * @ap: ATA port 110 * @adev: ATA device 111 * 112 * Program the DMA mode timings for the controller according to the pio 113 * clocking table. Note that this device sets the DMA timings to PIO 114 * mode values. This may seem bizarre but the 5520 architecture talks 115 * PIO mode to the disk and DMA mode to the controller so the underlying 116 * transfers are PIO timed. 117 */ 118 119 static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev) 120 { 121 static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 }; 122 cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]); 123 cs5520_enable_dma(ap, adev); 124 } 125 126 /** 127 * cs5520_set_piomode - program PIO timings 128 * @ap: ATA port 129 * @adev: ATA device 130 * 131 * Program the PIO mode timings for the controller according to the pio 132 * clocking table. We know pio_mode will equal dma_mode because of the 133 * CS5520 architecture. At least once we turned DMA on and wrote a 134 * mode setter. 135 */ 136 137 static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev) 138 { 139 cs5520_set_timings(ap, adev, adev->pio_mode); 140 } 141 142 static struct scsi_host_template cs5520_sht = { 143 .module = THIS_MODULE, 144 .name = DRV_NAME, 145 .ioctl = ata_scsi_ioctl, 146 .queuecommand = ata_scsi_queuecmd, 147 .can_queue = ATA_DEF_QUEUE, 148 .this_id = ATA_SHT_THIS_ID, 149 .sg_tablesize = LIBATA_DUMB_MAX_PRD, 150 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 151 .emulated = ATA_SHT_EMULATED, 152 .use_clustering = ATA_SHT_USE_CLUSTERING, 153 .proc_name = DRV_NAME, 154 .dma_boundary = ATA_DMA_BOUNDARY, 155 .slave_configure = ata_scsi_slave_config, 156 .slave_destroy = ata_scsi_slave_destroy, 157 .bios_param = ata_std_bios_param, 158 }; 159 160 static struct ata_port_operations cs5520_port_ops = { 161 .set_piomode = cs5520_set_piomode, 162 .set_dmamode = cs5520_set_dmamode, 163 164 .tf_load = ata_tf_load, 165 .tf_read = ata_tf_read, 166 .check_status = ata_check_status, 167 .exec_command = ata_exec_command, 168 .dev_select = ata_std_dev_select, 169 170 .freeze = ata_bmdma_freeze, 171 .thaw = ata_bmdma_thaw, 172 .error_handler = ata_bmdma_error_handler, 173 .post_internal_cmd = ata_bmdma_post_internal_cmd, 174 .cable_detect = ata_cable_40wire, 175 176 .bmdma_setup = ata_bmdma_setup, 177 .bmdma_start = ata_bmdma_start, 178 .bmdma_stop = ata_bmdma_stop, 179 .bmdma_status = ata_bmdma_status, 180 .qc_prep = ata_dumb_qc_prep, 181 .qc_issue = ata_qc_issue_prot, 182 .data_xfer = ata_data_xfer, 183 184 .irq_clear = ata_bmdma_irq_clear, 185 .irq_on = ata_irq_on, 186 187 .port_start = ata_sff_port_start, 188 }; 189 190 static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 191 { 192 static const unsigned int cmd_port[] = { 0x1F0, 0x170 }; 193 static const unsigned int ctl_port[] = { 0x3F6, 0x376 }; 194 struct ata_port_info pi = { 195 .flags = ATA_FLAG_SLAVE_POSS, 196 .pio_mask = 0x1f, 197 .port_ops = &cs5520_port_ops, 198 }; 199 const struct ata_port_info *ppi[2]; 200 u8 pcicfg; 201 void __iomem *iomap[5]; 202 struct ata_host *host; 203 struct ata_ioports *ioaddr; 204 int i, rc; 205 206 /* IDE port enable bits */ 207 pci_read_config_byte(pdev, 0x60, &pcicfg); 208 209 /* Check if the ATA ports are enabled */ 210 if ((pcicfg & 3) == 0) 211 return -ENODEV; 212 213 ppi[0] = ppi[1] = &ata_dummy_port_info; 214 if (pcicfg & 1) 215 ppi[0] = π 216 if (pcicfg & 2) 217 ppi[1] = π 218 219 if ((pcicfg & 0x40) == 0) { 220 dev_printk(KERN_WARNING, &pdev->dev, 221 "DMA mode disabled. Enabling.\n"); 222 pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); 223 } 224 225 pi.mwdma_mask = id->driver_data; 226 227 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 228 if (!host) 229 return -ENOMEM; 230 231 /* Perform set up for DMA */ 232 if (pci_enable_device_io(pdev)) { 233 printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n"); 234 return -ENODEV; 235 } 236 237 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { 238 printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n"); 239 return -ENODEV; 240 } 241 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { 242 printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n"); 243 return -ENODEV; 244 } 245 246 /* Map IO ports and initialize host accordingly */ 247 iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8); 248 iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1); 249 iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8); 250 iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1); 251 iomap[4] = pcim_iomap(pdev, 2, 0); 252 253 if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) 254 return -ENOMEM; 255 256 ioaddr = &host->ports[0]->ioaddr; 257 ioaddr->cmd_addr = iomap[0]; 258 ioaddr->ctl_addr = iomap[1]; 259 ioaddr->altstatus_addr = iomap[1]; 260 ioaddr->bmdma_addr = iomap[4]; 261 ata_std_ports(ioaddr); 262 263 ata_port_desc(host->ports[0], 264 "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]); 265 ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma"); 266 267 ioaddr = &host->ports[1]->ioaddr; 268 ioaddr->cmd_addr = iomap[2]; 269 ioaddr->ctl_addr = iomap[3]; 270 ioaddr->altstatus_addr = iomap[3]; 271 ioaddr->bmdma_addr = iomap[4] + 8; 272 ata_std_ports(ioaddr); 273 274 ata_port_desc(host->ports[1], 275 "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]); 276 ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma"); 277 278 /* activate the host */ 279 pci_set_master(pdev); 280 rc = ata_host_start(host); 281 if (rc) 282 return rc; 283 284 for (i = 0; i < 2; i++) { 285 static const int irq[] = { 14, 15 }; 286 struct ata_port *ap = host->ports[i]; 287 288 if (ata_port_is_dummy(ap)) 289 continue; 290 291 rc = devm_request_irq(&pdev->dev, irq[ap->port_no], 292 ata_interrupt, 0, DRV_NAME, host); 293 if (rc) 294 return rc; 295 296 ata_port_desc(ap, "irq %d", irq[i]); 297 } 298 299 return ata_host_register(host, &cs5520_sht); 300 } 301 302 #ifdef CONFIG_PM 303 /** 304 * cs5520_reinit_one - device resume 305 * @pdev: PCI device 306 * 307 * Do any reconfiguration work needed by a resume from RAM. We need 308 * to restore DMA mode support on BIOSen which disabled it 309 */ 310 311 static int cs5520_reinit_one(struct pci_dev *pdev) 312 { 313 u8 pcicfg; 314 pci_read_config_byte(pdev, 0x60, &pcicfg); 315 if ((pcicfg & 0x40) == 0) 316 pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); 317 return ata_pci_device_resume(pdev); 318 } 319 320 /** 321 * cs5520_pci_device_suspend - device suspend 322 * @pdev: PCI device 323 * 324 * We have to cut and waste bits from the standard method because 325 * the 5520 is a bit odd and not just a pure ATA device. As a result 326 * we must not disable it. The needed code is short and this avoids 327 * chip specific mess in the core code. 328 */ 329 330 static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 331 { 332 struct ata_host *host = dev_get_drvdata(&pdev->dev); 333 int rc = 0; 334 335 rc = ata_host_suspend(host, mesg); 336 if (rc) 337 return rc; 338 339 pci_save_state(pdev); 340 return 0; 341 } 342 #endif /* CONFIG_PM */ 343 344 /* For now keep DMA off. We can set it for all but A rev CS5510 once the 345 core ATA code can handle it */ 346 347 static const struct pci_device_id pata_cs5520[] = { 348 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), }, 349 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), }, 350 351 { }, 352 }; 353 354 static struct pci_driver cs5520_pci_driver = { 355 .name = DRV_NAME, 356 .id_table = pata_cs5520, 357 .probe = cs5520_init_one, 358 .remove = ata_pci_remove_one, 359 #ifdef CONFIG_PM 360 .suspend = cs5520_pci_device_suspend, 361 .resume = cs5520_reinit_one, 362 #endif 363 }; 364 365 static int __init cs5520_init(void) 366 { 367 return pci_register_driver(&cs5520_pci_driver); 368 } 369 370 static void __exit cs5520_exit(void) 371 { 372 pci_unregister_driver(&cs5520_pci_driver); 373 } 374 375 MODULE_AUTHOR("Alan Cox"); 376 MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520"); 377 MODULE_LICENSE("GPL"); 378 MODULE_DEVICE_TABLE(pci, pata_cs5520); 379 MODULE_VERSION(DRV_VERSION); 380 381 module_init(cs5520_init); 382 module_exit(cs5520_exit); 383 384