xref: /openbmc/linux/drivers/ata/pata_cmd64x.c (revision b6dcefde)
1 /*
2  * pata_cmd64x.c 	- CMD64x PATA for new ATA layer
3  *			  (C) 2005 Red Hat Inc
4  *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
5  *
6  * Based upon
7  * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
8  *
9  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
10  *           Note, this driver is not used at all on other systems because
11  *           there the "BIOS" has done all of the following already.
12  *           Due to massive hardware bugs, UltraDMA is only supported
13  *           on the 646U2 and not on the 646U.
14  *
15  * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
16  * Copyright (C) 1998		David S. Miller (davem@redhat.com)
17  *
18  * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
19  *
20  * TODO
21  *	Testing work
22  */
23 
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <scsi/scsi_host.h>
31 #include <linux/libata.h>
32 
33 #define DRV_NAME "pata_cmd64x"
34 #define DRV_VERSION "0.2.5"
35 
36 /*
37  * CMD64x specific registers definition.
38  */
39 
40 enum {
41 	CFR 		= 0x50,
42 		CFR_INTR_CH0  = 0x02,
43 	CNTRL 		= 0x51,
44 		CNTRL_DIS_RA0 = 0x40,
45 		CNTRL_DIS_RA1 = 0x80,
46 		CNTRL_ENA_2ND = 0x08,
47 	CMDTIM 		= 0x52,
48 	ARTTIM0 	= 0x53,
49 	DRWTIM0 	= 0x54,
50 	ARTTIM1 	= 0x55,
51 	DRWTIM1 	= 0x56,
52 	ARTTIM23 	= 0x57,
53 		ARTTIM23_DIS_RA2  = 0x04,
54 		ARTTIM23_DIS_RA3  = 0x08,
55 		ARTTIM23_INTR_CH1 = 0x10,
56 	ARTTIM2 	= 0x57,
57 	ARTTIM3 	= 0x57,
58 	DRWTIM23	= 0x58,
59 	DRWTIM2 	= 0x58,
60 	BRST 		= 0x59,
61 	DRWTIM3 	= 0x5b,
62 	BMIDECR0	= 0x70,
63 	MRDMODE		= 0x71,
64 		MRDMODE_INTR_CH0 = 0x04,
65 		MRDMODE_INTR_CH1 = 0x08,
66 		MRDMODE_BLK_CH0  = 0x10,
67 		MRDMODE_BLK_CH1	 = 0x20,
68 	BMIDESR0	= 0x72,
69 	UDIDETCR0	= 0x73,
70 	DTPR0		= 0x74,
71 	BMIDECR1	= 0x78,
72 	BMIDECSR	= 0x79,
73 	BMIDESR1	= 0x7A,
74 	UDIDETCR1	= 0x7B,
75 	DTPR1		= 0x7C
76 };
77 
78 static int cmd648_cable_detect(struct ata_port *ap)
79 {
80 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
81 	u8 r;
82 
83 	/* Check cable detect bits */
84 	pci_read_config_byte(pdev, BMIDECSR, &r);
85 	if (r & (1 << ap->port_no))
86 		return ATA_CBL_PATA80;
87 	return ATA_CBL_PATA40;
88 }
89 
90 /**
91  *	cmd64x_set_piomode	-	set PIO and MWDMA timing
92  *	@ap: ATA interface
93  *	@adev: ATA device
94  *	@mode: mode
95  *
96  *	Called to do the PIO and MWDMA mode setup.
97  */
98 
99 static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
100 {
101 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
102 	struct ata_timing t;
103 	const unsigned long T = 1000000 / 33;
104 	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
105 
106 	u8 reg;
107 
108 	/* Port layout is not logical so use a table */
109 	const u8 arttim_port[2][2] = {
110 		{ ARTTIM0, ARTTIM1 },
111 		{ ARTTIM23, ARTTIM23 }
112 	};
113 	const u8 drwtim_port[2][2] = {
114 		{ DRWTIM0, DRWTIM1 },
115 		{ DRWTIM2, DRWTIM3 }
116 	};
117 
118 	int arttim = arttim_port[ap->port_no][adev->devno];
119 	int drwtim = drwtim_port[ap->port_no][adev->devno];
120 
121 	/* ata_timing_compute is smart and will produce timings for MWDMA
122 	   that don't violate the drives PIO capabilities. */
123 	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
124 		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
125 		return;
126 	}
127 	if (ap->port_no) {
128 		/* Slave has shared address setup */
129 		struct ata_device *pair = ata_dev_pair(adev);
130 
131 		if (pair) {
132 			struct ata_timing tp;
133 			ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
134 			ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
135 		}
136 	}
137 
138 	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
139 		t.active, t.recover, t.setup);
140 	if (t.recover > 16) {
141 		t.active += t.recover - 16;
142 		t.recover = 16;
143 	}
144 	if (t.active > 16)
145 		t.active = 16;
146 
147 	/* Now convert the clocks into values we can actually stuff into
148 	   the chip */
149 
150 	if (t.recover > 1)
151 		t.recover--;
152 	else
153 		t.recover = 15;
154 
155 	if (t.setup > 4)
156 		t.setup = 0xC0;
157 	else
158 		t.setup = setup_data[t.setup];
159 
160 	t.active &= 0x0F;	/* 0 = 16 */
161 
162 	/* Load setup timing */
163 	pci_read_config_byte(pdev, arttim, &reg);
164 	reg &= 0x3F;
165 	reg |= t.setup;
166 	pci_write_config_byte(pdev, arttim, reg);
167 
168 	/* Load active/recovery */
169 	pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
170 }
171 
172 /**
173  *	cmd64x_set_piomode	-	set initial PIO mode data
174  *	@ap: ATA interface
175  *	@adev: ATA device
176  *
177  *	Used when configuring the devices ot set the PIO timings. All the
178  *	actual work is done by the PIO/MWDMA setting helper
179  */
180 
181 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
182 {
183 	cmd64x_set_timing(ap, adev, adev->pio_mode);
184 }
185 
186 /**
187  *	cmd64x_set_dmamode	-	set initial DMA mode data
188  *	@ap: ATA interface
189  *	@adev: ATA device
190  *
191  *	Called to do the DMA mode setup.
192  */
193 
194 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
195 {
196 	static const u8 udma_data[] = {
197 		0x30, 0x20, 0x10, 0x20, 0x10, 0x00
198 	};
199 
200 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
201 	u8 regU, regD;
202 
203 	int pciU = UDIDETCR0 + 8 * ap->port_no;
204 	int pciD = BMIDESR0 + 8 * ap->port_no;
205 	int shift = 2 * adev->devno;
206 
207 	pci_read_config_byte(pdev, pciD, &regD);
208 	pci_read_config_byte(pdev, pciU, &regU);
209 
210 	/* DMA bits off */
211 	regD &= ~(0x20 << adev->devno);
212 	/* DMA control bits */
213 	regU &= ~(0x30 << shift);
214 	/* DMA timing bits */
215 	regU &= ~(0x05 << adev->devno);
216 
217 	if (adev->dma_mode >= XFER_UDMA_0) {
218 		/* Merge the timing value */
219 		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
220 		/* Merge the control bits */
221 		regU |= 1 << adev->devno; /* UDMA on */
222 		if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
223 			regU |= 4 << adev->devno;
224 	} else {
225 		regU &= ~ (1 << adev->devno);	/* UDMA off */
226 		cmd64x_set_timing(ap, adev, adev->dma_mode);
227 	}
228 
229 	regD |= 0x20 << adev->devno;
230 
231 	pci_write_config_byte(pdev, pciU, regU);
232 	pci_write_config_byte(pdev, pciD, regD);
233 }
234 
235 /**
236  *	cmd648_dma_stop	-	DMA stop callback
237  *	@qc: Command in progress
238  *
239  *	DMA has completed.
240  */
241 
242 static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
243 {
244 	struct ata_port *ap = qc->ap;
245 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
246 	u8 dma_intr;
247 	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
248 	int dma_reg = ap->port_no ? ARTTIM2 : CFR;
249 
250 	ata_bmdma_stop(qc);
251 
252 	pci_read_config_byte(pdev, dma_reg, &dma_intr);
253 	pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
254 }
255 
256 /**
257  *	cmd646r1_dma_stop	-	DMA stop callback
258  *	@qc: Command in progress
259  *
260  *	Stub for now while investigating the r1 quirk in the old driver.
261  */
262 
263 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
264 {
265 	ata_bmdma_stop(qc);
266 }
267 
268 static struct scsi_host_template cmd64x_sht = {
269 	ATA_BMDMA_SHT(DRV_NAME),
270 };
271 
272 static const struct ata_port_operations cmd64x_base_ops = {
273 	.inherits	= &ata_bmdma_port_ops,
274 	.set_piomode	= cmd64x_set_piomode,
275 	.set_dmamode	= cmd64x_set_dmamode,
276 };
277 
278 static struct ata_port_operations cmd64x_port_ops = {
279 	.inherits	= &cmd64x_base_ops,
280 	.cable_detect	= ata_cable_40wire,
281 };
282 
283 static struct ata_port_operations cmd646r1_port_ops = {
284 	.inherits	= &cmd64x_base_ops,
285 	.bmdma_stop	= cmd646r1_bmdma_stop,
286 	.cable_detect	= ata_cable_40wire,
287 };
288 
289 static struct ata_port_operations cmd648_port_ops = {
290 	.inherits	= &cmd64x_base_ops,
291 	.bmdma_stop	= cmd648_bmdma_stop,
292 	.cable_detect	= cmd648_cable_detect,
293 };
294 
295 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
296 {
297 	static const struct ata_port_info cmd_info[6] = {
298 		{	/* CMD 643 - no UDMA */
299 			.flags = ATA_FLAG_SLAVE_POSS,
300 			.pio_mask = ATA_PIO4,
301 			.mwdma_mask = ATA_MWDMA2,
302 			.port_ops = &cmd64x_port_ops
303 		},
304 		{	/* CMD 646 with broken UDMA */
305 			.flags = ATA_FLAG_SLAVE_POSS,
306 			.pio_mask = ATA_PIO4,
307 			.mwdma_mask = ATA_MWDMA2,
308 			.port_ops = &cmd64x_port_ops
309 		},
310 		{	/* CMD 646 with working UDMA */
311 			.flags = ATA_FLAG_SLAVE_POSS,
312 			.pio_mask = ATA_PIO4,
313 			.mwdma_mask = ATA_MWDMA2,
314 			.udma_mask = ATA_UDMA2,
315 			.port_ops = &cmd64x_port_ops
316 		},
317 		{	/* CMD 646 rev 1  */
318 			.flags = ATA_FLAG_SLAVE_POSS,
319 			.pio_mask = ATA_PIO4,
320 			.mwdma_mask = ATA_MWDMA2,
321 			.port_ops = &cmd646r1_port_ops
322 		},
323 		{	/* CMD 648 */
324 			.flags = ATA_FLAG_SLAVE_POSS,
325 			.pio_mask = ATA_PIO4,
326 			.mwdma_mask = ATA_MWDMA2,
327 			.udma_mask = ATA_UDMA4,
328 			.port_ops = &cmd648_port_ops
329 		},
330 		{	/* CMD 649 */
331 			.flags = ATA_FLAG_SLAVE_POSS,
332 			.pio_mask = ATA_PIO4,
333 			.mwdma_mask = ATA_MWDMA2,
334 			.udma_mask = ATA_UDMA5,
335 			.port_ops = &cmd648_port_ops
336 		}
337 	};
338 	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
339 	u8 mrdmode;
340 	int rc;
341 
342 	rc = pcim_enable_device(pdev);
343 	if (rc)
344 		return rc;
345 
346 	if (id->driver_data == 0)	/* 643 */
347 		ata_pci_bmdma_clear_simplex(pdev);
348 
349 	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
350 		/* Does UDMA work ? */
351 		if (pdev->revision > 4)
352 			ppi[0] = &cmd_info[2];
353 		/* Early rev with other problems ? */
354 		else if (pdev->revision == 1)
355 			ppi[0] = &cmd_info[3];
356 	}
357 
358 	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
359 	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
360 	mrdmode &= ~ 0x30;	/* IRQ set up */
361 	mrdmode |= 0x02;	/* Memory read line enable */
362 	pci_write_config_byte(pdev, MRDMODE, mrdmode);
363 
364 	/* Force PIO 0 here.. */
365 
366 	/* PPC specific fixup copied from old driver */
367 #ifdef CONFIG_PPC
368 	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
369 #endif
370 
371 	return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL);
372 }
373 
374 #ifdef CONFIG_PM
375 static int cmd64x_reinit_one(struct pci_dev *pdev)
376 {
377 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
378 	u8 mrdmode;
379 	int rc;
380 
381 	rc = ata_pci_device_do_resume(pdev);
382 	if (rc)
383 		return rc;
384 
385 	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
386 	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
387 	mrdmode &= ~ 0x30;	/* IRQ set up */
388 	mrdmode |= 0x02;	/* Memory read line enable */
389 	pci_write_config_byte(pdev, MRDMODE, mrdmode);
390 #ifdef CONFIG_PPC
391 	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
392 #endif
393 	ata_host_resume(host);
394 	return 0;
395 }
396 #endif
397 
398 static const struct pci_device_id cmd64x[] = {
399 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
400 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
401 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
402 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
403 
404 	{ },
405 };
406 
407 static struct pci_driver cmd64x_pci_driver = {
408 	.name 		= DRV_NAME,
409 	.id_table	= cmd64x,
410 	.probe 		= cmd64x_init_one,
411 	.remove		= ata_pci_remove_one,
412 #ifdef CONFIG_PM
413 	.suspend	= ata_pci_device_suspend,
414 	.resume		= cmd64x_reinit_one,
415 #endif
416 };
417 
418 static int __init cmd64x_init(void)
419 {
420 	return pci_register_driver(&cmd64x_pci_driver);
421 }
422 
423 static void __exit cmd64x_exit(void)
424 {
425 	pci_unregister_driver(&cmd64x_pci_driver);
426 }
427 
428 MODULE_AUTHOR("Alan Cox");
429 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
430 MODULE_LICENSE("GPL");
431 MODULE_DEVICE_TABLE(pci, cmd64x);
432 MODULE_VERSION(DRV_VERSION);
433 
434 module_init(cmd64x_init);
435 module_exit(cmd64x_exit);
436