1 /* 2 * pata_cmd64x.c - CMD64x PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@lxorguk.ukuu.org.uk> 5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz 6 * 7 * Based upon 8 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 9 * 10 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. 11 * Note, this driver is not used at all on other systems because 12 * there the "BIOS" has done all of the following already. 13 * Due to massive hardware bugs, UltraDMA is only supported 14 * on the 646U2 and not on the 646U. 15 * 16 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 17 * Copyright (C) 1998 David S. Miller (davem@redhat.com) 18 * 19 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 20 * 21 * TODO 22 * Testing work 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include <linux/init.h> 29 #include <linux/blkdev.h> 30 #include <linux/delay.h> 31 #include <scsi/scsi_host.h> 32 #include <linux/libata.h> 33 34 #define DRV_NAME "pata_cmd64x" 35 #define DRV_VERSION "0.2.5" 36 37 /* 38 * CMD64x specific registers definition. 39 */ 40 41 enum { 42 CFR = 0x50, 43 CFR_INTR_CH0 = 0x04, 44 CMDTIM = 0x52, 45 ARTTIM0 = 0x53, 46 DRWTIM0 = 0x54, 47 ARTTIM1 = 0x55, 48 DRWTIM1 = 0x56, 49 ARTTIM23 = 0x57, 50 ARTTIM23_DIS_RA2 = 0x04, 51 ARTTIM23_DIS_RA3 = 0x08, 52 ARTTIM23_INTR_CH1 = 0x10, 53 DRWTIM2 = 0x58, 54 BRST = 0x59, 55 DRWTIM3 = 0x5b, 56 BMIDECR0 = 0x70, 57 MRDMODE = 0x71, 58 MRDMODE_INTR_CH0 = 0x04, 59 MRDMODE_INTR_CH1 = 0x08, 60 BMIDESR0 = 0x72, 61 UDIDETCR0 = 0x73, 62 DTPR0 = 0x74, 63 BMIDECR1 = 0x78, 64 BMIDECSR = 0x79, 65 UDIDETCR1 = 0x7B, 66 DTPR1 = 0x7C 67 }; 68 69 static int cmd648_cable_detect(struct ata_port *ap) 70 { 71 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 72 u8 r; 73 74 /* Check cable detect bits */ 75 pci_read_config_byte(pdev, BMIDECSR, &r); 76 if (r & (1 << ap->port_no)) 77 return ATA_CBL_PATA80; 78 return ATA_CBL_PATA40; 79 } 80 81 /** 82 * cmd64x_set_piomode - set PIO and MWDMA timing 83 * @ap: ATA interface 84 * @adev: ATA device 85 * @mode: mode 86 * 87 * Called to do the PIO and MWDMA mode setup. 88 */ 89 90 static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) 91 { 92 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 93 struct ata_timing t; 94 const unsigned long T = 1000000 / 33; 95 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; 96 97 u8 reg; 98 99 /* Port layout is not logical so use a table */ 100 const u8 arttim_port[2][2] = { 101 { ARTTIM0, ARTTIM1 }, 102 { ARTTIM23, ARTTIM23 } 103 }; 104 const u8 drwtim_port[2][2] = { 105 { DRWTIM0, DRWTIM1 }, 106 { DRWTIM2, DRWTIM3 } 107 }; 108 109 int arttim = arttim_port[ap->port_no][adev->devno]; 110 int drwtim = drwtim_port[ap->port_no][adev->devno]; 111 112 /* ata_timing_compute is smart and will produce timings for MWDMA 113 that don't violate the drives PIO capabilities. */ 114 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { 115 printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); 116 return; 117 } 118 if (ap->port_no) { 119 /* Slave has shared address setup */ 120 struct ata_device *pair = ata_dev_pair(adev); 121 122 if (pair) { 123 struct ata_timing tp; 124 125 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); 126 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 127 if (pair->dma_mode) { 128 ata_timing_compute(pair, pair->dma_mode, 129 &tp, T, 0); 130 ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP); 131 } 132 } 133 } 134 135 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", 136 t.active, t.recover, t.setup); 137 if (t.recover > 16) { 138 t.active += t.recover - 16; 139 t.recover = 16; 140 } 141 if (t.active > 16) 142 t.active = 16; 143 144 /* Now convert the clocks into values we can actually stuff into 145 the chip */ 146 147 if (t.recover == 16) 148 t.recover = 0; 149 else if (t.recover > 1) 150 t.recover--; 151 else 152 t.recover = 15; 153 154 if (t.setup > 4) 155 t.setup = 0xC0; 156 else 157 t.setup = setup_data[t.setup]; 158 159 t.active &= 0x0F; /* 0 = 16 */ 160 161 /* Load setup timing */ 162 pci_read_config_byte(pdev, arttim, ®); 163 reg &= 0x3F; 164 reg |= t.setup; 165 pci_write_config_byte(pdev, arttim, reg); 166 167 /* Load active/recovery */ 168 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); 169 } 170 171 /** 172 * cmd64x_set_piomode - set initial PIO mode data 173 * @ap: ATA interface 174 * @adev: ATA device 175 * 176 * Used when configuring the devices ot set the PIO timings. All the 177 * actual work is done by the PIO/MWDMA setting helper 178 */ 179 180 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) 181 { 182 cmd64x_set_timing(ap, adev, adev->pio_mode); 183 } 184 185 /** 186 * cmd64x_set_dmamode - set initial DMA mode data 187 * @ap: ATA interface 188 * @adev: ATA device 189 * 190 * Called to do the DMA mode setup. 191 */ 192 193 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 194 { 195 static const u8 udma_data[] = { 196 0x30, 0x20, 0x10, 0x20, 0x10, 0x00 197 }; 198 199 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 200 u8 regU, regD; 201 202 int pciU = UDIDETCR0 + 8 * ap->port_no; 203 int pciD = BMIDESR0 + 8 * ap->port_no; 204 int shift = 2 * adev->devno; 205 206 pci_read_config_byte(pdev, pciD, ®D); 207 pci_read_config_byte(pdev, pciU, ®U); 208 209 /* DMA bits off */ 210 regD &= ~(0x20 << adev->devno); 211 /* DMA control bits */ 212 regU &= ~(0x30 << shift); 213 /* DMA timing bits */ 214 regU &= ~(0x05 << adev->devno); 215 216 if (adev->dma_mode >= XFER_UDMA_0) { 217 /* Merge the timing value */ 218 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; 219 /* Merge the control bits */ 220 regU |= 1 << adev->devno; /* UDMA on */ 221 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */ 222 regU |= 4 << adev->devno; 223 } else { 224 regU &= ~ (1 << adev->devno); /* UDMA off */ 225 cmd64x_set_timing(ap, adev, adev->dma_mode); 226 } 227 228 regD |= 0x20 << adev->devno; 229 230 pci_write_config_byte(pdev, pciU, regU); 231 pci_write_config_byte(pdev, pciD, regD); 232 } 233 234 /** 235 * cmd648_dma_stop - DMA stop callback 236 * @qc: Command in progress 237 * 238 * DMA has completed. 239 */ 240 241 static void cmd648_bmdma_stop(struct ata_queued_cmd *qc) 242 { 243 struct ata_port *ap = qc->ap; 244 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 245 u8 dma_intr; 246 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; 247 int dma_reg = ap->port_no ? ARTTIM23 : CFR; 248 249 ata_bmdma_stop(qc); 250 251 pci_read_config_byte(pdev, dma_reg, &dma_intr); 252 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask); 253 } 254 255 /** 256 * cmd646r1_dma_stop - DMA stop callback 257 * @qc: Command in progress 258 * 259 * Stub for now while investigating the r1 quirk in the old driver. 260 */ 261 262 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) 263 { 264 ata_bmdma_stop(qc); 265 } 266 267 static struct scsi_host_template cmd64x_sht = { 268 ATA_BMDMA_SHT(DRV_NAME), 269 }; 270 271 static const struct ata_port_operations cmd64x_base_ops = { 272 .inherits = &ata_bmdma_port_ops, 273 .set_piomode = cmd64x_set_piomode, 274 .set_dmamode = cmd64x_set_dmamode, 275 }; 276 277 static struct ata_port_operations cmd64x_port_ops = { 278 .inherits = &cmd64x_base_ops, 279 .cable_detect = ata_cable_40wire, 280 }; 281 282 static struct ata_port_operations cmd646r1_port_ops = { 283 .inherits = &cmd64x_base_ops, 284 .bmdma_stop = cmd646r1_bmdma_stop, 285 .cable_detect = ata_cable_40wire, 286 }; 287 288 static struct ata_port_operations cmd648_port_ops = { 289 .inherits = &cmd64x_base_ops, 290 .bmdma_stop = cmd648_bmdma_stop, 291 .cable_detect = cmd648_cable_detect, 292 }; 293 294 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 295 { 296 static const struct ata_port_info cmd_info[6] = { 297 { /* CMD 643 - no UDMA */ 298 .flags = ATA_FLAG_SLAVE_POSS, 299 .pio_mask = ATA_PIO4, 300 .mwdma_mask = ATA_MWDMA2, 301 .port_ops = &cmd64x_port_ops 302 }, 303 { /* CMD 646 with broken UDMA */ 304 .flags = ATA_FLAG_SLAVE_POSS, 305 .pio_mask = ATA_PIO4, 306 .mwdma_mask = ATA_MWDMA2, 307 .port_ops = &cmd64x_port_ops 308 }, 309 { /* CMD 646 with working UDMA */ 310 .flags = ATA_FLAG_SLAVE_POSS, 311 .pio_mask = ATA_PIO4, 312 .mwdma_mask = ATA_MWDMA2, 313 .udma_mask = ATA_UDMA2, 314 .port_ops = &cmd64x_port_ops 315 }, 316 { /* CMD 646 rev 1 */ 317 .flags = ATA_FLAG_SLAVE_POSS, 318 .pio_mask = ATA_PIO4, 319 .mwdma_mask = ATA_MWDMA2, 320 .port_ops = &cmd646r1_port_ops 321 }, 322 { /* CMD 648 */ 323 .flags = ATA_FLAG_SLAVE_POSS, 324 .pio_mask = ATA_PIO4, 325 .mwdma_mask = ATA_MWDMA2, 326 .udma_mask = ATA_UDMA4, 327 .port_ops = &cmd648_port_ops 328 }, 329 { /* CMD 649 */ 330 .flags = ATA_FLAG_SLAVE_POSS, 331 .pio_mask = ATA_PIO4, 332 .mwdma_mask = ATA_MWDMA2, 333 .udma_mask = ATA_UDMA5, 334 .port_ops = &cmd648_port_ops 335 } 336 }; 337 const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL }; 338 u8 mrdmode; 339 int rc; 340 341 rc = pcim_enable_device(pdev); 342 if (rc) 343 return rc; 344 345 if (id->driver_data == 0) /* 643 */ 346 ata_pci_bmdma_clear_simplex(pdev); 347 348 if (pdev->device == PCI_DEVICE_ID_CMD_646) { 349 /* Does UDMA work ? */ 350 if (pdev->revision > 4) 351 ppi[0] = &cmd_info[2]; 352 /* Early rev with other problems ? */ 353 else if (pdev->revision == 1) 354 ppi[0] = &cmd_info[3]; 355 } 356 357 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 358 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 359 mrdmode &= ~ 0x30; /* IRQ set up */ 360 mrdmode |= 0x02; /* Memory read line enable */ 361 pci_write_config_byte(pdev, MRDMODE, mrdmode); 362 363 /* Force PIO 0 here.. */ 364 365 /* PPC specific fixup copied from old driver */ 366 #ifdef CONFIG_PPC 367 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 368 #endif 369 370 return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL, 0); 371 } 372 373 #ifdef CONFIG_PM 374 static int cmd64x_reinit_one(struct pci_dev *pdev) 375 { 376 struct ata_host *host = dev_get_drvdata(&pdev->dev); 377 u8 mrdmode; 378 int rc; 379 380 rc = ata_pci_device_do_resume(pdev); 381 if (rc) 382 return rc; 383 384 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 385 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 386 mrdmode &= ~ 0x30; /* IRQ set up */ 387 mrdmode |= 0x02; /* Memory read line enable */ 388 pci_write_config_byte(pdev, MRDMODE, mrdmode); 389 #ifdef CONFIG_PPC 390 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 391 #endif 392 ata_host_resume(host); 393 return 0; 394 } 395 #endif 396 397 static const struct pci_device_id cmd64x[] = { 398 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, 399 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, 400 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 }, 401 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 }, 402 403 { }, 404 }; 405 406 static struct pci_driver cmd64x_pci_driver = { 407 .name = DRV_NAME, 408 .id_table = cmd64x, 409 .probe = cmd64x_init_one, 410 .remove = ata_pci_remove_one, 411 #ifdef CONFIG_PM 412 .suspend = ata_pci_device_suspend, 413 .resume = cmd64x_reinit_one, 414 #endif 415 }; 416 417 static int __init cmd64x_init(void) 418 { 419 return pci_register_driver(&cmd64x_pci_driver); 420 } 421 422 static void __exit cmd64x_exit(void) 423 { 424 pci_unregister_driver(&cmd64x_pci_driver); 425 } 426 427 MODULE_AUTHOR("Alan Cox"); 428 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); 429 MODULE_LICENSE("GPL"); 430 MODULE_DEVICE_TABLE(pci, cmd64x); 431 MODULE_VERSION(DRV_VERSION); 432 433 module_init(cmd64x_init); 434 module_exit(cmd64x_exit); 435